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gerrit-public.fairphone.software / kernel / msm-4.19 / 22c6d93a73105fddd58796d7cb10f5f90ee2a338 / . / drivers / net / fec.h
blob: c6e4f979ff5d42a9942d3c1ab57182dfb7935bd1 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/****************************************************************************/
2
3/*
4 * fec.h -- Fast Ethernet Controller for Motorola ColdFire 5270,
5 5271, 5272, 5274, 5275, 5280 and 5282.
6 *
7 * (C) Copyright 2000-2003, Greg Ungerer (gerg@snapgear.com)
8 * (C) Copyright 2000-2001, Lineo (www.lineo.com)
9 */
10
11/****************************************************************************/
12#ifndef FEC_H
13#define FEC_H
14/****************************************************************************/
15
16#if defined(CONFIG_M527x) || defined(CONFIG_M528x)
17/*
18 * Just figures, Motorola would have to change the offsets for
19 * registers in the same peripheral device on different models
20 * of the ColdFire!
21 */
22typedef struct fec {
23 unsigned long fec_reserved0;
24 unsigned long fec_ievent; /* Interrupt event reg */
25 unsigned long fec_imask; /* Interrupt mask reg */
26 unsigned long fec_reserved1;
27 unsigned long fec_r_des_active; /* Receive descriptor reg */
28 unsigned long fec_x_des_active; /* Transmit descriptor reg */
29 unsigned long fec_reserved2[3];
30 unsigned long fec_ecntrl; /* Ethernet control reg */
31 unsigned long fec_reserved3[6];
32 unsigned long fec_mii_data; /* MII manage frame reg */
33 unsigned long fec_mii_speed; /* MII speed control reg */
34 unsigned long fec_reserved4[7];
35 unsigned long fec_mib_ctrlstat; /* MIB control/status reg */
36 unsigned long fec_reserved5[7];
37 unsigned long fec_r_cntrl; /* Receive control reg */
38 unsigned long fec_reserved6[15];
39 unsigned long fec_x_cntrl; /* Transmit Control reg */
40 unsigned long fec_reserved7[7];
41 unsigned long fec_addr_low; /* Low 32bits MAC address */
42 unsigned long fec_addr_high; /* High 16bits MAC address */
43 unsigned long fec_opd; /* Opcode + Pause duration */
44 unsigned long fec_reserved8[10];
45 unsigned long fec_hash_table_high; /* High 32bits hash table */
46 unsigned long fec_hash_table_low; /* Low 32bits hash table */
47 unsigned long fec_grp_hash_table_high;/* High 32bits hash table */
48 unsigned long fec_grp_hash_table_low; /* Low 32bits hash table */
49 unsigned long fec_reserved9[7];
50 unsigned long fec_x_wmrk; /* FIFO transmit water mark */
51 unsigned long fec_reserved10;
52 unsigned long fec_r_bound; /* FIFO receive bound reg */
53 unsigned long fec_r_fstart; /* FIFO receive start reg */
54 unsigned long fec_reserved11[11];
55 unsigned long fec_r_des_start; /* Receive descriptor ring */
56 unsigned long fec_x_des_start; /* Transmit descriptor ring */
57 unsigned long fec_r_buff_size; /* Maximum receive buff size */
58} fec_t;
59
60#else
61
62/*
63 * Define device register set address map.
64 */
65typedef struct fec {
66 unsigned long fec_ecntrl; /* Ethernet control reg */
67 unsigned long fec_ievent; /* Interrupt even reg */
68 unsigned long fec_imask; /* Interrupt mask reg */
69 unsigned long fec_ivec; /* Interrupt vec status reg */
70 unsigned long fec_r_des_active; /* Receive descriptor reg */
71 unsigned long fec_x_des_active; /* Transmit descriptor reg */
72 unsigned long fec_reserved1[10];
73 unsigned long fec_mii_data; /* MII manage frame reg */
74 unsigned long fec_mii_speed; /* MII speed control reg */
75 unsigned long fec_reserved2[17];
76 unsigned long fec_r_bound; /* FIFO receive bound reg */
77 unsigned long fec_r_fstart; /* FIFO receive start reg */
78 unsigned long fec_reserved3[4];
79 unsigned long fec_x_wmrk; /* FIFO transmit water mark */
80 unsigned long fec_reserved4;
81 unsigned long fec_x_fstart; /* FIFO transmit start reg */
82 unsigned long fec_reserved5[21];
83 unsigned long fec_r_cntrl; /* Receive control reg */
84 unsigned long fec_max_frm_len; /* Maximum frame length reg */
85 unsigned long fec_reserved6[14];
86 unsigned long fec_x_cntrl; /* Transmit Control reg */
87 unsigned long fec_reserved7[158];
88 unsigned long fec_addr_low; /* Low 32bits MAC address */
89 unsigned long fec_addr_high; /* High 16bits MAC address */
90 unsigned long fec_hash_table_high; /* High 32bits hash table */
91 unsigned long fec_hash_table_low; /* Low 32bits hash table */
92 unsigned long fec_r_des_start; /* Receive descriptor ring */
93 unsigned long fec_x_des_start; /* Transmit descriptor ring */
94 unsigned long fec_r_buff_size; /* Maximum receive buff size */
95 unsigned long reserved8[9];
96 unsigned long fec_fifo_ram[112]; /* FIFO RAM buffer */
97} fec_t;
98
99#endif /* CONFIG_M5272 */
100
101
102/*
103 * Define the buffer descriptor structure.
104 */
105typedef struct bufdesc {
106 unsigned short cbd_sc; /* Control and status info */
107 unsigned short cbd_datlen; /* Data length */
108 unsigned long cbd_bufaddr; /* Buffer address */
109} cbd_t;
110
111
112/*
113 * The following definitions courtesy of commproc.h, which where
114 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
115 */
116#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
117#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
118#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
119#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
120#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
121#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
122#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
123#define BD_SC_BR ((ushort)0x0020) /* Break received */
124#define BD_SC_FR ((ushort)0x0010) /* Framing error */
125#define BD_SC_PR ((ushort)0x0008) /* Parity error */
126#define BD_SC_OV ((ushort)0x0002) /* Overrun */
127#define BD_SC_CD ((ushort)0x0001) /* ?? */
128
129/* Buffer descriptor control/status used by Ethernet receive.
130*/
131#define BD_ENET_RX_EMPTY ((ushort)0x8000)
132#define BD_ENET_RX_WRAP ((ushort)0x2000)
133#define BD_ENET_RX_INTR ((ushort)0x1000)
134#define BD_ENET_RX_LAST ((ushort)0x0800)
135#define BD_ENET_RX_FIRST ((ushort)0x0400)
136#define BD_ENET_RX_MISS ((ushort)0x0100)
137#define BD_ENET_RX_LG ((ushort)0x0020)
138#define BD_ENET_RX_NO ((ushort)0x0010)
139#define BD_ENET_RX_SH ((ushort)0x0008)
140#define BD_ENET_RX_CR ((ushort)0x0004)
141#define BD_ENET_RX_OV ((ushort)0x0002)
142#define BD_ENET_RX_CL ((ushort)0x0001)
143#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
144
145/* Buffer descriptor control/status used by Ethernet transmit.
146*/
147#define BD_ENET_TX_READY ((ushort)0x8000)
148#define BD_ENET_TX_PAD ((ushort)0x4000)
149#define BD_ENET_TX_WRAP ((ushort)0x2000)
150#define BD_ENET_TX_INTR ((ushort)0x1000)
151#define BD_ENET_TX_LAST ((ushort)0x0800)
152#define BD_ENET_TX_TC ((ushort)0x0400)
153#define BD_ENET_TX_DEF ((ushort)0x0200)
154#define BD_ENET_TX_HB ((ushort)0x0100)
155#define BD_ENET_TX_LC ((ushort)0x0080)
156#define BD_ENET_TX_RL ((ushort)0x0040)
157#define BD_ENET_TX_RCMASK ((ushort)0x003c)
158#define BD_ENET_TX_UN ((ushort)0x0002)
159#define BD_ENET_TX_CSL ((ushort)0x0001)
160#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
161
162
163/****************************************************************************/
164#endif /* FEC_H */