Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1 | /* |
| 2 | * MTK NAND Flash controller driver. |
| 3 | * Copyright (C) 2016 MediaTek Inc. |
| 4 | * Authors: Xiaolei Li <xiaolei.li@mediatek.com> |
| 5 | * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/dma-mapping.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/clk.h> |
| 22 | #include <linux/mtd/nand.h> |
| 23 | #include <linux/mtd/mtd.h> |
| 24 | #include <linux/module.h> |
| 25 | #include <linux/iopoll.h> |
| 26 | #include <linux/of.h> |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 27 | #include <linux/of_device.h> |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 28 | #include "mtk_ecc.h" |
| 29 | |
| 30 | /* NAND controller register definition */ |
| 31 | #define NFI_CNFG (0x00) |
| 32 | #define CNFG_AHB BIT(0) |
| 33 | #define CNFG_READ_EN BIT(1) |
| 34 | #define CNFG_DMA_BURST_EN BIT(2) |
| 35 | #define CNFG_BYTE_RW BIT(6) |
| 36 | #define CNFG_HW_ECC_EN BIT(8) |
| 37 | #define CNFG_AUTO_FMT_EN BIT(9) |
| 38 | #define CNFG_OP_CUST (6 << 12) |
| 39 | #define NFI_PAGEFMT (0x04) |
| 40 | #define PAGEFMT_FDM_ECC_SHIFT (12) |
| 41 | #define PAGEFMT_FDM_SHIFT (8) |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 42 | #define PAGEFMT_SEC_SEL_512 BIT(2) |
| 43 | #define PAGEFMT_512_2K (0) |
| 44 | #define PAGEFMT_2K_4K (1) |
| 45 | #define PAGEFMT_4K_8K (2) |
| 46 | #define PAGEFMT_8K_16K (3) |
| 47 | /* NFI control */ |
| 48 | #define NFI_CON (0x08) |
| 49 | #define CON_FIFO_FLUSH BIT(0) |
| 50 | #define CON_NFI_RST BIT(1) |
| 51 | #define CON_BRD BIT(8) /* burst read */ |
| 52 | #define CON_BWR BIT(9) /* burst write */ |
| 53 | #define CON_SEC_SHIFT (12) |
| 54 | /* Timming control register */ |
| 55 | #define NFI_ACCCON (0x0C) |
| 56 | #define NFI_INTR_EN (0x10) |
| 57 | #define INTR_AHB_DONE_EN BIT(6) |
| 58 | #define NFI_INTR_STA (0x14) |
| 59 | #define NFI_CMD (0x20) |
| 60 | #define NFI_ADDRNOB (0x30) |
| 61 | #define NFI_COLADDR (0x34) |
| 62 | #define NFI_ROWADDR (0x38) |
| 63 | #define NFI_STRDATA (0x40) |
| 64 | #define STAR_EN (1) |
| 65 | #define STAR_DE (0) |
| 66 | #define NFI_CNRNB (0x44) |
| 67 | #define NFI_DATAW (0x50) |
| 68 | #define NFI_DATAR (0x54) |
| 69 | #define NFI_PIO_DIRDY (0x58) |
| 70 | #define PIO_DI_RDY (0x01) |
| 71 | #define NFI_STA (0x60) |
| 72 | #define STA_CMD BIT(0) |
| 73 | #define STA_ADDR BIT(1) |
| 74 | #define STA_BUSY BIT(8) |
| 75 | #define STA_EMP_PAGE BIT(12) |
| 76 | #define NFI_FSM_CUSTDATA (0xe << 16) |
| 77 | #define NFI_FSM_MASK (0xf << 16) |
| 78 | #define NFI_ADDRCNTR (0x70) |
| 79 | #define CNTR_MASK GENMASK(16, 12) |
RogerCC Lin | 559e58e | 2016-09-19 10:53:26 +0800 | [diff] [blame] | 80 | #define ADDRCNTR_SEC_SHIFT (12) |
| 81 | #define ADDRCNTR_SEC(val) \ |
| 82 | (((val) & CNTR_MASK) >> ADDRCNTR_SEC_SHIFT) |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 83 | #define NFI_STRADDR (0x80) |
| 84 | #define NFI_BYTELEN (0x84) |
| 85 | #define NFI_CSEL (0x90) |
| 86 | #define NFI_FDML(x) (0xA0 + (x) * sizeof(u32) * 2) |
| 87 | #define NFI_FDMM(x) (0xA4 + (x) * sizeof(u32) * 2) |
| 88 | #define NFI_FDM_MAX_SIZE (8) |
| 89 | #define NFI_FDM_MIN_SIZE (1) |
| 90 | #define NFI_MASTER_STA (0x224) |
| 91 | #define MASTER_STA_MASK (0x0FFF) |
| 92 | #define NFI_EMPTY_THRESH (0x23C) |
| 93 | |
| 94 | #define MTK_NAME "mtk-nand" |
| 95 | #define KB(x) ((x) * 1024UL) |
| 96 | #define MB(x) (KB(x) * 1024UL) |
| 97 | |
| 98 | #define MTK_TIMEOUT (500000) |
| 99 | #define MTK_RESET_TIMEOUT (1000000) |
| 100 | #define MTK_MAX_SECTOR (16) |
| 101 | #define MTK_NAND_MAX_NSELS (2) |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 102 | #define MTK_NFC_MIN_SPARE (16) |
Xiaolei Li | edfee36 | 2017-06-23 15:12:28 +0800 | [diff] [blame] | 103 | #define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \ |
| 104 | ((tpoecs) << 28 | (tprecs) << 22 | (tc2r) << 16 | \ |
| 105 | (tw2r) << 12 | (twh) << 8 | (twst) << 4 | (trlt)) |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 106 | |
| 107 | struct mtk_nfc_caps { |
| 108 | const u8 *spare_size; |
| 109 | u8 num_spare_size; |
| 110 | u8 pageformat_spare_shift; |
Xiaolei Li | edfee36 | 2017-06-23 15:12:28 +0800 | [diff] [blame] | 111 | u8 nfi_clk_div; |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 112 | }; |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 113 | |
| 114 | struct mtk_nfc_bad_mark_ctl { |
| 115 | void (*bm_swap)(struct mtd_info *, u8 *buf, int raw); |
| 116 | u32 sec; |
| 117 | u32 pos; |
| 118 | }; |
| 119 | |
| 120 | /* |
| 121 | * FDM: region used to store free OOB data |
| 122 | */ |
| 123 | struct mtk_nfc_fdm { |
| 124 | u32 reg_size; |
| 125 | u32 ecc_size; |
| 126 | }; |
| 127 | |
| 128 | struct mtk_nfc_nand_chip { |
| 129 | struct list_head node; |
| 130 | struct nand_chip nand; |
| 131 | |
| 132 | struct mtk_nfc_bad_mark_ctl bad_mark; |
| 133 | struct mtk_nfc_fdm fdm; |
| 134 | u32 spare_per_sector; |
| 135 | |
| 136 | int nsels; |
| 137 | u8 sels[0]; |
| 138 | /* nothing after this field */ |
| 139 | }; |
| 140 | |
| 141 | struct mtk_nfc_clk { |
| 142 | struct clk *nfi_clk; |
| 143 | struct clk *pad_clk; |
| 144 | }; |
| 145 | |
| 146 | struct mtk_nfc { |
| 147 | struct nand_hw_control controller; |
| 148 | struct mtk_ecc_config ecc_cfg; |
| 149 | struct mtk_nfc_clk clk; |
| 150 | struct mtk_ecc *ecc; |
| 151 | |
| 152 | struct device *dev; |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 153 | const struct mtk_nfc_caps *caps; |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 154 | void __iomem *regs; |
| 155 | |
| 156 | struct completion done; |
| 157 | struct list_head chips; |
| 158 | |
| 159 | u8 *buffer; |
| 160 | }; |
| 161 | |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 162 | /* |
| 163 | * supported spare size of each IP. |
| 164 | * order should be the same with the spare size bitfiled defination of |
| 165 | * register NFI_PAGEFMT. |
| 166 | */ |
| 167 | static const u8 spare_size_mt2701[] = { |
| 168 | 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 63, 64 |
| 169 | }; |
| 170 | |
Xiaolei Li | 30ee809 | 2017-05-31 16:26:41 +0800 | [diff] [blame] | 171 | static const u8 spare_size_mt2712[] = { |
| 172 | 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, 67, |
| 173 | 74 |
| 174 | }; |
| 175 | |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 176 | static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand) |
| 177 | { |
| 178 | return container_of(nand, struct mtk_nfc_nand_chip, nand); |
| 179 | } |
| 180 | |
| 181 | static inline u8 *data_ptr(struct nand_chip *chip, const u8 *p, int i) |
| 182 | { |
| 183 | return (u8 *)p + i * chip->ecc.size; |
| 184 | } |
| 185 | |
| 186 | static inline u8 *oob_ptr(struct nand_chip *chip, int i) |
| 187 | { |
| 188 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); |
| 189 | u8 *poi; |
| 190 | |
| 191 | /* map the sector's FDM data to free oob: |
| 192 | * the beginning of the oob area stores the FDM data of bad mark sectors |
| 193 | */ |
| 194 | |
| 195 | if (i < mtk_nand->bad_mark.sec) |
| 196 | poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size; |
| 197 | else if (i == mtk_nand->bad_mark.sec) |
| 198 | poi = chip->oob_poi; |
| 199 | else |
| 200 | poi = chip->oob_poi + i * mtk_nand->fdm.reg_size; |
| 201 | |
| 202 | return poi; |
| 203 | } |
| 204 | |
| 205 | static inline int mtk_data_len(struct nand_chip *chip) |
| 206 | { |
| 207 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); |
| 208 | |
| 209 | return chip->ecc.size + mtk_nand->spare_per_sector; |
| 210 | } |
| 211 | |
| 212 | static inline u8 *mtk_data_ptr(struct nand_chip *chip, int i) |
| 213 | { |
| 214 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 215 | |
| 216 | return nfc->buffer + i * mtk_data_len(chip); |
| 217 | } |
| 218 | |
| 219 | static inline u8 *mtk_oob_ptr(struct nand_chip *chip, int i) |
| 220 | { |
| 221 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 222 | |
| 223 | return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size; |
| 224 | } |
| 225 | |
| 226 | static inline void nfi_writel(struct mtk_nfc *nfc, u32 val, u32 reg) |
| 227 | { |
| 228 | writel(val, nfc->regs + reg); |
| 229 | } |
| 230 | |
| 231 | static inline void nfi_writew(struct mtk_nfc *nfc, u16 val, u32 reg) |
| 232 | { |
| 233 | writew(val, nfc->regs + reg); |
| 234 | } |
| 235 | |
| 236 | static inline void nfi_writeb(struct mtk_nfc *nfc, u8 val, u32 reg) |
| 237 | { |
| 238 | writeb(val, nfc->regs + reg); |
| 239 | } |
| 240 | |
| 241 | static inline u32 nfi_readl(struct mtk_nfc *nfc, u32 reg) |
| 242 | { |
| 243 | return readl_relaxed(nfc->regs + reg); |
| 244 | } |
| 245 | |
| 246 | static inline u16 nfi_readw(struct mtk_nfc *nfc, u32 reg) |
| 247 | { |
| 248 | return readw_relaxed(nfc->regs + reg); |
| 249 | } |
| 250 | |
| 251 | static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg) |
| 252 | { |
| 253 | return readb_relaxed(nfc->regs + reg); |
| 254 | } |
| 255 | |
| 256 | static void mtk_nfc_hw_reset(struct mtk_nfc *nfc) |
| 257 | { |
| 258 | struct device *dev = nfc->dev; |
| 259 | u32 val; |
| 260 | int ret; |
| 261 | |
| 262 | /* reset all registers and force the NFI master to terminate */ |
| 263 | nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON); |
| 264 | |
| 265 | /* wait for the master to finish the last transaction */ |
| 266 | ret = readl_poll_timeout(nfc->regs + NFI_MASTER_STA, val, |
| 267 | !(val & MASTER_STA_MASK), 50, |
| 268 | MTK_RESET_TIMEOUT); |
| 269 | if (ret) |
| 270 | dev_warn(dev, "master active in reset [0x%x] = 0x%x\n", |
| 271 | NFI_MASTER_STA, val); |
| 272 | |
| 273 | /* ensure any status register affected by the NFI master is reset */ |
| 274 | nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON); |
| 275 | nfi_writew(nfc, STAR_DE, NFI_STRDATA); |
| 276 | } |
| 277 | |
| 278 | static int mtk_nfc_send_command(struct mtk_nfc *nfc, u8 command) |
| 279 | { |
| 280 | struct device *dev = nfc->dev; |
| 281 | u32 val; |
| 282 | int ret; |
| 283 | |
| 284 | nfi_writel(nfc, command, NFI_CMD); |
| 285 | |
| 286 | ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val, |
| 287 | !(val & STA_CMD), 10, MTK_TIMEOUT); |
| 288 | if (ret) { |
| 289 | dev_warn(dev, "nfi core timed out entering command mode\n"); |
| 290 | return -EIO; |
| 291 | } |
| 292 | |
| 293 | return 0; |
| 294 | } |
| 295 | |
| 296 | static int mtk_nfc_send_address(struct mtk_nfc *nfc, int addr) |
| 297 | { |
| 298 | struct device *dev = nfc->dev; |
| 299 | u32 val; |
| 300 | int ret; |
| 301 | |
| 302 | nfi_writel(nfc, addr, NFI_COLADDR); |
| 303 | nfi_writel(nfc, 0, NFI_ROWADDR); |
| 304 | nfi_writew(nfc, 1, NFI_ADDRNOB); |
| 305 | |
| 306 | ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val, |
| 307 | !(val & STA_ADDR), 10, MTK_TIMEOUT); |
| 308 | if (ret) { |
| 309 | dev_warn(dev, "nfi core timed out entering address mode\n"); |
| 310 | return -EIO; |
| 311 | } |
| 312 | |
| 313 | return 0; |
| 314 | } |
| 315 | |
| 316 | static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd) |
| 317 | { |
| 318 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 319 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); |
| 320 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 321 | u32 fmt, spare, i; |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 322 | |
| 323 | if (!mtd->writesize) |
| 324 | return 0; |
| 325 | |
| 326 | spare = mtk_nand->spare_per_sector; |
| 327 | |
| 328 | switch (mtd->writesize) { |
| 329 | case 512: |
| 330 | fmt = PAGEFMT_512_2K | PAGEFMT_SEC_SEL_512; |
| 331 | break; |
| 332 | case KB(2): |
| 333 | if (chip->ecc.size == 512) |
| 334 | fmt = PAGEFMT_2K_4K | PAGEFMT_SEC_SEL_512; |
| 335 | else |
| 336 | fmt = PAGEFMT_512_2K; |
| 337 | break; |
| 338 | case KB(4): |
| 339 | if (chip->ecc.size == 512) |
| 340 | fmt = PAGEFMT_4K_8K | PAGEFMT_SEC_SEL_512; |
| 341 | else |
| 342 | fmt = PAGEFMT_2K_4K; |
| 343 | break; |
| 344 | case KB(8): |
| 345 | if (chip->ecc.size == 512) |
| 346 | fmt = PAGEFMT_8K_16K | PAGEFMT_SEC_SEL_512; |
| 347 | else |
| 348 | fmt = PAGEFMT_4K_8K; |
| 349 | break; |
| 350 | case KB(16): |
| 351 | fmt = PAGEFMT_8K_16K; |
| 352 | break; |
| 353 | default: |
| 354 | dev_err(nfc->dev, "invalid page len: %d\n", mtd->writesize); |
| 355 | return -EINVAL; |
| 356 | } |
| 357 | |
| 358 | /* |
| 359 | * the hardware will double the value for this eccsize, so we need to |
| 360 | * halve it |
| 361 | */ |
| 362 | if (chip->ecc.size == 1024) |
| 363 | spare >>= 1; |
| 364 | |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 365 | for (i = 0; i < nfc->caps->num_spare_size; i++) { |
| 366 | if (nfc->caps->spare_size[i] == spare) |
| 367 | break; |
| 368 | } |
| 369 | |
| 370 | if (i == nfc->caps->num_spare_size) { |
| 371 | dev_err(nfc->dev, "invalid spare size %d\n", spare); |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 372 | return -EINVAL; |
| 373 | } |
| 374 | |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 375 | fmt |= i << nfc->caps->pageformat_spare_shift; |
| 376 | |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 377 | fmt |= mtk_nand->fdm.reg_size << PAGEFMT_FDM_SHIFT; |
| 378 | fmt |= mtk_nand->fdm.ecc_size << PAGEFMT_FDM_ECC_SHIFT; |
Xiaolei Li | 582212c | 2017-05-31 16:26:39 +0800 | [diff] [blame] | 379 | nfi_writel(nfc, fmt, NFI_PAGEFMT); |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 380 | |
| 381 | nfc->ecc_cfg.strength = chip->ecc.strength; |
| 382 | nfc->ecc_cfg.len = chip->ecc.size + mtk_nand->fdm.ecc_size; |
| 383 | |
| 384 | return 0; |
| 385 | } |
| 386 | |
| 387 | static void mtk_nfc_select_chip(struct mtd_info *mtd, int chip) |
| 388 | { |
| 389 | struct nand_chip *nand = mtd_to_nand(mtd); |
| 390 | struct mtk_nfc *nfc = nand_get_controller_data(nand); |
| 391 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(nand); |
| 392 | |
| 393 | if (chip < 0) |
| 394 | return; |
| 395 | |
| 396 | mtk_nfc_hw_runtime_config(mtd); |
| 397 | |
| 398 | nfi_writel(nfc, mtk_nand->sels[chip], NFI_CSEL); |
| 399 | } |
| 400 | |
| 401 | static int mtk_nfc_dev_ready(struct mtd_info *mtd) |
| 402 | { |
| 403 | struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd)); |
| 404 | |
| 405 | if (nfi_readl(nfc, NFI_STA) & STA_BUSY) |
| 406 | return 0; |
| 407 | |
| 408 | return 1; |
| 409 | } |
| 410 | |
| 411 | static void mtk_nfc_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) |
| 412 | { |
| 413 | struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd)); |
| 414 | |
| 415 | if (ctrl & NAND_ALE) { |
| 416 | mtk_nfc_send_address(nfc, dat); |
| 417 | } else if (ctrl & NAND_CLE) { |
| 418 | mtk_nfc_hw_reset(nfc); |
| 419 | |
| 420 | nfi_writew(nfc, CNFG_OP_CUST, NFI_CNFG); |
| 421 | mtk_nfc_send_command(nfc, dat); |
| 422 | } |
| 423 | } |
| 424 | |
| 425 | static inline void mtk_nfc_wait_ioready(struct mtk_nfc *nfc) |
| 426 | { |
| 427 | int rc; |
| 428 | u8 val; |
| 429 | |
| 430 | rc = readb_poll_timeout_atomic(nfc->regs + NFI_PIO_DIRDY, val, |
| 431 | val & PIO_DI_RDY, 10, MTK_TIMEOUT); |
| 432 | if (rc < 0) |
| 433 | dev_err(nfc->dev, "data not ready\n"); |
| 434 | } |
| 435 | |
| 436 | static inline u8 mtk_nfc_read_byte(struct mtd_info *mtd) |
| 437 | { |
| 438 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 439 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 440 | u32 reg; |
| 441 | |
| 442 | /* after each byte read, the NFI_STA reg is reset by the hardware */ |
| 443 | reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK; |
| 444 | if (reg != NFI_FSM_CUSTDATA) { |
| 445 | reg = nfi_readw(nfc, NFI_CNFG); |
| 446 | reg |= CNFG_BYTE_RW | CNFG_READ_EN; |
| 447 | nfi_writew(nfc, reg, NFI_CNFG); |
| 448 | |
| 449 | /* |
| 450 | * set to max sector to allow the HW to continue reading over |
| 451 | * unaligned accesses |
| 452 | */ |
| 453 | reg = (MTK_MAX_SECTOR << CON_SEC_SHIFT) | CON_BRD; |
| 454 | nfi_writel(nfc, reg, NFI_CON); |
| 455 | |
| 456 | /* trigger to fetch data */ |
| 457 | nfi_writew(nfc, STAR_EN, NFI_STRDATA); |
| 458 | } |
| 459 | |
| 460 | mtk_nfc_wait_ioready(nfc); |
| 461 | |
| 462 | return nfi_readb(nfc, NFI_DATAR); |
| 463 | } |
| 464 | |
| 465 | static void mtk_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len) |
| 466 | { |
| 467 | int i; |
| 468 | |
| 469 | for (i = 0; i < len; i++) |
| 470 | buf[i] = mtk_nfc_read_byte(mtd); |
| 471 | } |
| 472 | |
| 473 | static void mtk_nfc_write_byte(struct mtd_info *mtd, u8 byte) |
| 474 | { |
| 475 | struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd)); |
| 476 | u32 reg; |
| 477 | |
| 478 | reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK; |
| 479 | |
| 480 | if (reg != NFI_FSM_CUSTDATA) { |
| 481 | reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW; |
| 482 | nfi_writew(nfc, reg, NFI_CNFG); |
| 483 | |
| 484 | reg = MTK_MAX_SECTOR << CON_SEC_SHIFT | CON_BWR; |
| 485 | nfi_writel(nfc, reg, NFI_CON); |
| 486 | |
| 487 | nfi_writew(nfc, STAR_EN, NFI_STRDATA); |
| 488 | } |
| 489 | |
| 490 | mtk_nfc_wait_ioready(nfc); |
| 491 | nfi_writeb(nfc, byte, NFI_DATAW); |
| 492 | } |
| 493 | |
| 494 | static void mtk_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) |
| 495 | { |
| 496 | int i; |
| 497 | |
| 498 | for (i = 0; i < len; i++) |
| 499 | mtk_nfc_write_byte(mtd, buf[i]); |
| 500 | } |
| 501 | |
Xiaolei Li | edfee36 | 2017-06-23 15:12:28 +0800 | [diff] [blame] | 502 | static int mtk_nfc_setup_data_interface(struct mtd_info *mtd, int csline, |
| 503 | const struct nand_data_interface *conf) |
| 504 | { |
| 505 | struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd)); |
| 506 | const struct nand_sdr_timings *timings; |
| 507 | u32 rate, tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt; |
| 508 | |
| 509 | timings = nand_get_sdr_timings(conf); |
| 510 | if (IS_ERR(timings)) |
| 511 | return -ENOTSUPP; |
| 512 | |
| 513 | if (csline == NAND_DATA_IFACE_CHECK_ONLY) |
| 514 | return 0; |
| 515 | |
| 516 | rate = clk_get_rate(nfc->clk.nfi_clk); |
| 517 | /* There is a frequency divider in some IPs */ |
| 518 | rate /= nfc->caps->nfi_clk_div; |
| 519 | |
| 520 | /* turn clock rate into KHZ */ |
| 521 | rate /= 1000; |
| 522 | |
| 523 | tpoecs = max(timings->tALH_min, timings->tCLH_min) / 1000; |
| 524 | tpoecs = DIV_ROUND_UP(tpoecs * rate, 1000000); |
| 525 | tpoecs &= 0xf; |
| 526 | |
| 527 | tprecs = max(timings->tCLS_min, timings->tALS_min) / 1000; |
| 528 | tprecs = DIV_ROUND_UP(tprecs * rate, 1000000); |
| 529 | tprecs &= 0x3f; |
| 530 | |
| 531 | /* sdr interface has no tCR which means CE# low to RE# low */ |
| 532 | tc2r = 0; |
| 533 | |
| 534 | tw2r = timings->tWHR_min / 1000; |
| 535 | tw2r = DIV_ROUND_UP(tw2r * rate, 1000000); |
| 536 | tw2r = DIV_ROUND_UP(tw2r - 1, 2); |
| 537 | tw2r &= 0xf; |
| 538 | |
| 539 | twh = max(timings->tREH_min, timings->tWH_min) / 1000; |
| 540 | twh = DIV_ROUND_UP(twh * rate, 1000000) - 1; |
| 541 | twh &= 0xf; |
| 542 | |
| 543 | twst = timings->tWP_min / 1000; |
| 544 | twst = DIV_ROUND_UP(twst * rate, 1000000) - 1; |
| 545 | twst &= 0xf; |
| 546 | |
| 547 | trlt = max(timings->tREA_max, timings->tRP_min) / 1000; |
| 548 | trlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1; |
| 549 | trlt &= 0xf; |
| 550 | |
| 551 | /* |
| 552 | * ACCON: access timing control register |
| 553 | * ------------------------------------- |
| 554 | * 31:28: tpoecs, minimum required time for CS post pulling down after |
| 555 | * accessing the device |
| 556 | * 27:22: tprecs, minimum required time for CS pre pulling down before |
| 557 | * accessing the device |
| 558 | * 21:16: tc2r, minimum required time from NCEB low to NREB low |
| 559 | * 15:12: tw2r, minimum required time from NWEB high to NREB low. |
| 560 | * 11:08: twh, write enable hold time |
| 561 | * 07:04: twst, write wait states |
| 562 | * 03:00: trlt, read wait states |
| 563 | */ |
| 564 | trlt = ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt); |
| 565 | nfi_writel(nfc, trlt, NFI_ACCCON); |
| 566 | |
| 567 | return 0; |
| 568 | } |
| 569 | |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 570 | static int mtk_nfc_sector_encode(struct nand_chip *chip, u8 *data) |
| 571 | { |
| 572 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 573 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); |
| 574 | int size = chip->ecc.size + mtk_nand->fdm.reg_size; |
| 575 | |
| 576 | nfc->ecc_cfg.mode = ECC_DMA_MODE; |
| 577 | nfc->ecc_cfg.op = ECC_ENCODE; |
| 578 | |
| 579 | return mtk_ecc_encode(nfc->ecc, &nfc->ecc_cfg, data, size); |
| 580 | } |
| 581 | |
| 582 | static void mtk_nfc_no_bad_mark_swap(struct mtd_info *a, u8 *b, int c) |
| 583 | { |
| 584 | /* nop */ |
| 585 | } |
| 586 | |
| 587 | static void mtk_nfc_bad_mark_swap(struct mtd_info *mtd, u8 *buf, int raw) |
| 588 | { |
| 589 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 590 | struct mtk_nfc_nand_chip *nand = to_mtk_nand(chip); |
| 591 | u32 bad_pos = nand->bad_mark.pos; |
| 592 | |
| 593 | if (raw) |
| 594 | bad_pos += nand->bad_mark.sec * mtk_data_len(chip); |
| 595 | else |
| 596 | bad_pos += nand->bad_mark.sec * chip->ecc.size; |
| 597 | |
| 598 | swap(chip->oob_poi[0], buf[bad_pos]); |
| 599 | } |
| 600 | |
| 601 | static int mtk_nfc_format_subpage(struct mtd_info *mtd, u32 offset, |
| 602 | u32 len, const u8 *buf) |
| 603 | { |
| 604 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 605 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); |
| 606 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 607 | struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; |
| 608 | u32 start, end; |
| 609 | int i, ret; |
| 610 | |
| 611 | start = offset / chip->ecc.size; |
| 612 | end = DIV_ROUND_UP(offset + len, chip->ecc.size); |
| 613 | |
| 614 | memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize); |
| 615 | for (i = 0; i < chip->ecc.steps; i++) { |
| 616 | memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i), |
| 617 | chip->ecc.size); |
| 618 | |
| 619 | if (start > i || i >= end) |
| 620 | continue; |
| 621 | |
| 622 | if (i == mtk_nand->bad_mark.sec) |
| 623 | mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1); |
| 624 | |
| 625 | memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size); |
| 626 | |
| 627 | /* program the CRC back to the OOB */ |
| 628 | ret = mtk_nfc_sector_encode(chip, mtk_data_ptr(chip, i)); |
| 629 | if (ret < 0) |
| 630 | return ret; |
| 631 | } |
| 632 | |
| 633 | return 0; |
| 634 | } |
| 635 | |
| 636 | static void mtk_nfc_format_page(struct mtd_info *mtd, const u8 *buf) |
| 637 | { |
| 638 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 639 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); |
| 640 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 641 | struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; |
| 642 | u32 i; |
| 643 | |
| 644 | memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize); |
| 645 | for (i = 0; i < chip->ecc.steps; i++) { |
| 646 | if (buf) |
| 647 | memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i), |
| 648 | chip->ecc.size); |
| 649 | |
| 650 | if (i == mtk_nand->bad_mark.sec) |
| 651 | mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1); |
| 652 | |
| 653 | memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size); |
| 654 | } |
| 655 | } |
| 656 | |
| 657 | static inline void mtk_nfc_read_fdm(struct nand_chip *chip, u32 start, |
| 658 | u32 sectors) |
| 659 | { |
| 660 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 661 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); |
| 662 | struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; |
| 663 | u32 vall, valm; |
| 664 | u8 *oobptr; |
| 665 | int i, j; |
| 666 | |
| 667 | for (i = 0; i < sectors; i++) { |
| 668 | oobptr = oob_ptr(chip, start + i); |
| 669 | vall = nfi_readl(nfc, NFI_FDML(i)); |
| 670 | valm = nfi_readl(nfc, NFI_FDMM(i)); |
| 671 | |
| 672 | for (j = 0; j < fdm->reg_size; j++) |
| 673 | oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8); |
| 674 | } |
| 675 | } |
| 676 | |
| 677 | static inline void mtk_nfc_write_fdm(struct nand_chip *chip) |
| 678 | { |
| 679 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 680 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); |
| 681 | struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; |
| 682 | u32 vall, valm; |
| 683 | u8 *oobptr; |
| 684 | int i, j; |
| 685 | |
| 686 | for (i = 0; i < chip->ecc.steps; i++) { |
| 687 | oobptr = oob_ptr(chip, i); |
| 688 | vall = 0; |
| 689 | valm = 0; |
| 690 | for (j = 0; j < 8; j++) { |
| 691 | if (j < 4) |
| 692 | vall |= (j < fdm->reg_size ? oobptr[j] : 0xff) |
| 693 | << (j * 8); |
| 694 | else |
| 695 | valm |= (j < fdm->reg_size ? oobptr[j] : 0xff) |
| 696 | << ((j - 4) * 8); |
| 697 | } |
| 698 | nfi_writel(nfc, vall, NFI_FDML(i)); |
| 699 | nfi_writel(nfc, valm, NFI_FDMM(i)); |
| 700 | } |
| 701 | } |
| 702 | |
| 703 | static int mtk_nfc_do_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
| 704 | const u8 *buf, int page, int len) |
| 705 | { |
| 706 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 707 | struct device *dev = nfc->dev; |
| 708 | dma_addr_t addr; |
| 709 | u32 reg; |
| 710 | int ret; |
| 711 | |
| 712 | addr = dma_map_single(dev, (void *)buf, len, DMA_TO_DEVICE); |
| 713 | ret = dma_mapping_error(nfc->dev, addr); |
| 714 | if (ret) { |
| 715 | dev_err(nfc->dev, "dma mapping error\n"); |
| 716 | return -EINVAL; |
| 717 | } |
| 718 | |
| 719 | reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AHB | CNFG_DMA_BURST_EN; |
| 720 | nfi_writew(nfc, reg, NFI_CNFG); |
| 721 | |
| 722 | nfi_writel(nfc, chip->ecc.steps << CON_SEC_SHIFT, NFI_CON); |
| 723 | nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR); |
| 724 | nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN); |
| 725 | |
| 726 | init_completion(&nfc->done); |
| 727 | |
| 728 | reg = nfi_readl(nfc, NFI_CON) | CON_BWR; |
| 729 | nfi_writel(nfc, reg, NFI_CON); |
| 730 | nfi_writew(nfc, STAR_EN, NFI_STRDATA); |
| 731 | |
| 732 | ret = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500)); |
| 733 | if (!ret) { |
| 734 | dev_err(dev, "program ahb done timeout\n"); |
| 735 | nfi_writew(nfc, 0, NFI_INTR_EN); |
| 736 | ret = -ETIMEDOUT; |
| 737 | goto timeout; |
| 738 | } |
| 739 | |
| 740 | ret = readl_poll_timeout_atomic(nfc->regs + NFI_ADDRCNTR, reg, |
RogerCC Lin | 559e58e | 2016-09-19 10:53:26 +0800 | [diff] [blame] | 741 | ADDRCNTR_SEC(reg) >= chip->ecc.steps, |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 742 | 10, MTK_TIMEOUT); |
| 743 | if (ret) |
| 744 | dev_err(dev, "hwecc write timeout\n"); |
| 745 | |
| 746 | timeout: |
| 747 | |
| 748 | dma_unmap_single(nfc->dev, addr, len, DMA_TO_DEVICE); |
| 749 | nfi_writel(nfc, 0, NFI_CON); |
| 750 | |
| 751 | return ret; |
| 752 | } |
| 753 | |
| 754 | static int mtk_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
| 755 | const u8 *buf, int page, int raw) |
| 756 | { |
| 757 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 758 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); |
| 759 | size_t len; |
| 760 | const u8 *bufpoi; |
| 761 | u32 reg; |
| 762 | int ret; |
| 763 | |
| 764 | if (!raw) { |
| 765 | /* OOB => FDM: from register, ECC: from HW */ |
| 766 | reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AUTO_FMT_EN; |
| 767 | nfi_writew(nfc, reg | CNFG_HW_ECC_EN, NFI_CNFG); |
| 768 | |
| 769 | nfc->ecc_cfg.op = ECC_ENCODE; |
| 770 | nfc->ecc_cfg.mode = ECC_NFI_MODE; |
| 771 | ret = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg); |
| 772 | if (ret) { |
| 773 | /* clear NFI config */ |
| 774 | reg = nfi_readw(nfc, NFI_CNFG); |
| 775 | reg &= ~(CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN); |
| 776 | nfi_writew(nfc, reg, NFI_CNFG); |
| 777 | |
| 778 | return ret; |
| 779 | } |
| 780 | |
| 781 | memcpy(nfc->buffer, buf, mtd->writesize); |
| 782 | mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, raw); |
| 783 | bufpoi = nfc->buffer; |
| 784 | |
| 785 | /* write OOB into the FDM registers (OOB area in MTK NAND) */ |
| 786 | mtk_nfc_write_fdm(chip); |
| 787 | } else { |
| 788 | bufpoi = buf; |
| 789 | } |
| 790 | |
| 791 | len = mtd->writesize + (raw ? mtd->oobsize : 0); |
| 792 | ret = mtk_nfc_do_write_page(mtd, chip, bufpoi, page, len); |
| 793 | |
| 794 | if (!raw) |
| 795 | mtk_ecc_disable(nfc->ecc); |
| 796 | |
| 797 | return ret; |
| 798 | } |
| 799 | |
| 800 | static int mtk_nfc_write_page_hwecc(struct mtd_info *mtd, |
| 801 | struct nand_chip *chip, const u8 *buf, |
| 802 | int oob_on, int page) |
| 803 | { |
| 804 | return mtk_nfc_write_page(mtd, chip, buf, page, 0); |
| 805 | } |
| 806 | |
| 807 | static int mtk_nfc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
| 808 | const u8 *buf, int oob_on, int pg) |
| 809 | { |
| 810 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 811 | |
| 812 | mtk_nfc_format_page(mtd, buf); |
| 813 | return mtk_nfc_write_page(mtd, chip, nfc->buffer, pg, 1); |
| 814 | } |
| 815 | |
| 816 | static int mtk_nfc_write_subpage_hwecc(struct mtd_info *mtd, |
| 817 | struct nand_chip *chip, u32 offset, |
| 818 | u32 data_len, const u8 *buf, |
| 819 | int oob_on, int page) |
| 820 | { |
| 821 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 822 | int ret; |
| 823 | |
| 824 | ret = mtk_nfc_format_subpage(mtd, offset, data_len, buf); |
| 825 | if (ret < 0) |
| 826 | return ret; |
| 827 | |
| 828 | /* use the data in the private buffer (now with FDM and CRC) */ |
| 829 | return mtk_nfc_write_page(mtd, chip, nfc->buffer, page, 1); |
| 830 | } |
| 831 | |
| 832 | static int mtk_nfc_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, |
| 833 | int page) |
| 834 | { |
| 835 | int ret; |
| 836 | |
| 837 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); |
| 838 | |
| 839 | ret = mtk_nfc_write_page_raw(mtd, chip, NULL, 1, page); |
| 840 | if (ret < 0) |
| 841 | return -EIO; |
| 842 | |
| 843 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); |
| 844 | ret = chip->waitfunc(mtd, chip); |
| 845 | |
| 846 | return ret & NAND_STATUS_FAIL ? -EIO : 0; |
| 847 | } |
| 848 | |
| 849 | static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 sectors) |
| 850 | { |
| 851 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 852 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 853 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); |
| 854 | struct mtk_ecc_stats stats; |
| 855 | int rc, i; |
| 856 | |
| 857 | rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE; |
| 858 | if (rc) { |
| 859 | memset(buf, 0xff, sectors * chip->ecc.size); |
| 860 | for (i = 0; i < sectors; i++) |
| 861 | memset(oob_ptr(chip, i), 0xff, mtk_nand->fdm.reg_size); |
| 862 | return 0; |
| 863 | } |
| 864 | |
| 865 | mtk_ecc_get_stats(nfc->ecc, &stats, sectors); |
| 866 | mtd->ecc_stats.corrected += stats.corrected; |
| 867 | mtd->ecc_stats.failed += stats.failed; |
| 868 | |
| 869 | return stats.bitflips; |
| 870 | } |
| 871 | |
| 872 | static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
| 873 | u32 data_offs, u32 readlen, |
| 874 | u8 *bufpoi, int page, int raw) |
| 875 | { |
| 876 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 877 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); |
| 878 | u32 spare = mtk_nand->spare_per_sector; |
| 879 | u32 column, sectors, start, end, reg; |
| 880 | dma_addr_t addr; |
| 881 | int bitflips; |
| 882 | size_t len; |
| 883 | u8 *buf; |
| 884 | int rc; |
| 885 | |
| 886 | start = data_offs / chip->ecc.size; |
| 887 | end = DIV_ROUND_UP(data_offs + readlen, chip->ecc.size); |
| 888 | |
| 889 | sectors = end - start; |
| 890 | column = start * (chip->ecc.size + spare); |
| 891 | |
| 892 | len = sectors * chip->ecc.size + (raw ? sectors * spare : 0); |
| 893 | buf = bufpoi + start * chip->ecc.size; |
| 894 | |
| 895 | if (column != 0) |
| 896 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, column, -1); |
| 897 | |
| 898 | addr = dma_map_single(nfc->dev, buf, len, DMA_FROM_DEVICE); |
| 899 | rc = dma_mapping_error(nfc->dev, addr); |
| 900 | if (rc) { |
| 901 | dev_err(nfc->dev, "dma mapping error\n"); |
| 902 | |
| 903 | return -EINVAL; |
| 904 | } |
| 905 | |
| 906 | reg = nfi_readw(nfc, NFI_CNFG); |
| 907 | reg |= CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_AHB; |
| 908 | if (!raw) { |
| 909 | reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN; |
| 910 | nfi_writew(nfc, reg, NFI_CNFG); |
| 911 | |
| 912 | nfc->ecc_cfg.mode = ECC_NFI_MODE; |
| 913 | nfc->ecc_cfg.sectors = sectors; |
| 914 | nfc->ecc_cfg.op = ECC_DECODE; |
| 915 | rc = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg); |
| 916 | if (rc) { |
| 917 | dev_err(nfc->dev, "ecc enable\n"); |
| 918 | /* clear NFI_CNFG */ |
| 919 | reg &= ~(CNFG_DMA_BURST_EN | CNFG_AHB | CNFG_READ_EN | |
| 920 | CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN); |
| 921 | nfi_writew(nfc, reg, NFI_CNFG); |
| 922 | dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE); |
| 923 | |
| 924 | return rc; |
| 925 | } |
| 926 | } else { |
| 927 | nfi_writew(nfc, reg, NFI_CNFG); |
| 928 | } |
| 929 | |
| 930 | nfi_writel(nfc, sectors << CON_SEC_SHIFT, NFI_CON); |
| 931 | nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN); |
| 932 | nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR); |
| 933 | |
| 934 | init_completion(&nfc->done); |
| 935 | reg = nfi_readl(nfc, NFI_CON) | CON_BRD; |
| 936 | nfi_writel(nfc, reg, NFI_CON); |
| 937 | nfi_writew(nfc, STAR_EN, NFI_STRDATA); |
| 938 | |
| 939 | rc = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500)); |
| 940 | if (!rc) |
| 941 | dev_warn(nfc->dev, "read ahb/dma done timeout\n"); |
| 942 | |
| 943 | rc = readl_poll_timeout_atomic(nfc->regs + NFI_BYTELEN, reg, |
RogerCC Lin | 559e58e | 2016-09-19 10:53:26 +0800 | [diff] [blame] | 944 | ADDRCNTR_SEC(reg) >= sectors, 10, |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 945 | MTK_TIMEOUT); |
| 946 | if (rc < 0) { |
| 947 | dev_err(nfc->dev, "subpage done timeout\n"); |
| 948 | bitflips = -EIO; |
| 949 | } else { |
| 950 | bitflips = 0; |
| 951 | if (!raw) { |
| 952 | rc = mtk_ecc_wait_done(nfc->ecc, ECC_DECODE); |
| 953 | bitflips = rc < 0 ? -ETIMEDOUT : |
| 954 | mtk_nfc_update_ecc_stats(mtd, buf, sectors); |
| 955 | mtk_nfc_read_fdm(chip, start, sectors); |
| 956 | } |
| 957 | } |
| 958 | |
| 959 | dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE); |
| 960 | |
| 961 | if (raw) |
| 962 | goto done; |
| 963 | |
| 964 | mtk_ecc_disable(nfc->ecc); |
| 965 | |
| 966 | if (clamp(mtk_nand->bad_mark.sec, start, end) == mtk_nand->bad_mark.sec) |
| 967 | mtk_nand->bad_mark.bm_swap(mtd, bufpoi, raw); |
| 968 | done: |
| 969 | nfi_writel(nfc, 0, NFI_CON); |
| 970 | |
| 971 | return bitflips; |
| 972 | } |
| 973 | |
| 974 | static int mtk_nfc_read_subpage_hwecc(struct mtd_info *mtd, |
| 975 | struct nand_chip *chip, u32 off, |
| 976 | u32 len, u8 *p, int pg) |
| 977 | { |
| 978 | return mtk_nfc_read_subpage(mtd, chip, off, len, p, pg, 0); |
| 979 | } |
| 980 | |
| 981 | static int mtk_nfc_read_page_hwecc(struct mtd_info *mtd, |
| 982 | struct nand_chip *chip, u8 *p, |
| 983 | int oob_on, int pg) |
| 984 | { |
| 985 | return mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, p, pg, 0); |
| 986 | } |
| 987 | |
| 988 | static int mtk_nfc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
| 989 | u8 *buf, int oob_on, int page) |
| 990 | { |
| 991 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); |
| 992 | struct mtk_nfc *nfc = nand_get_controller_data(chip); |
| 993 | struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; |
| 994 | int i, ret; |
| 995 | |
| 996 | memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize); |
| 997 | ret = mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, nfc->buffer, |
| 998 | page, 1); |
| 999 | if (ret < 0) |
| 1000 | return ret; |
| 1001 | |
| 1002 | for (i = 0; i < chip->ecc.steps; i++) { |
| 1003 | memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size); |
| 1004 | |
| 1005 | if (i == mtk_nand->bad_mark.sec) |
| 1006 | mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1); |
| 1007 | |
| 1008 | if (buf) |
| 1009 | memcpy(data_ptr(chip, buf, i), mtk_data_ptr(chip, i), |
| 1010 | chip->ecc.size); |
| 1011 | } |
| 1012 | |
| 1013 | return ret; |
| 1014 | } |
| 1015 | |
| 1016 | static int mtk_nfc_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, |
| 1017 | int page) |
| 1018 | { |
| 1019 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); |
| 1020 | |
| 1021 | return mtk_nfc_read_page_raw(mtd, chip, NULL, 1, page); |
| 1022 | } |
| 1023 | |
| 1024 | static inline void mtk_nfc_hw_init(struct mtk_nfc *nfc) |
| 1025 | { |
| 1026 | /* |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1027 | * CNRNB: nand ready/busy register |
| 1028 | * ------------------------------- |
| 1029 | * 7:4: timeout register for polling the NAND busy/ready signal |
| 1030 | * 0 : poll the status of the busy/ready signal after [7:4]*16 cycles. |
| 1031 | */ |
| 1032 | nfi_writew(nfc, 0xf1, NFI_CNRNB); |
Xiaolei Li | 582212c | 2017-05-31 16:26:39 +0800 | [diff] [blame] | 1033 | nfi_writel(nfc, PAGEFMT_8K_16K, NFI_PAGEFMT); |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1034 | |
| 1035 | mtk_nfc_hw_reset(nfc); |
| 1036 | |
| 1037 | nfi_readl(nfc, NFI_INTR_STA); |
| 1038 | nfi_writel(nfc, 0, NFI_INTR_EN); |
| 1039 | } |
| 1040 | |
| 1041 | static irqreturn_t mtk_nfc_irq(int irq, void *id) |
| 1042 | { |
| 1043 | struct mtk_nfc *nfc = id; |
| 1044 | u16 sta, ien; |
| 1045 | |
| 1046 | sta = nfi_readw(nfc, NFI_INTR_STA); |
| 1047 | ien = nfi_readw(nfc, NFI_INTR_EN); |
| 1048 | |
| 1049 | if (!(sta & ien)) |
| 1050 | return IRQ_NONE; |
| 1051 | |
| 1052 | nfi_writew(nfc, ~sta & ien, NFI_INTR_EN); |
| 1053 | complete(&nfc->done); |
| 1054 | |
| 1055 | return IRQ_HANDLED; |
| 1056 | } |
| 1057 | |
| 1058 | static int mtk_nfc_enable_clk(struct device *dev, struct mtk_nfc_clk *clk) |
| 1059 | { |
| 1060 | int ret; |
| 1061 | |
| 1062 | ret = clk_prepare_enable(clk->nfi_clk); |
| 1063 | if (ret) { |
| 1064 | dev_err(dev, "failed to enable nfi clk\n"); |
| 1065 | return ret; |
| 1066 | } |
| 1067 | |
| 1068 | ret = clk_prepare_enable(clk->pad_clk); |
| 1069 | if (ret) { |
| 1070 | dev_err(dev, "failed to enable pad clk\n"); |
| 1071 | clk_disable_unprepare(clk->nfi_clk); |
| 1072 | return ret; |
| 1073 | } |
| 1074 | |
| 1075 | return 0; |
| 1076 | } |
| 1077 | |
| 1078 | static void mtk_nfc_disable_clk(struct mtk_nfc_clk *clk) |
| 1079 | { |
| 1080 | clk_disable_unprepare(clk->nfi_clk); |
| 1081 | clk_disable_unprepare(clk->pad_clk); |
| 1082 | } |
| 1083 | |
| 1084 | static int mtk_nfc_ooblayout_free(struct mtd_info *mtd, int section, |
| 1085 | struct mtd_oob_region *oob_region) |
| 1086 | { |
| 1087 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 1088 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); |
| 1089 | struct mtk_nfc_fdm *fdm = &mtk_nand->fdm; |
| 1090 | u32 eccsteps; |
| 1091 | |
| 1092 | eccsteps = mtd->writesize / chip->ecc.size; |
| 1093 | |
| 1094 | if (section >= eccsteps) |
| 1095 | return -ERANGE; |
| 1096 | |
| 1097 | oob_region->length = fdm->reg_size - fdm->ecc_size; |
| 1098 | oob_region->offset = section * fdm->reg_size + fdm->ecc_size; |
| 1099 | |
| 1100 | return 0; |
| 1101 | } |
| 1102 | |
| 1103 | static int mtk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section, |
| 1104 | struct mtd_oob_region *oob_region) |
| 1105 | { |
| 1106 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 1107 | struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip); |
| 1108 | u32 eccsteps; |
| 1109 | |
| 1110 | if (section) |
| 1111 | return -ERANGE; |
| 1112 | |
| 1113 | eccsteps = mtd->writesize / chip->ecc.size; |
| 1114 | oob_region->offset = mtk_nand->fdm.reg_size * eccsteps; |
| 1115 | oob_region->length = mtd->oobsize - oob_region->offset; |
| 1116 | |
| 1117 | return 0; |
| 1118 | } |
| 1119 | |
| 1120 | static const struct mtd_ooblayout_ops mtk_nfc_ooblayout_ops = { |
| 1121 | .free = mtk_nfc_ooblayout_free, |
| 1122 | .ecc = mtk_nfc_ooblayout_ecc, |
| 1123 | }; |
| 1124 | |
| 1125 | static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd) |
| 1126 | { |
| 1127 | struct nand_chip *nand = mtd_to_nand(mtd); |
| 1128 | struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand); |
| 1129 | u32 ecc_bytes; |
| 1130 | |
| 1131 | ecc_bytes = DIV_ROUND_UP(nand->ecc.strength * ECC_PARITY_BITS, 8); |
| 1132 | |
| 1133 | fdm->reg_size = chip->spare_per_sector - ecc_bytes; |
| 1134 | if (fdm->reg_size > NFI_FDM_MAX_SIZE) |
| 1135 | fdm->reg_size = NFI_FDM_MAX_SIZE; |
| 1136 | |
| 1137 | /* bad block mark storage */ |
| 1138 | fdm->ecc_size = 1; |
| 1139 | } |
| 1140 | |
| 1141 | static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl, |
| 1142 | struct mtd_info *mtd) |
| 1143 | { |
| 1144 | struct nand_chip *nand = mtd_to_nand(mtd); |
| 1145 | |
| 1146 | if (mtd->writesize == 512) { |
| 1147 | bm_ctl->bm_swap = mtk_nfc_no_bad_mark_swap; |
| 1148 | } else { |
| 1149 | bm_ctl->bm_swap = mtk_nfc_bad_mark_swap; |
| 1150 | bm_ctl->sec = mtd->writesize / mtk_data_len(nand); |
| 1151 | bm_ctl->pos = mtd->writesize % mtk_data_len(nand); |
| 1152 | } |
| 1153 | } |
| 1154 | |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1155 | static int mtk_nfc_set_spare_per_sector(u32 *sps, struct mtd_info *mtd) |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1156 | { |
| 1157 | struct nand_chip *nand = mtd_to_nand(mtd); |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1158 | struct mtk_nfc *nfc = nand_get_controller_data(nand); |
| 1159 | const u8 *spare = nfc->caps->spare_size; |
| 1160 | u32 eccsteps, i, closest_spare = 0; |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1161 | |
| 1162 | eccsteps = mtd->writesize / nand->ecc.size; |
| 1163 | *sps = mtd->oobsize / eccsteps; |
| 1164 | |
| 1165 | if (nand->ecc.size == 1024) |
| 1166 | *sps >>= 1; |
| 1167 | |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1168 | if (*sps < MTK_NFC_MIN_SPARE) |
| 1169 | return -EINVAL; |
| 1170 | |
| 1171 | for (i = 0; i < nfc->caps->num_spare_size; i++) { |
| 1172 | if (*sps >= spare[i] && spare[i] >= spare[closest_spare]) { |
| 1173 | closest_spare = i; |
| 1174 | if (*sps == spare[i]) |
| 1175 | break; |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1176 | } |
| 1177 | } |
| 1178 | |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1179 | *sps = spare[closest_spare]; |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1180 | |
| 1181 | if (nand->ecc.size == 1024) |
| 1182 | *sps <<= 1; |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1183 | |
| 1184 | return 0; |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1185 | } |
| 1186 | |
| 1187 | static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd) |
| 1188 | { |
| 1189 | struct nand_chip *nand = mtd_to_nand(mtd); |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1190 | struct mtk_nfc *nfc = nand_get_controller_data(nand); |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1191 | u32 spare; |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1192 | int free, ret; |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1193 | |
| 1194 | /* support only ecc hw mode */ |
| 1195 | if (nand->ecc.mode != NAND_ECC_HW) { |
| 1196 | dev_err(dev, "ecc.mode not supported\n"); |
| 1197 | return -EINVAL; |
| 1198 | } |
| 1199 | |
| 1200 | /* if optional dt settings not present */ |
| 1201 | if (!nand->ecc.size || !nand->ecc.strength) { |
| 1202 | /* use datasheet requirements */ |
| 1203 | nand->ecc.strength = nand->ecc_strength_ds; |
| 1204 | nand->ecc.size = nand->ecc_step_ds; |
| 1205 | |
| 1206 | /* |
| 1207 | * align eccstrength and eccsize |
| 1208 | * this controller only supports 512 and 1024 sizes |
| 1209 | */ |
| 1210 | if (nand->ecc.size < 1024) { |
| 1211 | if (mtd->writesize > 512) { |
| 1212 | nand->ecc.size = 1024; |
| 1213 | nand->ecc.strength <<= 1; |
| 1214 | } else { |
| 1215 | nand->ecc.size = 512; |
| 1216 | } |
| 1217 | } else { |
| 1218 | nand->ecc.size = 1024; |
| 1219 | } |
| 1220 | |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1221 | ret = mtk_nfc_set_spare_per_sector(&spare, mtd); |
| 1222 | if (ret) |
| 1223 | return ret; |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1224 | |
| 1225 | /* calculate oob bytes except ecc parity data */ |
| 1226 | free = ((nand->ecc.strength * ECC_PARITY_BITS) + 7) >> 3; |
| 1227 | free = spare - free; |
| 1228 | |
| 1229 | /* |
| 1230 | * enhance ecc strength if oob left is bigger than max FDM size |
| 1231 | * or reduce ecc strength if oob size is not enough for ecc |
| 1232 | * parity data. |
| 1233 | */ |
| 1234 | if (free > NFI_FDM_MAX_SIZE) { |
| 1235 | spare -= NFI_FDM_MAX_SIZE; |
| 1236 | nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS; |
| 1237 | } else if (free < 0) { |
| 1238 | spare -= NFI_FDM_MIN_SIZE; |
| 1239 | nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS; |
| 1240 | } |
| 1241 | } |
| 1242 | |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1243 | mtk_ecc_adjust_strength(nfc->ecc, &nand->ecc.strength); |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1244 | |
| 1245 | dev_info(dev, "eccsize %d eccstrength %d\n", |
| 1246 | nand->ecc.size, nand->ecc.strength); |
| 1247 | |
| 1248 | return 0; |
| 1249 | } |
| 1250 | |
| 1251 | static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc, |
| 1252 | struct device_node *np) |
| 1253 | { |
| 1254 | struct mtk_nfc_nand_chip *chip; |
| 1255 | struct nand_chip *nand; |
| 1256 | struct mtd_info *mtd; |
| 1257 | int nsels, len; |
| 1258 | u32 tmp; |
| 1259 | int ret; |
| 1260 | int i; |
| 1261 | |
| 1262 | if (!of_get_property(np, "reg", &nsels)) |
| 1263 | return -ENODEV; |
| 1264 | |
| 1265 | nsels /= sizeof(u32); |
| 1266 | if (!nsels || nsels > MTK_NAND_MAX_NSELS) { |
| 1267 | dev_err(dev, "invalid reg property size %d\n", nsels); |
| 1268 | return -EINVAL; |
| 1269 | } |
| 1270 | |
| 1271 | chip = devm_kzalloc(dev, sizeof(*chip) + nsels * sizeof(u8), |
| 1272 | GFP_KERNEL); |
| 1273 | if (!chip) |
| 1274 | return -ENOMEM; |
| 1275 | |
| 1276 | chip->nsels = nsels; |
| 1277 | for (i = 0; i < nsels; i++) { |
| 1278 | ret = of_property_read_u32_index(np, "reg", i, &tmp); |
| 1279 | if (ret) { |
| 1280 | dev_err(dev, "reg property failure : %d\n", ret); |
| 1281 | return ret; |
| 1282 | } |
| 1283 | chip->sels[i] = tmp; |
| 1284 | } |
| 1285 | |
| 1286 | nand = &chip->nand; |
| 1287 | nand->controller = &nfc->controller; |
| 1288 | |
| 1289 | nand_set_flash_node(nand, np); |
| 1290 | nand_set_controller_data(nand, nfc); |
| 1291 | |
| 1292 | nand->options |= NAND_USE_BOUNCE_BUFFER | NAND_SUBPAGE_READ; |
| 1293 | nand->dev_ready = mtk_nfc_dev_ready; |
| 1294 | nand->select_chip = mtk_nfc_select_chip; |
| 1295 | nand->write_byte = mtk_nfc_write_byte; |
| 1296 | nand->write_buf = mtk_nfc_write_buf; |
| 1297 | nand->read_byte = mtk_nfc_read_byte; |
| 1298 | nand->read_buf = mtk_nfc_read_buf; |
| 1299 | nand->cmd_ctrl = mtk_nfc_cmd_ctrl; |
Xiaolei Li | edfee36 | 2017-06-23 15:12:28 +0800 | [diff] [blame] | 1300 | nand->setup_data_interface = mtk_nfc_setup_data_interface; |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1301 | |
| 1302 | /* set default mode in case dt entry is missing */ |
| 1303 | nand->ecc.mode = NAND_ECC_HW; |
| 1304 | |
| 1305 | nand->ecc.write_subpage = mtk_nfc_write_subpage_hwecc; |
| 1306 | nand->ecc.write_page_raw = mtk_nfc_write_page_raw; |
| 1307 | nand->ecc.write_page = mtk_nfc_write_page_hwecc; |
| 1308 | nand->ecc.write_oob_raw = mtk_nfc_write_oob_std; |
| 1309 | nand->ecc.write_oob = mtk_nfc_write_oob_std; |
| 1310 | |
| 1311 | nand->ecc.read_subpage = mtk_nfc_read_subpage_hwecc; |
| 1312 | nand->ecc.read_page_raw = mtk_nfc_read_page_raw; |
| 1313 | nand->ecc.read_page = mtk_nfc_read_page_hwecc; |
| 1314 | nand->ecc.read_oob_raw = mtk_nfc_read_oob_std; |
| 1315 | nand->ecc.read_oob = mtk_nfc_read_oob_std; |
| 1316 | |
| 1317 | mtd = nand_to_mtd(nand); |
| 1318 | mtd->owner = THIS_MODULE; |
| 1319 | mtd->dev.parent = dev; |
| 1320 | mtd->name = MTK_NAME; |
| 1321 | mtd_set_ooblayout(mtd, &mtk_nfc_ooblayout_ops); |
| 1322 | |
| 1323 | mtk_nfc_hw_init(nfc); |
| 1324 | |
| 1325 | ret = nand_scan_ident(mtd, nsels, NULL); |
| 1326 | if (ret) |
Masahiro Yamada | f0dbe4a | 2016-11-04 19:43:02 +0900 | [diff] [blame] | 1327 | return ret; |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1328 | |
| 1329 | /* store bbt magic in page, cause OOB is not protected */ |
| 1330 | if (nand->bbt_options & NAND_BBT_USE_FLASH) |
| 1331 | nand->bbt_options |= NAND_BBT_NO_OOB; |
| 1332 | |
| 1333 | ret = mtk_nfc_ecc_init(dev, mtd); |
| 1334 | if (ret) |
| 1335 | return -EINVAL; |
| 1336 | |
| 1337 | if (nand->options & NAND_BUSWIDTH_16) { |
| 1338 | dev_err(dev, "16bits buswidth not supported"); |
| 1339 | return -EINVAL; |
| 1340 | } |
| 1341 | |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1342 | ret = mtk_nfc_set_spare_per_sector(&chip->spare_per_sector, mtd); |
| 1343 | if (ret) |
| 1344 | return ret; |
| 1345 | |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1346 | mtk_nfc_set_fdm(&chip->fdm, mtd); |
| 1347 | mtk_nfc_set_bad_mark_ctl(&chip->bad_mark, mtd); |
| 1348 | |
| 1349 | len = mtd->writesize + mtd->oobsize; |
| 1350 | nfc->buffer = devm_kzalloc(dev, len, GFP_KERNEL); |
| 1351 | if (!nfc->buffer) |
| 1352 | return -ENOMEM; |
| 1353 | |
| 1354 | ret = nand_scan_tail(mtd); |
| 1355 | if (ret) |
Masahiro Yamada | f0dbe4a | 2016-11-04 19:43:02 +0900 | [diff] [blame] | 1356 | return ret; |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1357 | |
| 1358 | ret = mtd_device_parse_register(mtd, NULL, NULL, NULL, 0); |
| 1359 | if (ret) { |
| 1360 | dev_err(dev, "mtd parse partition error\n"); |
| 1361 | nand_release(mtd); |
| 1362 | return ret; |
| 1363 | } |
| 1364 | |
| 1365 | list_add_tail(&chip->node, &nfc->chips); |
| 1366 | |
| 1367 | return 0; |
| 1368 | } |
| 1369 | |
| 1370 | static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc) |
| 1371 | { |
| 1372 | struct device_node *np = dev->of_node; |
| 1373 | struct device_node *nand_np; |
| 1374 | int ret; |
| 1375 | |
| 1376 | for_each_child_of_node(np, nand_np) { |
| 1377 | ret = mtk_nfc_nand_chip_init(dev, nfc, nand_np); |
| 1378 | if (ret) { |
| 1379 | of_node_put(nand_np); |
| 1380 | return ret; |
| 1381 | } |
| 1382 | } |
| 1383 | |
| 1384 | return 0; |
| 1385 | } |
| 1386 | |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1387 | static const struct mtk_nfc_caps mtk_nfc_caps_mt2701 = { |
| 1388 | .spare_size = spare_size_mt2701, |
| 1389 | .num_spare_size = 16, |
| 1390 | .pageformat_spare_shift = 4, |
Xiaolei Li | edfee36 | 2017-06-23 15:12:28 +0800 | [diff] [blame] | 1391 | .nfi_clk_div = 1, |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1392 | }; |
| 1393 | |
Xiaolei Li | 30ee809 | 2017-05-31 16:26:41 +0800 | [diff] [blame] | 1394 | static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = { |
| 1395 | .spare_size = spare_size_mt2712, |
| 1396 | .num_spare_size = 19, |
| 1397 | .pageformat_spare_shift = 16, |
Xiaolei Li | edfee36 | 2017-06-23 15:12:28 +0800 | [diff] [blame] | 1398 | .nfi_clk_div = 2, |
Xiaolei Li | 30ee809 | 2017-05-31 16:26:41 +0800 | [diff] [blame] | 1399 | }; |
| 1400 | |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1401 | static const struct of_device_id mtk_nfc_id_table[] = { |
| 1402 | { |
| 1403 | .compatible = "mediatek,mt2701-nfc", |
| 1404 | .data = &mtk_nfc_caps_mt2701, |
Xiaolei Li | 30ee809 | 2017-05-31 16:26:41 +0800 | [diff] [blame] | 1405 | }, { |
| 1406 | .compatible = "mediatek,mt2712-nfc", |
| 1407 | .data = &mtk_nfc_caps_mt2712, |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1408 | }, |
| 1409 | {} |
| 1410 | }; |
| 1411 | MODULE_DEVICE_TABLE(of, mtk_nfc_id_table); |
| 1412 | |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1413 | static int mtk_nfc_probe(struct platform_device *pdev) |
| 1414 | { |
| 1415 | struct device *dev = &pdev->dev; |
| 1416 | struct device_node *np = dev->of_node; |
| 1417 | struct mtk_nfc *nfc; |
| 1418 | struct resource *res; |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1419 | const struct of_device_id *of_nfc_id = NULL; |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1420 | int ret, irq; |
| 1421 | |
| 1422 | nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); |
| 1423 | if (!nfc) |
| 1424 | return -ENOMEM; |
| 1425 | |
| 1426 | spin_lock_init(&nfc->controller.lock); |
| 1427 | init_waitqueue_head(&nfc->controller.wq); |
| 1428 | INIT_LIST_HEAD(&nfc->chips); |
| 1429 | |
| 1430 | /* probe defer if not ready */ |
| 1431 | nfc->ecc = of_mtk_ecc_get(np); |
| 1432 | if (IS_ERR(nfc->ecc)) |
| 1433 | return PTR_ERR(nfc->ecc); |
| 1434 | else if (!nfc->ecc) |
| 1435 | return -ENODEV; |
| 1436 | |
| 1437 | nfc->dev = dev; |
| 1438 | |
| 1439 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1440 | nfc->regs = devm_ioremap_resource(dev, res); |
| 1441 | if (IS_ERR(nfc->regs)) { |
| 1442 | ret = PTR_ERR(nfc->regs); |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1443 | goto release_ecc; |
| 1444 | } |
| 1445 | |
| 1446 | nfc->clk.nfi_clk = devm_clk_get(dev, "nfi_clk"); |
| 1447 | if (IS_ERR(nfc->clk.nfi_clk)) { |
| 1448 | dev_err(dev, "no clk\n"); |
| 1449 | ret = PTR_ERR(nfc->clk.nfi_clk); |
| 1450 | goto release_ecc; |
| 1451 | } |
| 1452 | |
| 1453 | nfc->clk.pad_clk = devm_clk_get(dev, "pad_clk"); |
| 1454 | if (IS_ERR(nfc->clk.pad_clk)) { |
| 1455 | dev_err(dev, "no pad clk\n"); |
| 1456 | ret = PTR_ERR(nfc->clk.pad_clk); |
| 1457 | goto release_ecc; |
| 1458 | } |
| 1459 | |
| 1460 | ret = mtk_nfc_enable_clk(dev, &nfc->clk); |
| 1461 | if (ret) |
| 1462 | goto release_ecc; |
| 1463 | |
| 1464 | irq = platform_get_irq(pdev, 0); |
| 1465 | if (irq < 0) { |
| 1466 | dev_err(dev, "no nfi irq resource\n"); |
| 1467 | ret = -EINVAL; |
| 1468 | goto clk_disable; |
| 1469 | } |
| 1470 | |
| 1471 | ret = devm_request_irq(dev, irq, mtk_nfc_irq, 0x0, "mtk-nand", nfc); |
| 1472 | if (ret) { |
| 1473 | dev_err(dev, "failed to request nfi irq\n"); |
| 1474 | goto clk_disable; |
| 1475 | } |
| 1476 | |
| 1477 | ret = dma_set_mask(dev, DMA_BIT_MASK(32)); |
| 1478 | if (ret) { |
| 1479 | dev_err(dev, "failed to set dma mask\n"); |
| 1480 | goto clk_disable; |
| 1481 | } |
| 1482 | |
Xiaolei Li | 7ec4a37 | 2017-05-31 16:26:40 +0800 | [diff] [blame] | 1483 | of_nfc_id = of_match_device(mtk_nfc_id_table, &pdev->dev); |
| 1484 | if (!of_nfc_id) { |
| 1485 | ret = -ENODEV; |
| 1486 | goto clk_disable; |
| 1487 | } |
| 1488 | |
| 1489 | nfc->caps = of_nfc_id->data; |
| 1490 | |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1491 | platform_set_drvdata(pdev, nfc); |
| 1492 | |
| 1493 | ret = mtk_nfc_nand_chips_init(dev, nfc); |
| 1494 | if (ret) { |
| 1495 | dev_err(dev, "failed to init nand chips\n"); |
| 1496 | goto clk_disable; |
| 1497 | } |
| 1498 | |
| 1499 | return 0; |
| 1500 | |
| 1501 | clk_disable: |
| 1502 | mtk_nfc_disable_clk(&nfc->clk); |
| 1503 | |
| 1504 | release_ecc: |
| 1505 | mtk_ecc_release(nfc->ecc); |
| 1506 | |
| 1507 | return ret; |
| 1508 | } |
| 1509 | |
| 1510 | static int mtk_nfc_remove(struct platform_device *pdev) |
| 1511 | { |
| 1512 | struct mtk_nfc *nfc = platform_get_drvdata(pdev); |
| 1513 | struct mtk_nfc_nand_chip *chip; |
| 1514 | |
| 1515 | while (!list_empty(&nfc->chips)) { |
| 1516 | chip = list_first_entry(&nfc->chips, struct mtk_nfc_nand_chip, |
| 1517 | node); |
| 1518 | nand_release(nand_to_mtd(&chip->nand)); |
| 1519 | list_del(&chip->node); |
| 1520 | } |
| 1521 | |
| 1522 | mtk_ecc_release(nfc->ecc); |
| 1523 | mtk_nfc_disable_clk(&nfc->clk); |
| 1524 | |
| 1525 | return 0; |
| 1526 | } |
| 1527 | |
| 1528 | #ifdef CONFIG_PM_SLEEP |
| 1529 | static int mtk_nfc_suspend(struct device *dev) |
| 1530 | { |
| 1531 | struct mtk_nfc *nfc = dev_get_drvdata(dev); |
| 1532 | |
| 1533 | mtk_nfc_disable_clk(&nfc->clk); |
| 1534 | |
| 1535 | return 0; |
| 1536 | } |
| 1537 | |
| 1538 | static int mtk_nfc_resume(struct device *dev) |
| 1539 | { |
| 1540 | struct mtk_nfc *nfc = dev_get_drvdata(dev); |
| 1541 | struct mtk_nfc_nand_chip *chip; |
| 1542 | struct nand_chip *nand; |
| 1543 | struct mtd_info *mtd; |
| 1544 | int ret; |
| 1545 | u32 i; |
| 1546 | |
| 1547 | udelay(200); |
| 1548 | |
| 1549 | ret = mtk_nfc_enable_clk(dev, &nfc->clk); |
| 1550 | if (ret) |
| 1551 | return ret; |
| 1552 | |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1553 | /* reset NAND chip if VCC was powered off */ |
| 1554 | list_for_each_entry(chip, &nfc->chips, node) { |
| 1555 | nand = &chip->nand; |
| 1556 | mtd = nand_to_mtd(nand); |
| 1557 | for (i = 0; i < chip->nsels; i++) { |
| 1558 | nand->select_chip(mtd, i); |
| 1559 | nand->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
| 1560 | } |
| 1561 | } |
| 1562 | |
| 1563 | return 0; |
| 1564 | } |
| 1565 | |
| 1566 | static SIMPLE_DEV_PM_OPS(mtk_nfc_pm_ops, mtk_nfc_suspend, mtk_nfc_resume); |
| 1567 | #endif |
| 1568 | |
Jorge Ramirez-Ortiz | 1d6b1e4 | 2016-06-14 11:50:51 -0400 | [diff] [blame] | 1569 | static struct platform_driver mtk_nfc_driver = { |
| 1570 | .probe = mtk_nfc_probe, |
| 1571 | .remove = mtk_nfc_remove, |
| 1572 | .driver = { |
| 1573 | .name = MTK_NAME, |
| 1574 | .of_match_table = mtk_nfc_id_table, |
| 1575 | #ifdef CONFIG_PM_SLEEP |
| 1576 | .pm = &mtk_nfc_pm_ops, |
| 1577 | #endif |
| 1578 | }, |
| 1579 | }; |
| 1580 | |
| 1581 | module_platform_driver(mtk_nfc_driver); |
| 1582 | |
| 1583 | MODULE_LICENSE("GPL"); |
| 1584 | MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>"); |
| 1585 | MODULE_DESCRIPTION("MTK Nand Flash Controller Driver"); |