Ian Molton | 64e8867 | 2010-01-06 13:51:48 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright(c) 2009 Ian Molton <spyro@f2s.com> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
Paul Gortmaker | 5d4a357 | 2011-07-10 12:41:10 -0400 | [diff] [blame] | 9 | #include <linux/export.h> |
Ian Molton | 64e8867 | 2010-01-06 13:51:48 +0100 | [diff] [blame] | 10 | #include <linux/mfd/tmio.h> |
| 11 | |
Masahiro Yamada | 299fad6b9 | 2017-11-07 17:14:12 +0900 | [diff] [blame] | 12 | #define CNF_CMD 0x04 |
| 13 | #define CNF_CTL_BASE 0x10 |
| 14 | #define CNF_INT_PIN 0x3d |
| 15 | #define CNF_STOP_CLK_CTL 0x40 |
| 16 | #define CNF_GCLK_CTL 0x41 |
| 17 | #define CNF_SD_CLK_MODE 0x42 |
| 18 | #define CNF_PIN_STATUS 0x44 |
| 19 | #define CNF_PWR_CTL_1 0x48 |
| 20 | #define CNF_PWR_CTL_2 0x49 |
| 21 | #define CNF_PWR_CTL_3 0x4a |
| 22 | #define CNF_CARD_DETECT_MODE 0x4c |
| 23 | #define CNF_SD_SLOT 0x50 |
| 24 | #define CNF_EXT_GCLK_CTL_1 0xf0 |
| 25 | #define CNF_EXT_GCLK_CTL_2 0xf1 |
| 26 | #define CNF_EXT_GCLK_CTL_3 0xf9 |
| 27 | #define CNF_SD_LED_EN_1 0xfa |
| 28 | #define CNF_SD_LED_EN_2 0xfe |
| 29 | |
| 30 | #define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/ |
| 31 | |
Ian Molton | 64e8867 | 2010-01-06 13:51:48 +0100 | [diff] [blame] | 32 | int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base) |
| 33 | { |
| 34 | /* Enable the MMC/SD Control registers */ |
| 35 | sd_config_write16(cnf, shift, CNF_CMD, SDCREN); |
| 36 | sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe); |
| 37 | |
| 38 | /* Disable SD power during suspend */ |
| 39 | sd_config_write8(cnf, shift, CNF_PWR_CTL_3, 0x01); |
| 40 | |
| 41 | /* The below is required but why? FIXME */ |
| 42 | sd_config_write8(cnf, shift, CNF_STOP_CLK_CTL, 0x1f); |
| 43 | |
| 44 | /* Power down SD bus */ |
| 45 | sd_config_write8(cnf, shift, CNF_PWR_CTL_2, 0x00); |
| 46 | |
| 47 | return 0; |
| 48 | } |
| 49 | EXPORT_SYMBOL(tmio_core_mmc_enable); |
| 50 | |
| 51 | int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base) |
| 52 | { |
| 53 | |
| 54 | /* Enable the MMC/SD Control registers */ |
| 55 | sd_config_write16(cnf, shift, CNF_CMD, SDCREN); |
| 56 | sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe); |
| 57 | |
| 58 | return 0; |
| 59 | } |
| 60 | EXPORT_SYMBOL(tmio_core_mmc_resume); |
| 61 | |
| 62 | void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state) |
| 63 | { |
| 64 | sd_config_write8(cnf, shift, CNF_PWR_CTL_2, state ? 0x02 : 0x00); |
| 65 | } |
| 66 | EXPORT_SYMBOL(tmio_core_mmc_pwr); |
| 67 | |
| 68 | void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state) |
| 69 | { |
| 70 | sd_config_write8(cnf, shift, CNF_SD_CLK_MODE, state ? 1 : 0); |
| 71 | } |
| 72 | EXPORT_SYMBOL(tmio_core_mmc_clk_div); |
| 73 | |