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gerrit-public.fairphone.software / kernel / msm-4.19 / 24a768cfc4f8cbbb3eaf56284610e652ef05fc5b / . / drivers / net / ethernet / intel / i40e / i40e_common.c
blob: 9d09ab31ec89ef49f605436c4ba4dcf31770dc11 [file] [log] [blame]
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
Greg Rosedc641b72013-12-18 13:45:51 +0000[diff] [blame]4 * Copyright(c) 2013 - 2014 Intel Corporation.
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
Greg Rosedc641b72013-12-18 13:45:51 +0000[diff] [blame]15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
Shannon Nelsonab600852014-01-17 15:36:39 -0800[diff] [blame]45 case I40E_DEV_ID_SFP_XL710:
Shannon Nelsonab600852014-01-17 15:36:39 -0800[diff] [blame]46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_A:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
Shannon Nelsonab600852014-01-17 15:36:39 -0800[diff] [blame]50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]53 hw->mac.type = I40E_MAC_XL710;
54 break;
Shannon Nelsonab600852014-01-17 15:36:39 -0800[diff] [blame]55 case I40E_DEV_ID_VF:
56 case I40E_DEV_ID_VF_HV:
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]57 hw->mac.type = I40E_MAC_VF;
58 break;
59 default:
60 hw->mac.type = I40E_MAC_GENERIC;
61 break;
62 }
63 } else {
64 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
65 }
66
67 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
68 hw->mac.type, status);
69 return status;
70}
71
72/**
73 * i40e_debug_aq
74 * @hw: debug mask related to admin queue
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]75 * @mask: debug mask
76 * @desc: pointer to admin queue descriptor
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]77 * @buffer: pointer to command buffer
78 *
79 * Dumps debug log about adminq command with descriptor contents.
80 **/
81void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
82 void *buffer)
83{
84 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
85 u8 *aq_buffer = (u8 *)buffer;
86 u32 data[4];
87 u32 i = 0;
88
89 if ((!(mask & hw->debug_mask)) || (desc == NULL))
90 return;
91
92 i40e_debug(hw, mask,
93 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
94 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
95 aq_desc->retval);
96 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
97 aq_desc->cookie_high, aq_desc->cookie_low);
98 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
99 aq_desc->params.internal.param0,
100 aq_desc->params.internal.param1);
101 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
102 aq_desc->params.external.addr_high,
103 aq_desc->params.external.addr_low);
104
105 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
106 memset(data, 0, sizeof(data));
107 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
108 for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
109 data[((i % 16) / 4)] |=
110 ((u32)aq_buffer[i]) << (8 * (i % 4));
111 if ((i % 16) == 15) {
112 i40e_debug(hw, mask,
113 "\t0x%04X %08X %08X %08X %08X\n",
114 i - 15, data[0], data[1], data[2],
115 data[3]);
116 memset(data, 0, sizeof(data));
117 }
118 }
119 if ((i % 16) != 0)
120 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
121 i - (i % 16), data[0], data[1], data[2],
122 data[3]);
123 }
124}
125
126/**
Anjali Singhai Jaine1860d82013-11-28 06:39:45 +0000[diff] [blame]127 * i40e_check_asq_alive
128 * @hw: pointer to the hw struct
129 *
130 * Returns true if Queue is enabled else false.
131 **/
132bool i40e_check_asq_alive(struct i40e_hw *hw)
133{
Kevin Scott8b833b42014-04-09 05:58:54 +0000[diff] [blame]134 if (hw->aq.asq.len)
135 return !!(rd32(hw, hw->aq.asq.len) &
136 I40E_PF_ATQLEN_ATQENABLE_MASK);
137 else
138 return false;
Anjali Singhai Jaine1860d82013-11-28 06:39:45 +0000[diff] [blame]139}
140
141/**
142 * i40e_aq_queue_shutdown
143 * @hw: pointer to the hw struct
144 * @unloading: is the driver unloading itself
145 *
146 * Tell the Firmware that we're shutting down the AdminQ and whether
147 * or not the driver is unloading as well.
148 **/
149i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
150 bool unloading)
151{
152 struct i40e_aq_desc desc;
153 struct i40e_aqc_queue_shutdown *cmd =
154 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
155 i40e_status status;
156
157 i40e_fill_default_direct_cmd_desc(&desc,
158 i40e_aqc_opc_queue_shutdown);
159
160 if (unloading)
161 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
162 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
163
164 return status;
165}
166
Jesse Brandeburg206812b2014-02-12 01:45:33 +0000[diff] [blame]167/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
168 * hardware to a bit-field that can be used by SW to more easily determine the
169 * packet type.
170 *
171 * Macros are used to shorten the table lines and make this table human
172 * readable.
173 *
174 * We store the PTYPE in the top byte of the bit field - this is just so that
175 * we can check that the table doesn't have a row missing, as the index into
176 * the table should be the PTYPE.
177 *
178 * Typical work flow:
179 *
180 * IF NOT i40e_ptype_lookup[ptype].known
181 * THEN
182 * Packet is unknown
183 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
184 * Use the rest of the fields to look at the tunnels, inner protocols, etc
185 * ELSE
186 * Use the enum i40e_rx_l2_ptype to decode the packet type
187 * ENDIF
188 */
189
190/* macro to make the table lines short */
191#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
192 { PTYPE, \
193 1, \
194 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
195 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
196 I40E_RX_PTYPE_##OUTER_FRAG, \
197 I40E_RX_PTYPE_TUNNEL_##T, \
198 I40E_RX_PTYPE_TUNNEL_END_##TE, \
199 I40E_RX_PTYPE_##TEF, \
200 I40E_RX_PTYPE_INNER_PROT_##I, \
201 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
202
203#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
204 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
205
206/* shorter macros makes the table fit but are terse */
207#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
208#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
209#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
210
211/* Lookup table mapping the HW PTYPE to the bit field for decoding */
212struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
213 /* L2 Packet types */
214 I40E_PTT_UNUSED_ENTRY(0),
215 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
216 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
217 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
218 I40E_PTT_UNUSED_ENTRY(4),
219 I40E_PTT_UNUSED_ENTRY(5),
220 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
221 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
222 I40E_PTT_UNUSED_ENTRY(8),
223 I40E_PTT_UNUSED_ENTRY(9),
224 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
225 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
226 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
227 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
228 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
229 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
230 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
231 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
235 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
236
237 /* Non Tunneled IPv4 */
238 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
239 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
240 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
241 I40E_PTT_UNUSED_ENTRY(25),
242 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
243 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
244 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
245
246 /* IPv4 --> IPv4 */
247 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
248 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
249 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
250 I40E_PTT_UNUSED_ENTRY(32),
251 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
252 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
253 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
254
255 /* IPv4 --> IPv6 */
256 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
257 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
258 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
259 I40E_PTT_UNUSED_ENTRY(39),
260 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
261 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
262 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
263
264 /* IPv4 --> GRE/NAT */
265 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
266
267 /* IPv4 --> GRE/NAT --> IPv4 */
268 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
269 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
270 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
271 I40E_PTT_UNUSED_ENTRY(47),
272 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
273 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
274 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
275
276 /* IPv4 --> GRE/NAT --> IPv6 */
277 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
278 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
279 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
280 I40E_PTT_UNUSED_ENTRY(54),
281 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
282 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
283 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
284
285 /* IPv4 --> GRE/NAT --> MAC */
286 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
287
288 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
289 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
290 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
291 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
292 I40E_PTT_UNUSED_ENTRY(62),
293 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
294 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
295 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
296
297 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
298 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
299 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
300 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
301 I40E_PTT_UNUSED_ENTRY(69),
302 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
303 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
304 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
305
306 /* IPv4 --> GRE/NAT --> MAC/VLAN */
307 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
308
309 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
310 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
311 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
312 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
313 I40E_PTT_UNUSED_ENTRY(77),
314 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
315 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
316 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
317
318 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
319 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
320 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
321 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
322 I40E_PTT_UNUSED_ENTRY(84),
323 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
324 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
325 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
326
327 /* Non Tunneled IPv6 */
328 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
329 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
330 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
331 I40E_PTT_UNUSED_ENTRY(91),
332 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
333 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
334 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
335
336 /* IPv6 --> IPv4 */
337 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
338 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
339 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
340 I40E_PTT_UNUSED_ENTRY(98),
341 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
342 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
343 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
344
345 /* IPv6 --> IPv6 */
346 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
347 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
348 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
349 I40E_PTT_UNUSED_ENTRY(105),
350 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
351 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
352 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
353
354 /* IPv6 --> GRE/NAT */
355 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
356
357 /* IPv6 --> GRE/NAT -> IPv4 */
358 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
359 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
360 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
361 I40E_PTT_UNUSED_ENTRY(113),
362 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
363 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
364 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
365
366 /* IPv6 --> GRE/NAT -> IPv6 */
367 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
368 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
369 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
370 I40E_PTT_UNUSED_ENTRY(120),
371 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
372 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
373 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
374
375 /* IPv6 --> GRE/NAT -> MAC */
376 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
377
378 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
379 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
380 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
381 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
382 I40E_PTT_UNUSED_ENTRY(128),
383 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
384 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
385 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
386
387 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
388 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
389 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
390 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
391 I40E_PTT_UNUSED_ENTRY(135),
392 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
393 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
394 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
395
396 /* IPv6 --> GRE/NAT -> MAC/VLAN */
397 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
398
399 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
400 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
401 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
402 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
403 I40E_PTT_UNUSED_ENTRY(143),
404 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
405 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
406 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
407
408 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
409 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
410 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
411 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
412 I40E_PTT_UNUSED_ENTRY(150),
413 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
414 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
415 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
416
417 /* unused entries */
418 I40E_PTT_UNUSED_ENTRY(154),
419 I40E_PTT_UNUSED_ENTRY(155),
420 I40E_PTT_UNUSED_ENTRY(156),
421 I40E_PTT_UNUSED_ENTRY(157),
422 I40E_PTT_UNUSED_ENTRY(158),
423 I40E_PTT_UNUSED_ENTRY(159),
424
425 I40E_PTT_UNUSED_ENTRY(160),
426 I40E_PTT_UNUSED_ENTRY(161),
427 I40E_PTT_UNUSED_ENTRY(162),
428 I40E_PTT_UNUSED_ENTRY(163),
429 I40E_PTT_UNUSED_ENTRY(164),
430 I40E_PTT_UNUSED_ENTRY(165),
431 I40E_PTT_UNUSED_ENTRY(166),
432 I40E_PTT_UNUSED_ENTRY(167),
433 I40E_PTT_UNUSED_ENTRY(168),
434 I40E_PTT_UNUSED_ENTRY(169),
435
436 I40E_PTT_UNUSED_ENTRY(170),
437 I40E_PTT_UNUSED_ENTRY(171),
438 I40E_PTT_UNUSED_ENTRY(172),
439 I40E_PTT_UNUSED_ENTRY(173),
440 I40E_PTT_UNUSED_ENTRY(174),
441 I40E_PTT_UNUSED_ENTRY(175),
442 I40E_PTT_UNUSED_ENTRY(176),
443 I40E_PTT_UNUSED_ENTRY(177),
444 I40E_PTT_UNUSED_ENTRY(178),
445 I40E_PTT_UNUSED_ENTRY(179),
446
447 I40E_PTT_UNUSED_ENTRY(180),
448 I40E_PTT_UNUSED_ENTRY(181),
449 I40E_PTT_UNUSED_ENTRY(182),
450 I40E_PTT_UNUSED_ENTRY(183),
451 I40E_PTT_UNUSED_ENTRY(184),
452 I40E_PTT_UNUSED_ENTRY(185),
453 I40E_PTT_UNUSED_ENTRY(186),
454 I40E_PTT_UNUSED_ENTRY(187),
455 I40E_PTT_UNUSED_ENTRY(188),
456 I40E_PTT_UNUSED_ENTRY(189),
457
458 I40E_PTT_UNUSED_ENTRY(190),
459 I40E_PTT_UNUSED_ENTRY(191),
460 I40E_PTT_UNUSED_ENTRY(192),
461 I40E_PTT_UNUSED_ENTRY(193),
462 I40E_PTT_UNUSED_ENTRY(194),
463 I40E_PTT_UNUSED_ENTRY(195),
464 I40E_PTT_UNUSED_ENTRY(196),
465 I40E_PTT_UNUSED_ENTRY(197),
466 I40E_PTT_UNUSED_ENTRY(198),
467 I40E_PTT_UNUSED_ENTRY(199),
468
469 I40E_PTT_UNUSED_ENTRY(200),
470 I40E_PTT_UNUSED_ENTRY(201),
471 I40E_PTT_UNUSED_ENTRY(202),
472 I40E_PTT_UNUSED_ENTRY(203),
473 I40E_PTT_UNUSED_ENTRY(204),
474 I40E_PTT_UNUSED_ENTRY(205),
475 I40E_PTT_UNUSED_ENTRY(206),
476 I40E_PTT_UNUSED_ENTRY(207),
477 I40E_PTT_UNUSED_ENTRY(208),
478 I40E_PTT_UNUSED_ENTRY(209),
479
480 I40E_PTT_UNUSED_ENTRY(210),
481 I40E_PTT_UNUSED_ENTRY(211),
482 I40E_PTT_UNUSED_ENTRY(212),
483 I40E_PTT_UNUSED_ENTRY(213),
484 I40E_PTT_UNUSED_ENTRY(214),
485 I40E_PTT_UNUSED_ENTRY(215),
486 I40E_PTT_UNUSED_ENTRY(216),
487 I40E_PTT_UNUSED_ENTRY(217),
488 I40E_PTT_UNUSED_ENTRY(218),
489 I40E_PTT_UNUSED_ENTRY(219),
490
491 I40E_PTT_UNUSED_ENTRY(220),
492 I40E_PTT_UNUSED_ENTRY(221),
493 I40E_PTT_UNUSED_ENTRY(222),
494 I40E_PTT_UNUSED_ENTRY(223),
495 I40E_PTT_UNUSED_ENTRY(224),
496 I40E_PTT_UNUSED_ENTRY(225),
497 I40E_PTT_UNUSED_ENTRY(226),
498 I40E_PTT_UNUSED_ENTRY(227),
499 I40E_PTT_UNUSED_ENTRY(228),
500 I40E_PTT_UNUSED_ENTRY(229),
501
502 I40E_PTT_UNUSED_ENTRY(230),
503 I40E_PTT_UNUSED_ENTRY(231),
504 I40E_PTT_UNUSED_ENTRY(232),
505 I40E_PTT_UNUSED_ENTRY(233),
506 I40E_PTT_UNUSED_ENTRY(234),
507 I40E_PTT_UNUSED_ENTRY(235),
508 I40E_PTT_UNUSED_ENTRY(236),
509 I40E_PTT_UNUSED_ENTRY(237),
510 I40E_PTT_UNUSED_ENTRY(238),
511 I40E_PTT_UNUSED_ENTRY(239),
512
513 I40E_PTT_UNUSED_ENTRY(240),
514 I40E_PTT_UNUSED_ENTRY(241),
515 I40E_PTT_UNUSED_ENTRY(242),
516 I40E_PTT_UNUSED_ENTRY(243),
517 I40E_PTT_UNUSED_ENTRY(244),
518 I40E_PTT_UNUSED_ENTRY(245),
519 I40E_PTT_UNUSED_ENTRY(246),
520 I40E_PTT_UNUSED_ENTRY(247),
521 I40E_PTT_UNUSED_ENTRY(248),
522 I40E_PTT_UNUSED_ENTRY(249),
523
524 I40E_PTT_UNUSED_ENTRY(250),
525 I40E_PTT_UNUSED_ENTRY(251),
526 I40E_PTT_UNUSED_ENTRY(252),
527 I40E_PTT_UNUSED_ENTRY(253),
528 I40E_PTT_UNUSED_ENTRY(254),
529 I40E_PTT_UNUSED_ENTRY(255)
530};
531
532
Anjali Singhai Jaine1860d82013-11-28 06:39:45 +0000[diff] [blame]533/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]534 * i40e_init_shared_code - Initialize the shared code
535 * @hw: pointer to hardware structure
536 *
537 * This assigns the MAC type and PHY code and inits the NVM.
538 * Does not touch the hardware. This function must be called prior to any
539 * other function in the shared code. The i40e_hw structure should be
540 * memset to 0 prior to calling this function. The following fields in
541 * hw structure should be filled in prior to calling this function:
542 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
543 * subsystem_vendor_id, and revision_id
544 **/
545i40e_status i40e_init_shared_code(struct i40e_hw *hw)
546{
547 i40e_status status = 0;
548 u32 reg;
549
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]550 i40e_set_mac_type(hw);
551
552 switch (hw->mac.type) {
553 case I40E_MAC_XL710:
554 break;
555 default:
556 return I40E_ERR_DEVICE_NOT_SUPPORTED;
557 break;
558 }
559
Shannon Nelsonaf89d26c2013-12-11 08:17:14 +0000[diff] [blame]560 hw->phy.get_link_info = true;
561
562 /* Determine port number */
563 reg = rd32(hw, I40E_PFGEN_PORTNUM);
564 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
565 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
566 hw->port = (u8)reg;
567
Shannon Nelson5f9116a2013-12-11 08:17:13 +0000[diff] [blame]568 /* Determine the PF number based on the PCI fn */
569 reg = rd32(hw, I40E_GLPCI_CAPSUP);
570 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
571 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
572 else
573 hw->pf_id = (u8)hw->bus.func;
574
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]575 status = i40e_init_nvm(hw);
576 return status;
577}
578
579/**
580 * i40e_aq_mac_address_read - Retrieve the MAC addresses
581 * @hw: pointer to the hw struct
582 * @flags: a return indicator of what addresses were added to the addr store
583 * @addrs: the requestor's mac addr store
584 * @cmd_details: pointer to command details structure or NULL
585 **/
586static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
587 u16 *flags,
588 struct i40e_aqc_mac_address_read_data *addrs,
589 struct i40e_asq_cmd_details *cmd_details)
590{
591 struct i40e_aq_desc desc;
592 struct i40e_aqc_mac_address_read *cmd_data =
593 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
594 i40e_status status;
595
596 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
597 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
598
599 status = i40e_asq_send_command(hw, &desc, addrs,
600 sizeof(*addrs), cmd_details);
601 *flags = le16_to_cpu(cmd_data->command_flags);
602
603 return status;
604}
605
606/**
607 * i40e_aq_mac_address_write - Change the MAC addresses
608 * @hw: pointer to the hw struct
609 * @flags: indicates which MAC to be written
610 * @mac_addr: address to write
611 * @cmd_details: pointer to command details structure or NULL
612 **/
613i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
614 u16 flags, u8 *mac_addr,
615 struct i40e_asq_cmd_details *cmd_details)
616{
617 struct i40e_aq_desc desc;
618 struct i40e_aqc_mac_address_write *cmd_data =
619 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
620 i40e_status status;
621
622 i40e_fill_default_direct_cmd_desc(&desc,
623 i40e_aqc_opc_mac_address_write);
624 cmd_data->command_flags = cpu_to_le16(flags);
Kamil Krawczyk55c29c32013-12-18 13:45:52 +0000[diff] [blame]625 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
626 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
627 ((u32)mac_addr[3] << 16) |
628 ((u32)mac_addr[4] << 8) |
629 mac_addr[5]);
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]630
631 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
632
633 return status;
634}
635
636/**
637 * i40e_get_mac_addr - get MAC address
638 * @hw: pointer to the HW structure
639 * @mac_addr: pointer to MAC address
640 *
641 * Reads the adapter's MAC address from register
642 **/
643i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
644{
645 struct i40e_aqc_mac_address_read_data addrs;
646 i40e_status status;
647 u16 flags = 0;
648
649 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
650
651 if (flags & I40E_AQC_LAN_ADDR_VALID)
652 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
653
654 return status;
655}
656
657/**
Matt Jared351499ab2014-04-23 04:50:03 +0000[diff] [blame]658 * i40e_pre_tx_queue_cfg - pre tx queue configure
659 * @hw: pointer to the HW structure
660 * @queue: target pf queue index
661 * @enable: state change request
662 *
663 * Handles hw requirement to indicate intention to enable
664 * or disable target queue.
665 **/
666void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
667{
Shannon Nelsondfb699f2014-05-22 06:32:28 +0000[diff] [blame]668 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
Matt Jared351499ab2014-04-23 04:50:03 +0000[diff] [blame]669 u32 reg_block = 0;
Shannon Nelsondfb699f2014-05-22 06:32:28 +0000[diff] [blame]670 u32 reg_val;
Matt Jared351499ab2014-04-23 04:50:03 +0000[diff] [blame]671
Christopher Pau24a768c2014-06-04 20:41:59 +0000[diff] [blame^]672 if (abs_queue_idx >= 128) {
Matt Jared351499ab2014-04-23 04:50:03 +0000[diff] [blame]673 reg_block = abs_queue_idx / 128;
Christopher Pau24a768c2014-06-04 20:41:59 +0000[diff] [blame^]674 abs_queue_idx %= 128;
675 }
Matt Jared351499ab2014-04-23 04:50:03 +0000[diff] [blame]676
677 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
678 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
679 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
680
681 if (enable)
682 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
683 else
684 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
685
686 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
687}
688
689/**
Jesse Brandeburgbe405eb2013-11-20 10:02:50 +0000[diff] [blame]690 * i40e_get_media_type - Gets media type
691 * @hw: pointer to the hardware structure
692 **/
693static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
694{
695 enum i40e_media_type media;
696
697 switch (hw->phy.link_info.phy_type) {
698 case I40E_PHY_TYPE_10GBASE_SR:
699 case I40E_PHY_TYPE_10GBASE_LR:
700 case I40E_PHY_TYPE_40GBASE_SR4:
701 case I40E_PHY_TYPE_40GBASE_LR4:
702 media = I40E_MEDIA_TYPE_FIBER;
703 break;
704 case I40E_PHY_TYPE_100BASE_TX:
705 case I40E_PHY_TYPE_1000BASE_T:
706 case I40E_PHY_TYPE_10GBASE_T:
707 media = I40E_MEDIA_TYPE_BASET;
708 break;
709 case I40E_PHY_TYPE_10GBASE_CR1_CU:
710 case I40E_PHY_TYPE_40GBASE_CR4_CU:
711 case I40E_PHY_TYPE_10GBASE_CR1:
712 case I40E_PHY_TYPE_40GBASE_CR4:
713 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
714 media = I40E_MEDIA_TYPE_DA;
715 break;
716 case I40E_PHY_TYPE_1000BASE_KX:
717 case I40E_PHY_TYPE_10GBASE_KX4:
718 case I40E_PHY_TYPE_10GBASE_KR:
719 case I40E_PHY_TYPE_40GBASE_KR4:
720 media = I40E_MEDIA_TYPE_BACKPLANE;
721 break;
722 case I40E_PHY_TYPE_SGMII:
723 case I40E_PHY_TYPE_XAUI:
724 case I40E_PHY_TYPE_XFI:
725 case I40E_PHY_TYPE_XLAUI:
726 case I40E_PHY_TYPE_XLPPI:
727 default:
728 media = I40E_MEDIA_TYPE_UNKNOWN;
729 break;
730 }
731
732 return media;
733}
734
Jesse Brandeburg7134f9c2013-11-26 08:56:05 +0000[diff] [blame]735#define I40E_PF_RESET_WAIT_COUNT_A0 200
Shannon Nelsond0ff5682014-04-23 04:50:06 +0000[diff] [blame]736#define I40E_PF_RESET_WAIT_COUNT 100
Jesse Brandeburgbe405eb2013-11-20 10:02:50 +0000[diff] [blame]737/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]738 * i40e_pf_reset - Reset the PF
739 * @hw: pointer to the hardware structure
740 *
741 * Assuming someone else has triggered a global reset,
742 * assure the global reset is complete and then reset the PF
743 **/
744i40e_status i40e_pf_reset(struct i40e_hw *hw)
745{
Jesse Brandeburg7134f9c2013-11-26 08:56:05 +0000[diff] [blame]746 u32 cnt = 0;
Shannon Nelson42794bd2013-12-11 08:17:10 +0000[diff] [blame]747 u32 cnt1 = 0;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]748 u32 reg = 0;
749 u32 grst_del;
750
751 /* Poll for Global Reset steady state in case of recent GRST.
752 * The grst delay value is in 100ms units, and we'll wait a
753 * couple counts longer to be sure we don't just miss the end.
754 */
755 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
756 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
Jesse Brandeburg7134f9c2013-11-26 08:56:05 +0000[diff] [blame]757 for (cnt = 0; cnt < grst_del + 2; cnt++) {
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]758 reg = rd32(hw, I40E_GLGEN_RSTAT);
759 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
760 break;
761 msleep(100);
762 }
763 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
764 hw_dbg(hw, "Global reset polling failed to complete.\n");
765 return I40E_ERR_RESET_FAILED;
766 }
767
Shannon Nelson42794bd2013-12-11 08:17:10 +0000[diff] [blame]768 /* Now Wait for the FW to be ready */
769 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
770 reg = rd32(hw, I40E_GLNVM_ULD);
771 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
772 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
773 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
774 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
775 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
776 break;
777 }
778 usleep_range(10000, 20000);
779 }
780 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
781 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
782 hw_dbg(hw, "wait for FW Reset complete timedout\n");
783 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
784 return I40E_ERR_RESET_FAILED;
785 }
786
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]787 /* If there was a Global Reset in progress when we got here,
788 * we don't need to do the PF Reset
789 */
Jesse Brandeburg7134f9c2013-11-26 08:56:05 +0000[diff] [blame]790 if (!cnt) {
791 if (hw->revision_id == 0)
792 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
793 else
794 cnt = I40E_PF_RESET_WAIT_COUNT;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]795 reg = rd32(hw, I40E_PFGEN_CTRL);
796 wr32(hw, I40E_PFGEN_CTRL,
797 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
Jesse Brandeburg7134f9c2013-11-26 08:56:05 +0000[diff] [blame]798 for (; cnt; cnt--) {
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]799 reg = rd32(hw, I40E_PFGEN_CTRL);
800 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
801 break;
802 usleep_range(1000, 2000);
803 }
804 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
805 hw_dbg(hw, "PF reset polling failed to complete.\n");
806 return I40E_ERR_RESET_FAILED;
807 }
808 }
809
810 i40e_clear_pxe_mode(hw);
Shannon Nelson922680b2013-12-18 05:29:17 +0000[diff] [blame]811
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]812 return 0;
813}
814
815/**
Shannon Nelson838d41d2014-06-04 20:41:27 +0000[diff] [blame]816 * i40e_clear_hw - clear out any left over hw state
817 * @hw: pointer to the hw struct
818 *
819 * Clear queues and interrupts, typically called at init time,
820 * but after the capabilities have been found so we know how many
821 * queues and msix vectors have been allocated.
822 **/
823void i40e_clear_hw(struct i40e_hw *hw)
824{
825 u32 num_queues, base_queue;
826 u32 num_pf_int;
827 u32 num_vf_int;
828 u32 num_vfs;
829 u32 i, j;
830 u32 val;
831 u32 eol = 0x7ff;
832
833 /* get number of interrupts, queues, and vfs */
834 val = rd32(hw, I40E_GLPCI_CNF2);
835 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
836 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
837 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
838 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
839
840 val = rd32(hw, I40E_PFLAN_QALLOC);
841 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
842 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
843 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
844 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
845 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
846 num_queues = (j - base_queue) + 1;
847 else
848 num_queues = 0;
849
850 val = rd32(hw, I40E_PF_VT_PFALLOC);
851 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
852 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
853 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
854 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
855 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
856 num_vfs = (j - i) + 1;
857 else
858 num_vfs = 0;
859
860 /* stop all the interrupts */
861 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
862 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
863 for (i = 0; i < num_pf_int - 2; i++)
864 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
865
866 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
867 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
868 wr32(hw, I40E_PFINT_LNKLST0, val);
869 for (i = 0; i < num_pf_int - 2; i++)
870 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
871 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
872 for (i = 0; i < num_vfs; i++)
873 wr32(hw, I40E_VPINT_LNKLST0(i), val);
874 for (i = 0; i < num_vf_int - 2; i++)
875 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
876
877 /* warn the HW of the coming Tx disables */
878 for (i = 0; i < num_queues; i++) {
879 u32 abs_queue_idx = base_queue + i;
880 u32 reg_block = 0;
881
882 if (abs_queue_idx >= 128) {
883 reg_block = abs_queue_idx / 128;
884 abs_queue_idx %= 128;
885 }
886
887 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
888 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
889 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
890 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
891
892 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
893 }
894 udelay(400);
895
896 /* stop all the queues */
897 for (i = 0; i < num_queues; i++) {
898 wr32(hw, I40E_QINT_TQCTL(i), 0);
899 wr32(hw, I40E_QTX_ENA(i), 0);
900 wr32(hw, I40E_QINT_RQCTL(i), 0);
901 wr32(hw, I40E_QRX_ENA(i), 0);
902 }
903
904 /* short wait for all queue disables to settle */
905 udelay(50);
906}
907
908/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]909 * i40e_clear_pxe_mode - clear pxe operations mode
910 * @hw: pointer to the hw struct
911 *
912 * Make sure all PXE mode settings are cleared, including things
913 * like descriptor fetch/write-back mode.
914 **/
915void i40e_clear_pxe_mode(struct i40e_hw *hw)
916{
917 u32 reg;
918
Shannon Nelsonc9b9b0a2014-04-09 05:59:05 +0000[diff] [blame]919 if (i40e_check_asq_alive(hw))
920 i40e_aq_clear_pxe_mode(hw, NULL);
921
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]922 /* Clear single descriptor fetch/write-back mode */
923 reg = rd32(hw, I40E_GLLAN_RCTL_0);
Jesse Brandeburg7134f9c2013-11-26 08:56:05 +0000[diff] [blame]924
925 if (hw->revision_id == 0) {
926 /* As a work around clear PXE_MODE instead of setting it */
927 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
928 } else {
929 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
930 }
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]931}
932
933/**
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]934 * i40e_led_is_mine - helper to find matching led
935 * @hw: pointer to the hw struct
936 * @idx: index into GPIO registers
937 *
938 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
939 */
940static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
941{
942 u32 gpio_val = 0;
943 u32 port;
944
945 if (!hw->func_caps.led[idx])
946 return 0;
947
948 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
949 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
950 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
951
952 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
953 * if it is not our port then ignore
954 */
955 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
956 (port != hw->port))
957 return 0;
958
959 return gpio_val;
960}
961
962#define I40E_LED0 22
963#define I40E_LINK_ACTIVITY 0xC
964
965/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]966 * i40e_led_get - return current on/off mode
967 * @hw: pointer to the hw struct
968 *
969 * The value returned is the 'mode' field as defined in the
970 * GPIO register definitions: 0x0 = off, 0xf = on, and other
971 * values are variations of possible behaviors relating to
972 * blink, link, and wire.
973 **/
974u32 i40e_led_get(struct i40e_hw *hw)
975{
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]976 u32 mode = 0;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]977 int i;
978
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]979 /* as per the documentation GPIO 22-29 are the LED
980 * GPIO pins named LED0..LED7
981 */
982 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
983 u32 gpio_val = i40e_led_is_mine(hw, i);
984
985 if (!gpio_val)
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]986 continue;
987
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]988 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
989 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]990 break;
991 }
992
993 return mode;
994}
995
996/**
997 * i40e_led_set - set new on/off mode
998 * @hw: pointer to the hw struct
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]999 * @mode: 0=off, 0xf=on (else see manual for mode details)
1000 * @blink: true if the LED should blink when on, false if steady
1001 *
1002 * if this function is used to turn on the blink it should
1003 * be used to disable the blink when restoring the original state.
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1004 **/
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]1005void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1006{
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1007 int i;
1008
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]1009 if (mode & 0xfffffff0)
1010 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1011
1012 /* as per the documentation GPIO 22-29 are the LED
1013 * GPIO pins named LED0..LED7
1014 */
1015 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1016 u32 gpio_val = i40e_led_is_mine(hw, i);
1017
1018 if (!gpio_val)
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1019 continue;
1020
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1021 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]1022 /* this & is a bit of paranoia, but serves as a range check */
1023 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1024 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1025
1026 if (mode == I40E_LINK_ACTIVITY)
1027 blink = false;
1028
1029 gpio_val |= (blink ? 1 : 0) <<
1030 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
1031
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1032 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
Jesse Brandeburg0556a9e2013-11-28 06:39:33 +0000[diff] [blame]1033 break;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1034 }
1035}
1036
1037/* Admin command wrappers */
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1038
1039/**
Shannon Nelsonc9b9b0a2014-04-09 05:59:05 +0000[diff] [blame]1040 * i40e_aq_clear_pxe_mode
1041 * @hw: pointer to the hw struct
1042 * @cmd_details: pointer to command details structure or NULL
1043 *
1044 * Tell the firmware that the driver is taking over from PXE
1045 **/
1046i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1047 struct i40e_asq_cmd_details *cmd_details)
1048{
1049 i40e_status status;
1050 struct i40e_aq_desc desc;
1051 struct i40e_aqc_clear_pxe *cmd =
1052 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1053
1054 i40e_fill_default_direct_cmd_desc(&desc,
1055 i40e_aqc_opc_clear_pxe_mode);
1056
1057 cmd->rx_cnt = 0x2;
1058
1059 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1060
1061 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1062
1063 return status;
1064}
1065
1066/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1067 * i40e_aq_set_link_restart_an
1068 * @hw: pointer to the hw struct
Catherine Sullivan1ac978a2014-06-04 01:23:20 +0000[diff] [blame]1069 * @enable_link: if true: enable link, if false: disable link
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1070 * @cmd_details: pointer to command details structure or NULL
1071 *
1072 * Sets up the link and restarts the Auto-Negotiation over the link.
1073 **/
1074i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
Catherine Sullivan1ac978a2014-06-04 01:23:20 +0000[diff] [blame]1075 bool enable_link,
1076 struct i40e_asq_cmd_details *cmd_details)
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1077{
1078 struct i40e_aq_desc desc;
1079 struct i40e_aqc_set_link_restart_an *cmd =
1080 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1081 i40e_status status;
1082
1083 i40e_fill_default_direct_cmd_desc(&desc,
1084 i40e_aqc_opc_set_link_restart_an);
1085
1086 cmd->command = I40E_AQ_PHY_RESTART_AN;
Catherine Sullivan1ac978a2014-06-04 01:23:20 +0000[diff] [blame]1087 if (enable_link)
1088 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1089 else
1090 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1091
1092 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1093
1094 return status;
1095}
1096
1097/**
1098 * i40e_aq_get_link_info
1099 * @hw: pointer to the hw struct
1100 * @enable_lse: enable/disable LinkStatusEvent reporting
1101 * @link: pointer to link status structure - optional
1102 * @cmd_details: pointer to command details structure or NULL
1103 *
1104 * Returns the link status of the adapter.
1105 **/
1106i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1107 bool enable_lse, struct i40e_link_status *link,
1108 struct i40e_asq_cmd_details *cmd_details)
1109{
1110 struct i40e_aq_desc desc;
1111 struct i40e_aqc_get_link_status *resp =
1112 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1113 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1114 i40e_status status;
1115 u16 command_flags;
1116
1117 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1118
1119 if (enable_lse)
1120 command_flags = I40E_AQ_LSE_ENABLE;
1121 else
1122 command_flags = I40E_AQ_LSE_DISABLE;
1123 resp->command_flags = cpu_to_le16(command_flags);
1124
1125 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1126
1127 if (status)
1128 goto aq_get_link_info_exit;
1129
1130 /* save off old link status information */
Mitch Williamsc36bd4a72013-12-18 13:46:04 +0000[diff] [blame]1131 hw->phy.link_info_old = *hw_link_info;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1132
1133 /* update link status */
1134 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
Jesse Brandeburgbe405eb2013-11-20 10:02:50 +0000[diff] [blame]1135 hw->phy.media_type = i40e_get_media_type(hw);
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1136 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1137 hw_link_info->link_info = resp->link_info;
1138 hw_link_info->an_info = resp->an_info;
1139 hw_link_info->ext_info = resp->ext_info;
Kamil Krawczyk639dc372013-11-20 10:03:07 +0000[diff] [blame]1140 hw_link_info->loopback = resp->loopback;
Neerav Parikh6bb3f232014-04-01 07:11:56 +0000[diff] [blame]1141 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1142 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1143
1144 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1145 hw_link_info->crc_enable = true;
1146 else
1147 hw_link_info->crc_enable = false;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1148
1149 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1150 hw_link_info->lse_enable = true;
1151 else
1152 hw_link_info->lse_enable = false;
1153
1154 /* save link status information */
1155 if (link)
Jesse Brandeburgd7595a22013-09-13 08:23:22 +0000[diff] [blame]1156 *link = *hw_link_info;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1157
1158 /* flag cleared so helper functions don't call AQ again */
1159 hw->phy.get_link_info = false;
1160
1161aq_get_link_info_exit:
1162 return status;
1163}
1164
1165/**
1166 * i40e_aq_add_vsi
1167 * @hw: pointer to the hw struct
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]1168 * @vsi_ctx: pointer to a vsi context struct
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1169 * @cmd_details: pointer to command details structure or NULL
1170 *
1171 * Add a VSI context to the hardware.
1172**/
1173i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1174 struct i40e_vsi_context *vsi_ctx,
1175 struct i40e_asq_cmd_details *cmd_details)
1176{
1177 struct i40e_aq_desc desc;
1178 struct i40e_aqc_add_get_update_vsi *cmd =
1179 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1180 struct i40e_aqc_add_get_update_vsi_completion *resp =
1181 (struct i40e_aqc_add_get_update_vsi_completion *)
1182 &desc.params.raw;
1183 i40e_status status;
1184
1185 i40e_fill_default_direct_cmd_desc(&desc,
1186 i40e_aqc_opc_add_vsi);
1187
1188 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1189 cmd->connection_type = vsi_ctx->connection_type;
1190 cmd->vf_id = vsi_ctx->vf_num;
1191 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1192
1193 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1194
1195 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1196 sizeof(vsi_ctx->info), cmd_details);
1197
1198 if (status)
1199 goto aq_add_vsi_exit;
1200
1201 vsi_ctx->seid = le16_to_cpu(resp->seid);
1202 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1203 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1204 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1205
1206aq_add_vsi_exit:
1207 return status;
1208}
1209
1210/**
1211 * i40e_aq_set_vsi_unicast_promiscuous
1212 * @hw: pointer to the hw struct
1213 * @seid: vsi number
1214 * @set: set unicast promiscuous enable/disable
1215 * @cmd_details: pointer to command details structure or NULL
1216 **/
1217i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
Mitch Williams885552a2013-12-21 05:44:41 +0000[diff] [blame]1218 u16 seid, bool set,
1219 struct i40e_asq_cmd_details *cmd_details)
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1220{
1221 struct i40e_aq_desc desc;
1222 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1223 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1224 i40e_status status;
1225 u16 flags = 0;
1226
1227 i40e_fill_default_direct_cmd_desc(&desc,
1228 i40e_aqc_opc_set_vsi_promiscuous_modes);
1229
1230 if (set)
1231 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1232
1233 cmd->promiscuous_flags = cpu_to_le16(flags);
1234
1235 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1236
1237 cmd->seid = cpu_to_le16(seid);
1238 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1239
1240 return status;
1241}
1242
1243/**
1244 * i40e_aq_set_vsi_multicast_promiscuous
1245 * @hw: pointer to the hw struct
1246 * @seid: vsi number
1247 * @set: set multicast promiscuous enable/disable
1248 * @cmd_details: pointer to command details structure or NULL
1249 **/
1250i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1251 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1252{
1253 struct i40e_aq_desc desc;
1254 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1255 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1256 i40e_status status;
1257 u16 flags = 0;
1258
1259 i40e_fill_default_direct_cmd_desc(&desc,
1260 i40e_aqc_opc_set_vsi_promiscuous_modes);
1261
1262 if (set)
1263 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1264
1265 cmd->promiscuous_flags = cpu_to_le16(flags);
1266
1267 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1268
1269 cmd->seid = cpu_to_le16(seid);
1270 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1271
1272 return status;
1273}
1274
1275/**
1276 * i40e_aq_set_vsi_broadcast
1277 * @hw: pointer to the hw struct
1278 * @seid: vsi number
1279 * @set_filter: true to set filter, false to clear filter
1280 * @cmd_details: pointer to command details structure or NULL
1281 *
1282 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1283 **/
1284i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1285 u16 seid, bool set_filter,
1286 struct i40e_asq_cmd_details *cmd_details)
1287{
1288 struct i40e_aq_desc desc;
1289 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1290 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1291 i40e_status status;
1292
1293 i40e_fill_default_direct_cmd_desc(&desc,
1294 i40e_aqc_opc_set_vsi_promiscuous_modes);
1295
1296 if (set_filter)
1297 cmd->promiscuous_flags
1298 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1299 else
1300 cmd->promiscuous_flags
1301 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1302
1303 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1304 cmd->seid = cpu_to_le16(seid);
1305 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1306
1307 return status;
1308}
1309
1310/**
1311 * i40e_get_vsi_params - get VSI configuration info
1312 * @hw: pointer to the hw struct
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]1313 * @vsi_ctx: pointer to a vsi context struct
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1314 * @cmd_details: pointer to command details structure or NULL
1315 **/
1316i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1317 struct i40e_vsi_context *vsi_ctx,
1318 struct i40e_asq_cmd_details *cmd_details)
1319{
1320 struct i40e_aq_desc desc;
Shannon Nelsonf5ac8572013-11-28 06:39:43 +0000[diff] [blame]1321 struct i40e_aqc_add_get_update_vsi *cmd =
1322 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1323 struct i40e_aqc_add_get_update_vsi_completion *resp =
1324 (struct i40e_aqc_add_get_update_vsi_completion *)
1325 &desc.params.raw;
1326 i40e_status status;
1327
1328 i40e_fill_default_direct_cmd_desc(&desc,
1329 i40e_aqc_opc_get_vsi_parameters);
1330
Shannon Nelsonf5ac8572013-11-28 06:39:43 +0000[diff] [blame]1331 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1332
1333 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1334
1335 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1336 sizeof(vsi_ctx->info), NULL);
1337
1338 if (status)
1339 goto aq_get_vsi_params_exit;
1340
1341 vsi_ctx->seid = le16_to_cpu(resp->seid);
1342 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1343 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1344 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1345
1346aq_get_vsi_params_exit:
1347 return status;
1348}
1349
1350/**
1351 * i40e_aq_update_vsi_params
1352 * @hw: pointer to the hw struct
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]1353 * @vsi_ctx: pointer to a vsi context struct
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1354 * @cmd_details: pointer to command details structure or NULL
1355 *
1356 * Update a VSI context.
1357 **/
1358i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1359 struct i40e_vsi_context *vsi_ctx,
1360 struct i40e_asq_cmd_details *cmd_details)
1361{
1362 struct i40e_aq_desc desc;
Shannon Nelsonf5ac8572013-11-28 06:39:43 +0000[diff] [blame]1363 struct i40e_aqc_add_get_update_vsi *cmd =
1364 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1365 i40e_status status;
1366
1367 i40e_fill_default_direct_cmd_desc(&desc,
1368 i40e_aqc_opc_update_vsi_parameters);
Shannon Nelsonf5ac8572013-11-28 06:39:43 +0000[diff] [blame]1369 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1370
1371 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1372
1373 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1374 sizeof(vsi_ctx->info), cmd_details);
1375
1376 return status;
1377}
1378
1379/**
1380 * i40e_aq_get_switch_config
1381 * @hw: pointer to the hardware structure
1382 * @buf: pointer to the result buffer
1383 * @buf_size: length of input buffer
1384 * @start_seid: seid to start for the report, 0 == beginning
1385 * @cmd_details: pointer to command details structure or NULL
1386 *
1387 * Fill the buf with switch configuration returned from AdminQ command
1388 **/
1389i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1390 struct i40e_aqc_get_switch_config_resp *buf,
1391 u16 buf_size, u16 *start_seid,
1392 struct i40e_asq_cmd_details *cmd_details)
1393{
1394 struct i40e_aq_desc desc;
1395 struct i40e_aqc_switch_seid *scfg =
1396 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1397 i40e_status status;
1398
1399 i40e_fill_default_direct_cmd_desc(&desc,
1400 i40e_aqc_opc_get_switch_config);
1401 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1402 if (buf_size > I40E_AQ_LARGE_BUF)
1403 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1404 scfg->seid = cpu_to_le16(*start_seid);
1405
1406 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1407 *start_seid = le16_to_cpu(scfg->seid);
1408
1409 return status;
1410}
1411
1412/**
1413 * i40e_aq_get_firmware_version
1414 * @hw: pointer to the hw struct
1415 * @fw_major_version: firmware major version
1416 * @fw_minor_version: firmware minor version
1417 * @api_major_version: major queue version
1418 * @api_minor_version: minor queue version
1419 * @cmd_details: pointer to command details structure or NULL
1420 *
1421 * Get the firmware version from the admin queue commands
1422 **/
1423i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1424 u16 *fw_major_version, u16 *fw_minor_version,
1425 u16 *api_major_version, u16 *api_minor_version,
1426 struct i40e_asq_cmd_details *cmd_details)
1427{
1428 struct i40e_aq_desc desc;
1429 struct i40e_aqc_get_version *resp =
1430 (struct i40e_aqc_get_version *)&desc.params.raw;
1431 i40e_status status;
1432
1433 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1434
1435 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1436
1437 if (!status) {
1438 if (fw_major_version != NULL)
1439 *fw_major_version = le16_to_cpu(resp->fw_major);
1440 if (fw_minor_version != NULL)
1441 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1442 if (api_major_version != NULL)
1443 *api_major_version = le16_to_cpu(resp->api_major);
1444 if (api_minor_version != NULL)
1445 *api_minor_version = le16_to_cpu(resp->api_minor);
1446 }
1447
1448 return status;
1449}
1450
1451/**
1452 * i40e_aq_send_driver_version
1453 * @hw: pointer to the hw struct
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1454 * @dv: driver's major, minor version
1455 * @cmd_details: pointer to command details structure or NULL
1456 *
1457 * Send the driver version to the firmware
1458 **/
1459i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1460 struct i40e_driver_version *dv,
1461 struct i40e_asq_cmd_details *cmd_details)
1462{
1463 struct i40e_aq_desc desc;
1464 struct i40e_aqc_driver_version *cmd =
1465 (struct i40e_aqc_driver_version *)&desc.params.raw;
1466 i40e_status status;
Kevin Scott9d2f98e2014-04-01 07:11:52 +0000[diff] [blame]1467 u16 len;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1468
1469 if (dv == NULL)
1470 return I40E_ERR_PARAM;
1471
1472 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1473
1474 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1475 cmd->driver_major_ver = dv->major_version;
1476 cmd->driver_minor_ver = dv->minor_version;
1477 cmd->driver_build_ver = dv->build_version;
1478 cmd->driver_subbuild_ver = dv->subbuild_version;
Shannon Nelsond2466012014-04-01 07:11:45 +0000[diff] [blame]1479
1480 len = 0;
1481 while (len < sizeof(dv->driver_string) &&
1482 (dv->driver_string[len] < 0x80) &&
1483 dv->driver_string[len])
1484 len++;
1485 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
1486 len, cmd_details);
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1487
1488 return status;
1489}
1490
1491/**
1492 * i40e_get_link_status - get status of the HW network link
1493 * @hw: pointer to the hw struct
1494 *
1495 * Returns true if link is up, false if link is down.
1496 *
1497 * Side effect: LinkStatusEvent reporting becomes enabled
1498 **/
1499bool i40e_get_link_status(struct i40e_hw *hw)
1500{
1501 i40e_status status = 0;
1502 bool link_status = false;
1503
1504 if (hw->phy.get_link_info) {
1505 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1506
1507 if (status)
1508 goto i40e_get_link_status_exit;
1509 }
1510
1511 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1512
1513i40e_get_link_status_exit:
1514 return link_status;
1515}
1516
1517/**
1518 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1519 * @hw: pointer to the hw struct
1520 * @uplink_seid: the MAC or other gizmo SEID
1521 * @downlink_seid: the VSI SEID
1522 * @enabled_tc: bitmap of TCs to be enabled
1523 * @default_port: true for default port VSI, false for control port
Kevin Scotte1c51b952013-11-20 10:02:51 +0000[diff] [blame]1524 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1525 * @veb_seid: pointer to where to put the resulting VEB SEID
1526 * @cmd_details: pointer to command details structure or NULL
1527 *
1528 * This asks the FW to add a VEB between the uplink and downlink
1529 * elements. If the uplink SEID is 0, this will be a floating VEB.
1530 **/
1531i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1532 u16 downlink_seid, u8 enabled_tc,
Kevin Scotte1c51b952013-11-20 10:02:51 +0000[diff] [blame]1533 bool default_port, bool enable_l2_filtering,
1534 u16 *veb_seid,
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1535 struct i40e_asq_cmd_details *cmd_details)
1536{
1537 struct i40e_aq_desc desc;
1538 struct i40e_aqc_add_veb *cmd =
1539 (struct i40e_aqc_add_veb *)&desc.params.raw;
1540 struct i40e_aqc_add_veb_completion *resp =
1541 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1542 i40e_status status;
1543 u16 veb_flags = 0;
1544
1545 /* SEIDs need to either both be set or both be 0 for floating VEB */
1546 if (!!uplink_seid != !!downlink_seid)
1547 return I40E_ERR_PARAM;
1548
1549 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1550
1551 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1552 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1553 cmd->enable_tcs = enabled_tc;
1554 if (!uplink_seid)
1555 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1556 if (default_port)
1557 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1558 else
1559 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
Kevin Scotte1c51b952013-11-20 10:02:51 +0000[diff] [blame]1560
1561 if (enable_l2_filtering)
1562 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1563
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1564 cmd->veb_flags = cpu_to_le16(veb_flags);
1565
1566 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1567
1568 if (!status && veb_seid)
1569 *veb_seid = le16_to_cpu(resp->veb_seid);
1570
1571 return status;
1572}
1573
1574/**
1575 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1576 * @hw: pointer to the hw struct
1577 * @veb_seid: the SEID of the VEB to query
1578 * @switch_id: the uplink switch id
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]1579 * @floating: set to true if the VEB is floating
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1580 * @statistic_index: index of the stats counter block for this VEB
1581 * @vebs_used: number of VEB's used by function
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]1582 * @vebs_free: total VEB's not reserved by any function
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1583 * @cmd_details: pointer to command details structure or NULL
1584 *
1585 * This retrieves the parameters for a particular VEB, specified by
1586 * uplink_seid, and returns them to the caller.
1587 **/
1588i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1589 u16 veb_seid, u16 *switch_id,
1590 bool *floating, u16 *statistic_index,
1591 u16 *vebs_used, u16 *vebs_free,
1592 struct i40e_asq_cmd_details *cmd_details)
1593{
1594 struct i40e_aq_desc desc;
1595 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1596 (struct i40e_aqc_get_veb_parameters_completion *)
1597 &desc.params.raw;
1598 i40e_status status;
1599
1600 if (veb_seid == 0)
1601 return I40E_ERR_PARAM;
1602
1603 i40e_fill_default_direct_cmd_desc(&desc,
1604 i40e_aqc_opc_get_veb_parameters);
1605 cmd_resp->seid = cpu_to_le16(veb_seid);
1606
1607 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1608 if (status)
1609 goto get_veb_exit;
1610
1611 if (switch_id)
1612 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1613 if (statistic_index)
1614 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1615 if (vebs_used)
1616 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1617 if (vebs_free)
1618 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1619 if (floating) {
1620 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1621 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1622 *floating = true;
1623 else
1624 *floating = false;
1625 }
1626
1627get_veb_exit:
1628 return status;
1629}
1630
1631/**
1632 * i40e_aq_add_macvlan
1633 * @hw: pointer to the hw struct
1634 * @seid: VSI for the mac address
1635 * @mv_list: list of macvlans to be added
1636 * @count: length of the list
1637 * @cmd_details: pointer to command details structure or NULL
1638 *
1639 * Add MAC/VLAN addresses to the HW filtering
1640 **/
1641i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1642 struct i40e_aqc_add_macvlan_element_data *mv_list,
1643 u16 count, struct i40e_asq_cmd_details *cmd_details)
1644{
1645 struct i40e_aq_desc desc;
1646 struct i40e_aqc_macvlan *cmd =
1647 (struct i40e_aqc_macvlan *)&desc.params.raw;
1648 i40e_status status;
1649 u16 buf_size;
1650
1651 if (count == 0 || !mv_list || !hw)
1652 return I40E_ERR_PARAM;
1653
1654 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1655
1656 /* prep the rest of the request */
1657 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1658 cmd->num_addresses = cpu_to_le16(count);
1659 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1660 cmd->seid[1] = 0;
1661 cmd->seid[2] = 0;
1662
1663 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1664 if (buf_size > I40E_AQ_LARGE_BUF)
1665 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1666
1667 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1668 cmd_details);
1669
1670 return status;
1671}
1672
1673/**
1674 * i40e_aq_remove_macvlan
1675 * @hw: pointer to the hw struct
1676 * @seid: VSI for the mac address
1677 * @mv_list: list of macvlans to be removed
1678 * @count: length of the list
1679 * @cmd_details: pointer to command details structure or NULL
1680 *
1681 * Remove MAC/VLAN addresses from the HW filtering
1682 **/
1683i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1684 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1685 u16 count, struct i40e_asq_cmd_details *cmd_details)
1686{
1687 struct i40e_aq_desc desc;
1688 struct i40e_aqc_macvlan *cmd =
1689 (struct i40e_aqc_macvlan *)&desc.params.raw;
1690 i40e_status status;
1691 u16 buf_size;
1692
1693 if (count == 0 || !mv_list || !hw)
1694 return I40E_ERR_PARAM;
1695
1696 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1697
1698 /* prep the rest of the request */
1699 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1700 cmd->num_addresses = cpu_to_le16(count);
1701 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1702 cmd->seid[1] = 0;
1703 cmd->seid[2] = 0;
1704
1705 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1706 if (buf_size > I40E_AQ_LARGE_BUF)
1707 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1708
1709 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1710 cmd_details);
1711
1712 return status;
1713}
1714
1715/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1716 * i40e_aq_send_msg_to_vf
1717 * @hw: pointer to the hardware structure
1718 * @vfid: vf id to send msg
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]1719 * @v_opcode: opcodes for VF-PF communication
1720 * @v_retval: return error code
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1721 * @msg: pointer to the msg buffer
1722 * @msglen: msg length
1723 * @cmd_details: pointer to command details
1724 *
1725 * send msg to vf
1726 **/
1727i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1728 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1729 struct i40e_asq_cmd_details *cmd_details)
1730{
1731 struct i40e_aq_desc desc;
1732 struct i40e_aqc_pf_vf_message *cmd =
1733 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1734 i40e_status status;
1735
1736 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1737 cmd->id = cpu_to_le32(vfid);
1738 desc.cookie_high = cpu_to_le32(v_opcode);
1739 desc.cookie_low = cpu_to_le32(v_retval);
1740 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1741 if (msglen) {
1742 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1743 I40E_AQ_FLAG_RD));
1744 if (msglen > I40E_AQ_LARGE_BUF)
1745 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1746 desc.datalen = cpu_to_le16(msglen);
1747 }
1748 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1749
1750 return status;
1751}
1752
1753/**
1754 * i40e_aq_set_hmc_resource_profile
1755 * @hw: pointer to the hw struct
1756 * @profile: type of profile the HMC is to be set as
1757 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1758 * @cmd_details: pointer to command details structure or NULL
1759 *
1760 * set the HMC profile of the device.
1761 **/
1762i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
1763 enum i40e_aq_hmc_profile profile,
1764 u8 pe_vf_enabled_count,
1765 struct i40e_asq_cmd_details *cmd_details)
1766{
1767 struct i40e_aq_desc desc;
1768 struct i40e_aq_get_set_hmc_resource_profile *cmd =
1769 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
1770 i40e_status status;
1771
1772 i40e_fill_default_direct_cmd_desc(&desc,
1773 i40e_aqc_opc_set_hmc_resource_profile);
1774
1775 cmd->pm_profile = (u8)profile;
1776 cmd->pe_vf_enabled = pe_vf_enabled_count;
1777
1778 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1779
1780 return status;
1781}
1782
1783/**
1784 * i40e_aq_request_resource
1785 * @hw: pointer to the hw struct
1786 * @resource: resource id
1787 * @access: access type
1788 * @sdp_number: resource number
1789 * @timeout: the maximum time in ms that the driver may hold the resource
1790 * @cmd_details: pointer to command details structure or NULL
1791 *
1792 * requests common resource using the admin queue commands
1793 **/
1794i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
1795 enum i40e_aq_resources_ids resource,
1796 enum i40e_aq_resource_access_type access,
1797 u8 sdp_number, u64 *timeout,
1798 struct i40e_asq_cmd_details *cmd_details)
1799{
1800 struct i40e_aq_desc desc;
1801 struct i40e_aqc_request_resource *cmd_resp =
1802 (struct i40e_aqc_request_resource *)&desc.params.raw;
1803 i40e_status status;
1804
1805 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
1806
1807 cmd_resp->resource_id = cpu_to_le16(resource);
1808 cmd_resp->access_type = cpu_to_le16(access);
1809 cmd_resp->resource_number = cpu_to_le32(sdp_number);
1810
1811 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1812 /* The completion specifies the maximum time in ms that the driver
1813 * may hold the resource in the Timeout field.
1814 * If the resource is held by someone else, the command completes with
1815 * busy return value and the timeout field indicates the maximum time
1816 * the current owner of the resource has to free it.
1817 */
1818 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
1819 *timeout = le32_to_cpu(cmd_resp->timeout);
1820
1821 return status;
1822}
1823
1824/**
1825 * i40e_aq_release_resource
1826 * @hw: pointer to the hw struct
1827 * @resource: resource id
1828 * @sdp_number: resource number
1829 * @cmd_details: pointer to command details structure or NULL
1830 *
1831 * release common resource using the admin queue commands
1832 **/
1833i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
1834 enum i40e_aq_resources_ids resource,
1835 u8 sdp_number,
1836 struct i40e_asq_cmd_details *cmd_details)
1837{
1838 struct i40e_aq_desc desc;
1839 struct i40e_aqc_request_resource *cmd =
1840 (struct i40e_aqc_request_resource *)&desc.params.raw;
1841 i40e_status status;
1842
1843 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
1844
1845 cmd->resource_id = cpu_to_le16(resource);
1846 cmd->resource_number = cpu_to_le32(sdp_number);
1847
1848 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1849
1850 return status;
1851}
1852
1853/**
1854 * i40e_aq_read_nvm
1855 * @hw: pointer to the hw struct
1856 * @module_pointer: module pointer location in words from the NVM beginning
1857 * @offset: byte offset from the module beginning
1858 * @length: length of the section to be read (in bytes from the offset)
1859 * @data: command buffer (size [bytes] = length)
1860 * @last_command: tells if this is the last command in a series
1861 * @cmd_details: pointer to command details structure or NULL
1862 *
1863 * Read the NVM using the admin queue commands
1864 **/
1865i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
1866 u32 offset, u16 length, void *data,
1867 bool last_command,
1868 struct i40e_asq_cmd_details *cmd_details)
1869{
1870 struct i40e_aq_desc desc;
1871 struct i40e_aqc_nvm_update *cmd =
1872 (struct i40e_aqc_nvm_update *)&desc.params.raw;
1873 i40e_status status;
1874
1875 /* In offset the highest byte must be zeroed. */
1876 if (offset & 0xFF000000) {
1877 status = I40E_ERR_PARAM;
1878 goto i40e_aq_read_nvm_exit;
1879 }
1880
1881 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
1882
1883 /* If this is the last command in a series, set the proper flag. */
1884 if (last_command)
1885 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
1886 cmd->module_pointer = module_pointer;
1887 cmd->offset = cpu_to_le32(offset);
1888 cmd->length = cpu_to_le16(length);
1889
1890 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1891 if (length > I40E_AQ_LARGE_BUF)
1892 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1893
1894 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
1895
1896i40e_aq_read_nvm_exit:
1897 return status;
1898}
1899
1900#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
1901#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
1902#define I40E_DEV_FUNC_CAP_NPAR 0x03
1903#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
1904#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
1905#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
1906#define I40E_DEV_FUNC_CAP_VF 0x13
1907#define I40E_DEV_FUNC_CAP_VMDQ 0x14
1908#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
1909#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
1910#define I40E_DEV_FUNC_CAP_VSI 0x17
1911#define I40E_DEV_FUNC_CAP_DCB 0x18
1912#define I40E_DEV_FUNC_CAP_FCOE 0x21
1913#define I40E_DEV_FUNC_CAP_RSS 0x40
1914#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
1915#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
1916#define I40E_DEV_FUNC_CAP_MSIX 0x43
1917#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
1918#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
1919#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
1920#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
1921#define I40E_DEV_FUNC_CAP_CEM 0xF2
1922#define I40E_DEV_FUNC_CAP_IWARP 0x51
1923#define I40E_DEV_FUNC_CAP_LED 0x61
1924#define I40E_DEV_FUNC_CAP_SDP 0x62
1925#define I40E_DEV_FUNC_CAP_MDIO 0x63
1926
1927/**
1928 * i40e_parse_discover_capabilities
1929 * @hw: pointer to the hw struct
1930 * @buff: pointer to a buffer containing device/function capability records
1931 * @cap_count: number of capability records in the list
1932 * @list_type_opc: type of capabilities list to parse
1933 *
1934 * Parse the device/function capabilities list.
1935 **/
1936static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
1937 u32 cap_count,
1938 enum i40e_admin_queue_opc list_type_opc)
1939{
1940 struct i40e_aqc_list_capabilities_element_resp *cap;
1941 u32 number, logical_id, phys_id;
1942 struct i40e_hw_capabilities *p;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1943 u32 i = 0;
1944 u16 id;
1945
1946 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
1947
1948 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
Joe Perchesb58f2f72014-03-25 04:30:32 +0000[diff] [blame]1949 p = &hw->dev_caps;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1950 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
Joe Perchesb58f2f72014-03-25 04:30:32 +0000[diff] [blame]1951 p = &hw->func_caps;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]1952 else
1953 return;
1954
1955 for (i = 0; i < cap_count; i++, cap++) {
1956 id = le16_to_cpu(cap->id);
1957 number = le32_to_cpu(cap->number);
1958 logical_id = le32_to_cpu(cap->logical_id);
1959 phys_id = le32_to_cpu(cap->phys_id);
1960
1961 switch (id) {
1962 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
1963 p->switch_mode = number;
1964 break;
1965 case I40E_DEV_FUNC_CAP_MGMT_MODE:
1966 p->management_mode = number;
1967 break;
1968 case I40E_DEV_FUNC_CAP_NPAR:
1969 p->npar_enable = number;
1970 break;
1971 case I40E_DEV_FUNC_CAP_OS2BMC:
1972 p->os2bmc = number;
1973 break;
1974 case I40E_DEV_FUNC_CAP_VALID_FUNC:
1975 p->valid_functions = number;
1976 break;
1977 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
1978 if (number == 1)
1979 p->sr_iov_1_1 = true;
1980 break;
1981 case I40E_DEV_FUNC_CAP_VF:
1982 p->num_vfs = number;
1983 p->vf_base_id = logical_id;
1984 break;
1985 case I40E_DEV_FUNC_CAP_VMDQ:
1986 if (number == 1)
1987 p->vmdq = true;
1988 break;
1989 case I40E_DEV_FUNC_CAP_802_1_QBG:
1990 if (number == 1)
1991 p->evb_802_1_qbg = true;
1992 break;
1993 case I40E_DEV_FUNC_CAP_802_1_QBH:
1994 if (number == 1)
1995 p->evb_802_1_qbh = true;
1996 break;
1997 case I40E_DEV_FUNC_CAP_VSI:
1998 p->num_vsis = number;
1999 break;
2000 case I40E_DEV_FUNC_CAP_DCB:
2001 if (number == 1) {
2002 p->dcb = true;
2003 p->enabled_tcmap = logical_id;
2004 p->maxtc = phys_id;
2005 }
2006 break;
2007 case I40E_DEV_FUNC_CAP_FCOE:
2008 if (number == 1)
2009 p->fcoe = true;
2010 break;
2011 case I40E_DEV_FUNC_CAP_RSS:
2012 p->rss = true;
Carolyn Wybornye157ea32014-06-03 23:50:22 +0000[diff] [blame]2013 p->rss_table_size = number;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2014 p->rss_table_entry_width = logical_id;
2015 break;
2016 case I40E_DEV_FUNC_CAP_RX_QUEUES:
2017 p->num_rx_qp = number;
2018 p->base_queue = phys_id;
2019 break;
2020 case I40E_DEV_FUNC_CAP_TX_QUEUES:
2021 p->num_tx_qp = number;
2022 p->base_queue = phys_id;
2023 break;
2024 case I40E_DEV_FUNC_CAP_MSIX:
2025 p->num_msix_vectors = number;
2026 break;
2027 case I40E_DEV_FUNC_CAP_MSIX_VF:
2028 p->num_msix_vectors_vf = number;
2029 break;
2030 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
2031 if (number == 1)
2032 p->mfp_mode_1 = true;
2033 break;
2034 case I40E_DEV_FUNC_CAP_CEM:
2035 if (number == 1)
2036 p->mgmt_cem = true;
2037 break;
2038 case I40E_DEV_FUNC_CAP_IWARP:
2039 if (number == 1)
2040 p->iwarp = true;
2041 break;
2042 case I40E_DEV_FUNC_CAP_LED:
2043 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2044 p->led[phys_id] = true;
2045 break;
2046 case I40E_DEV_FUNC_CAP_SDP:
2047 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2048 p->sdp[phys_id] = true;
2049 break;
2050 case I40E_DEV_FUNC_CAP_MDIO:
2051 if (number == 1) {
2052 p->mdio_port_num = phys_id;
2053 p->mdio_port_mode = logical_id;
2054 }
2055 break;
2056 case I40E_DEV_FUNC_CAP_IEEE_1588:
2057 if (number == 1)
2058 p->ieee_1588 = true;
2059 break;
2060 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
2061 p->fd = true;
2062 p->fd_filters_guaranteed = number;
2063 p->fd_filters_best_effort = logical_id;
2064 break;
2065 default:
2066 break;
2067 }
2068 }
2069
Vasu Dev566bb852014-04-09 05:59:06 +0000[diff] [blame]2070 /* Software override ensuring FCoE is disabled if npar or mfp
2071 * mode because it is not supported in these modes.
2072 */
2073 if (p->npar_enable || p->mfp_mode_1)
2074 p->fcoe = false;
2075
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2076 /* additional HW specific goodies that might
2077 * someday be HW version specific
2078 */
2079 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
2080}
2081
2082/**
2083 * i40e_aq_discover_capabilities
2084 * @hw: pointer to the hw struct
2085 * @buff: a virtual buffer to hold the capabilities
2086 * @buff_size: Size of the virtual buffer
2087 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
2088 * @list_type_opc: capabilities type to discover - pass in the command opcode
2089 * @cmd_details: pointer to command details structure or NULL
2090 *
2091 * Get the device capabilities descriptions from the firmware
2092 **/
2093i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
2094 void *buff, u16 buff_size, u16 *data_size,
2095 enum i40e_admin_queue_opc list_type_opc,
2096 struct i40e_asq_cmd_details *cmd_details)
2097{
2098 struct i40e_aqc_list_capabilites *cmd;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2099 struct i40e_aq_desc desc;
Jesse Brandeburg8fb905b2014-01-17 15:36:33 -0800[diff] [blame]2100 i40e_status status = 0;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2101
2102 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
2103
2104 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
2105 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
2106 status = I40E_ERR_PARAM;
2107 goto exit;
2108 }
2109
2110 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
2111
2112 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2113 if (buff_size > I40E_AQ_LARGE_BUF)
2114 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2115
2116 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2117 *data_size = le16_to_cpu(desc.datalen);
2118
2119 if (status)
2120 goto exit;
2121
2122 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
2123 list_type_opc);
2124
2125exit:
2126 return status;
2127}
2128
2129/**
2130 * i40e_aq_get_lldp_mib
2131 * @hw: pointer to the hw struct
2132 * @bridge_type: type of bridge requested
2133 * @mib_type: Local, Remote or both Local and Remote MIBs
2134 * @buff: pointer to a user supplied buffer to store the MIB block
2135 * @buff_size: size of the buffer (in bytes)
2136 * @local_len : length of the returned Local LLDP MIB
2137 * @remote_len: length of the returned Remote LLDP MIB
2138 * @cmd_details: pointer to command details structure or NULL
2139 *
2140 * Requests the complete LLDP MIB (entire packet).
2141 **/
2142i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
2143 u8 mib_type, void *buff, u16 buff_size,
2144 u16 *local_len, u16 *remote_len,
2145 struct i40e_asq_cmd_details *cmd_details)
2146{
2147 struct i40e_aq_desc desc;
2148 struct i40e_aqc_lldp_get_mib *cmd =
2149 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2150 struct i40e_aqc_lldp_get_mib *resp =
2151 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
2152 i40e_status status;
2153
2154 if (buff_size == 0 || !buff)
2155 return I40E_ERR_PARAM;
2156
2157 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
2158 /* Indirect Command */
2159 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2160
2161 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
2162 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
2163 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
2164
2165 desc.datalen = cpu_to_le16(buff_size);
2166
2167 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2168 if (buff_size > I40E_AQ_LARGE_BUF)
2169 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2170
2171 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2172 if (!status) {
2173 if (local_len != NULL)
2174 *local_len = le16_to_cpu(resp->local_len);
2175 if (remote_len != NULL)
2176 *remote_len = le16_to_cpu(resp->remote_len);
2177 }
2178
2179 return status;
2180}
2181
2182/**
2183 * i40e_aq_cfg_lldp_mib_change_event
2184 * @hw: pointer to the hw struct
2185 * @enable_update: Enable or Disable event posting
2186 * @cmd_details: pointer to command details structure or NULL
2187 *
2188 * Enable or Disable posting of an event on ARQ when LLDP MIB
2189 * associated with the interface changes
2190 **/
2191i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2192 bool enable_update,
2193 struct i40e_asq_cmd_details *cmd_details)
2194{
2195 struct i40e_aq_desc desc;
2196 struct i40e_aqc_lldp_update_mib *cmd =
2197 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2198 i40e_status status;
2199
2200 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2201
2202 if (!enable_update)
2203 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2204
2205 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2206
2207 return status;
2208}
2209
2210/**
2211 * i40e_aq_stop_lldp
2212 * @hw: pointer to the hw struct
2213 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2214 * @cmd_details: pointer to command details structure or NULL
2215 *
2216 * Stop or Shutdown the embedded LLDP Agent
2217 **/
2218i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2219 struct i40e_asq_cmd_details *cmd_details)
2220{
2221 struct i40e_aq_desc desc;
2222 struct i40e_aqc_lldp_stop *cmd =
2223 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2224 i40e_status status;
2225
2226 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2227
2228 if (shutdown_agent)
2229 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2230
2231 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2232
2233 return status;
2234}
2235
2236/**
2237 * i40e_aq_start_lldp
2238 * @hw: pointer to the hw struct
2239 * @cmd_details: pointer to command details structure or NULL
2240 *
2241 * Start the embedded LLDP Agent on all ports.
2242 **/
2243i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2244 struct i40e_asq_cmd_details *cmd_details)
2245{
2246 struct i40e_aq_desc desc;
2247 struct i40e_aqc_lldp_start *cmd =
2248 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2249 i40e_status status;
2250
2251 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2252
2253 cmd->command = I40E_AQ_LLDP_AGENT_START;
2254
2255 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2256
2257 return status;
2258}
2259
2260/**
Jeff Kirshera1c9a9d2013-12-28 07:32:18 +0000[diff] [blame]2261 * i40e_aq_add_udp_tunnel
2262 * @hw: pointer to the hw struct
2263 * @udp_port: the UDP port to add
2264 * @header_len: length of the tunneling header length in DWords
2265 * @protocol_index: protocol index type
Jeff Kirsher98d44382013-12-21 05:44:42 +0000[diff] [blame]2266 * @filter_index: pointer to filter index
Jeff Kirshera1c9a9d2013-12-28 07:32:18 +0000[diff] [blame]2267 * @cmd_details: pointer to command details structure or NULL
2268 **/
2269i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
Kevin Scottf4f94b92014-04-05 07:46:10 +0000[diff] [blame]2270 u16 udp_port, u8 protocol_index,
2271 u8 *filter_index,
Jeff Kirshera1c9a9d2013-12-28 07:32:18 +0000[diff] [blame]2272 struct i40e_asq_cmd_details *cmd_details)
2273{
2274 struct i40e_aq_desc desc;
2275 struct i40e_aqc_add_udp_tunnel *cmd =
2276 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2277 struct i40e_aqc_del_udp_tunnel_completion *resp =
2278 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2279 i40e_status status;
2280
2281 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2282
2283 cmd->udp_port = cpu_to_le16(udp_port);
Shannon Nelson981b7542013-12-11 08:17:11 +0000[diff] [blame]2284 cmd->protocol_type = protocol_index;
Jeff Kirshera1c9a9d2013-12-28 07:32:18 +0000[diff] [blame]2285
2286 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2287
2288 if (!status)
2289 *filter_index = resp->index;
2290
2291 return status;
2292}
2293
2294/**
2295 * i40e_aq_del_udp_tunnel
2296 * @hw: pointer to the hw struct
2297 * @index: filter index
2298 * @cmd_details: pointer to command details structure or NULL
2299 **/
2300i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2301 struct i40e_asq_cmd_details *cmd_details)
2302{
2303 struct i40e_aq_desc desc;
2304 struct i40e_aqc_remove_udp_tunnel *cmd =
2305 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2306 i40e_status status;
2307
2308 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2309
2310 cmd->index = index;
2311
2312 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2313
2314 return status;
2315}
2316
2317/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2318 * i40e_aq_delete_element - Delete switch element
2319 * @hw: pointer to the hw struct
2320 * @seid: the SEID to delete from the switch
2321 * @cmd_details: pointer to command details structure or NULL
2322 *
2323 * This deletes a switch element from the switch.
2324 **/
2325i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2326 struct i40e_asq_cmd_details *cmd_details)
2327{
2328 struct i40e_aq_desc desc;
2329 struct i40e_aqc_switch_seid *cmd =
2330 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2331 i40e_status status;
2332
2333 if (seid == 0)
2334 return I40E_ERR_PARAM;
2335
2336 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2337
2338 cmd->seid = cpu_to_le16(seid);
2339
2340 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2341
2342 return status;
2343}
2344
2345/**
Neerav Parikhafb3ff02014-01-17 15:36:36 -0800[diff] [blame]2346 * i40e_aq_dcb_updated - DCB Updated Command
2347 * @hw: pointer to the hw struct
2348 * @cmd_details: pointer to command details structure or NULL
2349 *
2350 * EMP will return when the shared RPB settings have been
2351 * recomputed and modified. The retval field in the descriptor
2352 * will be set to 0 when RPB is modified.
2353 **/
2354i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2355 struct i40e_asq_cmd_details *cmd_details)
2356{
2357 struct i40e_aq_desc desc;
2358 i40e_status status;
2359
2360 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2361
2362 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2363
2364 return status;
2365}
2366
2367/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2368 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2369 * @hw: pointer to the hw struct
2370 * @seid: seid for the physical port/switching component/vsi
2371 * @buff: Indirect buffer to hold data parameters and response
2372 * @buff_size: Indirect buffer size
2373 * @opcode: Tx scheduler AQ command opcode
2374 * @cmd_details: pointer to command details structure or NULL
2375 *
2376 * Generic command handler for Tx scheduler AQ commands
2377 **/
2378static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2379 void *buff, u16 buff_size,
2380 enum i40e_admin_queue_opc opcode,
2381 struct i40e_asq_cmd_details *cmd_details)
2382{
2383 struct i40e_aq_desc desc;
2384 struct i40e_aqc_tx_sched_ind *cmd =
2385 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2386 i40e_status status;
2387 bool cmd_param_flag = false;
2388
2389 switch (opcode) {
2390 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2391 case i40e_aqc_opc_configure_vsi_tc_bw:
2392 case i40e_aqc_opc_enable_switching_comp_ets:
2393 case i40e_aqc_opc_modify_switching_comp_ets:
2394 case i40e_aqc_opc_disable_switching_comp_ets:
2395 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2396 case i40e_aqc_opc_configure_switching_comp_bw_config:
2397 cmd_param_flag = true;
2398 break;
2399 case i40e_aqc_opc_query_vsi_bw_config:
2400 case i40e_aqc_opc_query_vsi_ets_sla_config:
2401 case i40e_aqc_opc_query_switching_comp_ets_config:
2402 case i40e_aqc_opc_query_port_ets_config:
2403 case i40e_aqc_opc_query_switching_comp_bw_config:
2404 cmd_param_flag = false;
2405 break;
2406 default:
2407 return I40E_ERR_PARAM;
2408 }
2409
2410 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2411
2412 /* Indirect command */
2413 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2414 if (cmd_param_flag)
2415 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2416 if (buff_size > I40E_AQ_LARGE_BUF)
2417 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2418
2419 desc.datalen = cpu_to_le16(buff_size);
2420
2421 cmd->vsi_seid = cpu_to_le16(seid);
2422
2423 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2424
2425 return status;
2426}
2427
2428/**
Mitch Williams6b192892014-03-06 09:02:29 +0000[diff] [blame]2429 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
2430 * @hw: pointer to the hw struct
2431 * @seid: VSI seid
2432 * @credit: BW limit credits (0 = disabled)
2433 * @max_credit: Max BW limit credits
2434 * @cmd_details: pointer to command details structure or NULL
2435 **/
2436i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
2437 u16 seid, u16 credit, u8 max_credit,
2438 struct i40e_asq_cmd_details *cmd_details)
2439{
2440 struct i40e_aq_desc desc;
2441 struct i40e_aqc_configure_vsi_bw_limit *cmd =
2442 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
2443 i40e_status status;
2444
2445 i40e_fill_default_direct_cmd_desc(&desc,
2446 i40e_aqc_opc_configure_vsi_bw_limit);
2447
2448 cmd->vsi_seid = cpu_to_le16(seid);
2449 cmd->credit = cpu_to_le16(credit);
2450 cmd->max_credit = max_credit;
2451
2452 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2453
2454 return status;
2455}
2456
2457/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2458 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2459 * @hw: pointer to the hw struct
2460 * @seid: VSI seid
2461 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2462 * @cmd_details: pointer to command details structure or NULL
2463 **/
2464i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
2465 u16 seid,
2466 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
2467 struct i40e_asq_cmd_details *cmd_details)
2468{
2469 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2470 i40e_aqc_opc_configure_vsi_tc_bw,
2471 cmd_details);
2472}
2473
2474/**
Neerav Parikhafb3ff02014-01-17 15:36:36 -0800[diff] [blame]2475 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
2476 * @hw: pointer to the hw struct
2477 * @seid: seid of the switching component connected to Physical Port
2478 * @ets_data: Buffer holding ETS parameters
2479 * @cmd_details: pointer to command details structure or NULL
2480 **/
2481i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
2482 u16 seid,
2483 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
2484 enum i40e_admin_queue_opc opcode,
2485 struct i40e_asq_cmd_details *cmd_details)
2486{
2487 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
2488 sizeof(*ets_data), opcode, cmd_details);
2489}
2490
2491/**
2492 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
2493 * @hw: pointer to the hw struct
2494 * @seid: seid of the switching component
2495 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
2496 * @cmd_details: pointer to command details structure or NULL
2497 **/
2498i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
2499 u16 seid,
2500 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
2501 struct i40e_asq_cmd_details *cmd_details)
2502{
2503 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2504 i40e_aqc_opc_configure_switching_comp_bw_config,
2505 cmd_details);
2506}
2507
2508/**
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2509 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
2510 * @hw: pointer to the hw struct
2511 * @seid: seid of the VSI
2512 * @bw_data: Buffer to hold VSI BW configuration
2513 * @cmd_details: pointer to command details structure or NULL
2514 **/
2515i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
2516 u16 seid,
2517 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
2518 struct i40e_asq_cmd_details *cmd_details)
2519{
2520 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2521 i40e_aqc_opc_query_vsi_bw_config,
2522 cmd_details);
2523}
2524
2525/**
2526 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
2527 * @hw: pointer to the hw struct
2528 * @seid: seid of the VSI
2529 * @bw_data: Buffer to hold VSI BW configuration per TC
2530 * @cmd_details: pointer to command details structure or NULL
2531 **/
2532i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
2533 u16 seid,
2534 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
2535 struct i40e_asq_cmd_details *cmd_details)
2536{
2537 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2538 i40e_aqc_opc_query_vsi_ets_sla_config,
2539 cmd_details);
2540}
2541
2542/**
2543 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
2544 * @hw: pointer to the hw struct
2545 * @seid: seid of the switching component
2546 * @bw_data: Buffer to hold switching component's per TC BW config
2547 * @cmd_details: pointer to command details structure or NULL
2548 **/
2549i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
2550 u16 seid,
2551 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
2552 struct i40e_asq_cmd_details *cmd_details)
2553{
2554 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2555 i40e_aqc_opc_query_switching_comp_ets_config,
2556 cmd_details);
2557}
2558
2559/**
2560 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
2561 * @hw: pointer to the hw struct
2562 * @seid: seid of the VSI or switching component connected to Physical Port
2563 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
2564 * @cmd_details: pointer to command details structure or NULL
2565 **/
2566i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
2567 u16 seid,
2568 struct i40e_aqc_query_port_ets_config_resp *bw_data,
2569 struct i40e_asq_cmd_details *cmd_details)
2570{
2571 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2572 i40e_aqc_opc_query_port_ets_config,
2573 cmd_details);
2574}
2575
2576/**
2577 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
2578 * @hw: pointer to the hw struct
2579 * @seid: seid of the switching component
2580 * @bw_data: Buffer to hold switching component's BW configuration
2581 * @cmd_details: pointer to command details structure or NULL
2582 **/
2583i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
2584 u16 seid,
2585 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
2586 struct i40e_asq_cmd_details *cmd_details)
2587{
2588 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2589 i40e_aqc_opc_query_switching_comp_bw_config,
2590 cmd_details);
2591}
2592
2593/**
2594 * i40e_validate_filter_settings
2595 * @hw: pointer to the hardware structure
2596 * @settings: Filter control settings
2597 *
2598 * Check and validate the filter control settings passed.
2599 * The function checks for the valid filter/context sizes being
2600 * passed for FCoE and PE.
2601 *
2602 * Returns 0 if the values passed are valid and within
2603 * range else returns an error.
2604 **/
2605static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
2606 struct i40e_filter_control_settings *settings)
2607{
2608 u32 fcoe_cntx_size, fcoe_filt_size;
2609 u32 pe_cntx_size, pe_filt_size;
Anjali Singhai Jain467d7292014-05-10 04:49:02 +0000[diff] [blame]2610 u32 fcoe_fmax;
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2611 u32 val;
2612
2613 /* Validate FCoE settings passed */
2614 switch (settings->fcoe_filt_num) {
2615 case I40E_HASH_FILTER_SIZE_1K:
2616 case I40E_HASH_FILTER_SIZE_2K:
2617 case I40E_HASH_FILTER_SIZE_4K:
2618 case I40E_HASH_FILTER_SIZE_8K:
2619 case I40E_HASH_FILTER_SIZE_16K:
2620 case I40E_HASH_FILTER_SIZE_32K:
2621 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2622 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
2623 break;
2624 default:
2625 return I40E_ERR_PARAM;
2626 }
2627
2628 switch (settings->fcoe_cntx_num) {
2629 case I40E_DMA_CNTX_SIZE_512:
2630 case I40E_DMA_CNTX_SIZE_1K:
2631 case I40E_DMA_CNTX_SIZE_2K:
2632 case I40E_DMA_CNTX_SIZE_4K:
2633 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2634 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
2635 break;
2636 default:
2637 return I40E_ERR_PARAM;
2638 }
2639
2640 /* Validate PE settings passed */
2641 switch (settings->pe_filt_num) {
2642 case I40E_HASH_FILTER_SIZE_1K:
2643 case I40E_HASH_FILTER_SIZE_2K:
2644 case I40E_HASH_FILTER_SIZE_4K:
2645 case I40E_HASH_FILTER_SIZE_8K:
2646 case I40E_HASH_FILTER_SIZE_16K:
2647 case I40E_HASH_FILTER_SIZE_32K:
2648 case I40E_HASH_FILTER_SIZE_64K:
2649 case I40E_HASH_FILTER_SIZE_128K:
2650 case I40E_HASH_FILTER_SIZE_256K:
2651 case I40E_HASH_FILTER_SIZE_512K:
2652 case I40E_HASH_FILTER_SIZE_1M:
2653 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2654 pe_filt_size <<= (u32)settings->pe_filt_num;
2655 break;
2656 default:
2657 return I40E_ERR_PARAM;
2658 }
2659
2660 switch (settings->pe_cntx_num) {
2661 case I40E_DMA_CNTX_SIZE_512:
2662 case I40E_DMA_CNTX_SIZE_1K:
2663 case I40E_DMA_CNTX_SIZE_2K:
2664 case I40E_DMA_CNTX_SIZE_4K:
2665 case I40E_DMA_CNTX_SIZE_8K:
2666 case I40E_DMA_CNTX_SIZE_16K:
2667 case I40E_DMA_CNTX_SIZE_32K:
2668 case I40E_DMA_CNTX_SIZE_64K:
2669 case I40E_DMA_CNTX_SIZE_128K:
2670 case I40E_DMA_CNTX_SIZE_256K:
2671 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2672 pe_cntx_size <<= (u32)settings->pe_cntx_num;
2673 break;
2674 default:
2675 return I40E_ERR_PARAM;
2676 }
2677
2678 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
2679 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
2680 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
2681 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
2682 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
2683 return I40E_ERR_INVALID_SIZE;
2684
Jesse Brandeburg56a62fc2013-09-11 08:40:12 +0000[diff] [blame]2685 return 0;
2686}
2687
2688/**
2689 * i40e_set_filter_control
2690 * @hw: pointer to the hardware structure
2691 * @settings: Filter control settings
2692 *
2693 * Set the Queue Filters for PE/FCoE and enable filters required
2694 * for a single PF. It is expected that these settings are programmed
2695 * at the driver initialization time.
2696 **/
2697i40e_status i40e_set_filter_control(struct i40e_hw *hw,
2698 struct i40e_filter_control_settings *settings)
2699{
2700 i40e_status ret = 0;
2701 u32 hash_lut_size = 0;
2702 u32 val;
2703
2704 if (!settings)
2705 return I40E_ERR_PARAM;
2706
2707 /* Validate the input settings */
2708 ret = i40e_validate_filter_settings(hw, settings);
2709 if (ret)
2710 return ret;
2711
2712 /* Read the PF Queue Filter control register */
2713 val = rd32(hw, I40E_PFQF_CTL_0);
2714
2715 /* Program required PE hash buckets for the PF */
2716 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
2717 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
2718 I40E_PFQF_CTL_0_PEHSIZE_MASK;
2719 /* Program required PE contexts for the PF */
2720 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
2721 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
2722 I40E_PFQF_CTL_0_PEDSIZE_MASK;
2723
2724 /* Program required FCoE hash buckets for the PF */
2725 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2726 val |= ((u32)settings->fcoe_filt_num <<
2727 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
2728 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2729 /* Program required FCoE DDP contexts for the PF */
2730 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2731 val |= ((u32)settings->fcoe_cntx_num <<
2732 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
2733 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2734
2735 /* Program Hash LUT size for the PF */
2736 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2737 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
2738 hash_lut_size = 1;
2739 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
2740 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2741
2742 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2743 if (settings->enable_fdir)
2744 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
2745 if (settings->enable_ethtype)
2746 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
2747 if (settings->enable_macvlan)
2748 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
2749
2750 wr32(hw, I40E_PFQF_CTL_0, val);
2751
2752 return 0;
2753}
Neerav Parikhafb3ff02014-01-17 15:36:36 -0800[diff] [blame]2754
2755/**
2756 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
2757 * @hw: pointer to the hw struct
2758 * @mac_addr: MAC address to use in the filter
2759 * @ethtype: Ethertype to use in the filter
2760 * @flags: Flags that needs to be applied to the filter
2761 * @vsi_seid: seid of the control VSI
2762 * @queue: VSI queue number to send the packet to
2763 * @is_add: Add control packet filter if True else remove
2764 * @stats: Structure to hold information on control filter counts
2765 * @cmd_details: pointer to command details structure or NULL
2766 *
2767 * This command will Add or Remove control packet filter for a control VSI.
2768 * In return it will update the total number of perfect filter count in
2769 * the stats member.
2770 **/
2771i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
2772 u8 *mac_addr, u16 ethtype, u16 flags,
2773 u16 vsi_seid, u16 queue, bool is_add,
2774 struct i40e_control_filter_stats *stats,
2775 struct i40e_asq_cmd_details *cmd_details)
2776{
2777 struct i40e_aq_desc desc;
2778 struct i40e_aqc_add_remove_control_packet_filter *cmd =
2779 (struct i40e_aqc_add_remove_control_packet_filter *)
2780 &desc.params.raw;
2781 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
2782 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
2783 &desc.params.raw;
2784 i40e_status status;
2785
2786 if (vsi_seid == 0)
2787 return I40E_ERR_PARAM;
2788
2789 if (is_add) {
2790 i40e_fill_default_direct_cmd_desc(&desc,
2791 i40e_aqc_opc_add_control_packet_filter);
2792 cmd->queue = cpu_to_le16(queue);
2793 } else {
2794 i40e_fill_default_direct_cmd_desc(&desc,
2795 i40e_aqc_opc_remove_control_packet_filter);
2796 }
2797
2798 if (mac_addr)
2799 memcpy(cmd->mac, mac_addr, ETH_ALEN);
2800
2801 cmd->etype = cpu_to_le16(ethtype);
2802 cmd->flags = cpu_to_le16(flags);
2803 cmd->seid = cpu_to_le16(vsi_seid);
2804
2805 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2806
2807 if (!status && stats) {
2808 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
2809 stats->etype_used = le16_to_cpu(resp->etype_used);
2810 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
2811 stats->etype_free = le16_to_cpu(resp->etype_free);
2812 }
2813
2814 return status;
2815}
2816
Catherine Sullivand4dfb812013-11-28 06:39:21 +0000[diff] [blame]2817/**
2818 * i40e_set_pci_config_data - store PCI bus info
2819 * @hw: pointer to hardware structure
2820 * @link_status: the link status word from PCI config space
2821 *
2822 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
2823 **/
2824void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
2825{
2826 hw->bus.type = i40e_bus_type_pci_express;
2827
2828 switch (link_status & PCI_EXP_LNKSTA_NLW) {
2829 case PCI_EXP_LNKSTA_NLW_X1:
2830 hw->bus.width = i40e_bus_width_pcie_x1;
2831 break;
2832 case PCI_EXP_LNKSTA_NLW_X2:
2833 hw->bus.width = i40e_bus_width_pcie_x2;
2834 break;
2835 case PCI_EXP_LNKSTA_NLW_X4:
2836 hw->bus.width = i40e_bus_width_pcie_x4;
2837 break;
2838 case PCI_EXP_LNKSTA_NLW_X8:
2839 hw->bus.width = i40e_bus_width_pcie_x8;
2840 break;
2841 default:
2842 hw->bus.width = i40e_bus_width_unknown;
2843 break;
2844 }
2845
2846 switch (link_status & PCI_EXP_LNKSTA_CLS) {
2847 case PCI_EXP_LNKSTA_CLS_2_5GB:
2848 hw->bus.speed = i40e_bus_speed_2500;
2849 break;
2850 case PCI_EXP_LNKSTA_CLS_5_0GB:
2851 hw->bus.speed = i40e_bus_speed_5000;
2852 break;
2853 case PCI_EXP_LNKSTA_CLS_8_0GB:
2854 hw->bus.speed = i40e_bus_speed_8000;
2855 break;
2856 default:
2857 hw->bus.speed = i40e_bus_speed_unknown;
2858 break;
2859 }
2860}