Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | /dts-v1/; |
| 9 | |
| 10 | #include "am33xx.dtsi" |
| 11 | |
| 12 | / { |
| 13 | model = "Toby Churchill SL50 Series"; |
| 14 | compatible = "tcl,am335x-sl50", "ti,am33xx"; |
| 15 | |
| 16 | cpus { |
| 17 | cpu@0 { |
| 18 | cpu0-supply = <&dcdc2_reg>; |
| 19 | }; |
| 20 | }; |
| 21 | |
| 22 | leds { |
| 23 | compatible = "gpio-leds"; |
| 24 | pinctrl-names = "default"; |
| 25 | pinctrl-0 = <&led_pins>; |
| 26 | |
| 27 | led@0 { |
| 28 | label = "sl50:green:usr0"; |
| 29 | gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; |
| 30 | default-state = "off"; |
| 31 | }; |
| 32 | |
| 33 | led@1 { |
| 34 | label = "sl50:red:usr1"; |
| 35 | gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; |
| 36 | default-state = "off"; |
| 37 | }; |
| 38 | |
| 39 | led@2 { |
| 40 | label = "sl50:green:usr2"; |
| 41 | gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; |
| 42 | default-state = "off"; |
| 43 | }; |
| 44 | |
| 45 | led@3 { |
| 46 | label = "sl50:red:usr3"; |
| 47 | gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; |
| 48 | default-state = "off"; |
| 49 | }; |
| 50 | }; |
| 51 | |
| 52 | backlight0: disp0 { |
| 53 | compatible = "pwm-backlight"; |
| 54 | pwms = <&ehrpwm1 0 500000 0>; |
| 55 | brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; |
| 56 | default-brightness-level = <6>; |
| 57 | }; |
| 58 | |
| 59 | backlight1: disp1 { |
| 60 | compatible = "pwm-backlight"; |
| 61 | pwms = <&ehrpwm1 1 500000 0>; |
| 62 | brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>; |
| 63 | default-brightness-level = <6>; |
| 64 | }; |
| 65 | |
| 66 | sound { |
| 67 | compatible = "ti,da830-evm-audio"; |
| 68 | ti,model = "AM335x-SL50"; |
| 69 | ti,audio-codec = <&audio_codec>; |
| 70 | ti,mcasp-controller = <&mcasp0>; |
| 71 | ti,codec-clock-rate = <12000000>; |
| 72 | ti,audio-routing = |
| 73 | "Headphone Jack", "HPLOUT", |
| 74 | "Headphone Jack", "HPROUT", |
| 75 | "LINE1R", "Line In", |
| 76 | "LINE1L", "Line In"; |
| 77 | }; |
| 78 | |
| 79 | emmc_pwrseq: pwrseq@0 { |
| 80 | compatible = "mmc-pwrseq-emmc"; |
| 81 | pinctrl-names = "default"; |
| 82 | pinctrl-0 = <&emmc_pwrseq_pins>; |
| 83 | reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; |
| 84 | }; |
| 85 | |
| 86 | vmmcsd_fixed: fixedregulator@0 { |
| 87 | compatible = "regulator-fixed"; |
| 88 | regulator-name = "vmmcsd_fixed"; |
| 89 | regulator-min-microvolt = <3300000>; |
| 90 | regulator-max-microvolt = <3300000>; |
| 91 | }; |
| 92 | }; |
| 93 | |
| 94 | &am33xx_pinmux { |
| 95 | pinctrl-names = "default"; |
| 96 | pinctrl-0 = <&lwb_pins>; |
| 97 | |
| 98 | led_pins: pinmux_led_pins { |
| 99 | pinctrl-single,pins = < |
| 100 | AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */ |
| 101 | AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* gpmc_a6.gpio1_22 */ |
| 102 | AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* gpmc_a7.gpio1_23 */ |
| 103 | AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* gpmc_a8.gpio1_24 */ |
| 104 | >; |
| 105 | }; |
| 106 | |
| 107 | uart0_pins: pinmux_uart0_pins { |
| 108 | pinctrl-single,pins = < |
| 109 | AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ |
| 110 | AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ |
| 111 | >; |
| 112 | }; |
| 113 | |
| 114 | uart4_pins: pinmux_uart4_pins { |
| 115 | pinctrl-single,pins = < |
| 116 | AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* gpmc_wait0.uart4_rxd */ |
| 117 | AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpmc_wpn.uart4_txd */ |
| 118 | >; |
| 119 | }; |
| 120 | |
| 121 | i2c0_pins: pinmux_i2c0_pins { |
| 122 | pinctrl-single,pins = < |
| 123 | AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
| 124 | AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
| 125 | >; |
| 126 | }; |
| 127 | |
| 128 | i2c1_pins: pinmux_i2c1_pins { |
| 129 | pinctrl-single,pins = < |
| 130 | AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rxd.i2c1_sda */ |
| 131 | AM33XX_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_txdi2c1_scl */ |
| 132 | >; |
| 133 | }; |
| 134 | |
| 135 | i2c2_pins: pinmux_i2c2_pins { |
| 136 | pinctrl-single,pins = < |
| 137 | AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ |
| 138 | AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ |
| 139 | >; |
| 140 | }; |
| 141 | |
| 142 | cpsw_default: cpsw_default { |
| 143 | pinctrl-single,pins = < |
| 144 | /* Slave 1 */ |
| 145 | AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ |
| 146 | AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ |
| 147 | AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ |
| 148 | AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ |
| 149 | AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ |
| 150 | AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ |
| 151 | AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ |
| 152 | AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ |
| 153 | AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ |
| 154 | AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ |
| 155 | AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ |
| 156 | AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ |
| 157 | AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ |
| 158 | >; |
| 159 | }; |
| 160 | |
| 161 | cpsw_sleep: cpsw_sleep { |
| 162 | pinctrl-single,pins = < |
| 163 | /* Slave 1 reset value */ |
| 164 | AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 165 | AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 166 | AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 167 | AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 168 | AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 169 | AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 170 | AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 171 | AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 172 | AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 173 | AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 174 | AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 175 | AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 176 | AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 177 | >; |
| 178 | }; |
| 179 | |
| 180 | davinci_mdio_default: davinci_mdio_default { |
| 181 | pinctrl-single,pins = < |
| 182 | /* MDIO */ |
| 183 | AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ |
| 184 | AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ |
| 185 | >; |
| 186 | }; |
| 187 | |
| 188 | davinci_mdio_sleep: davinci_mdio_sleep { |
| 189 | pinctrl-single,pins = < |
| 190 | /* MDIO reset value */ |
| 191 | AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 192 | AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 193 | >; |
| 194 | }; |
| 195 | |
| 196 | mmc1_pins: pinmux_mmc1_pins { |
| 197 | pinctrl-single,pins = < |
| 198 | AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ |
| 199 | >; |
| 200 | }; |
| 201 | |
| 202 | emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins { |
| 203 | pinctrl-single,pins = < |
| 204 | AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a4.gpio1_20 */ |
| 205 | >; |
| 206 | }; |
| 207 | |
| 208 | emmc_pins: pinmux_emmc_pins { |
| 209 | pinctrl-single,pins = < |
| 210 | AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ |
| 211 | AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ |
| 212 | AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ |
| 213 | AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ |
| 214 | AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ |
| 215 | AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ |
| 216 | AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ |
| 217 | AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ |
| 218 | AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ |
| 219 | AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ |
| 220 | >; |
| 221 | }; |
| 222 | |
| 223 | audio_pins: pinmux_audio_pins { |
| 224 | pinctrl-single,pins = < |
| 225 | AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ |
| 226 | AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ |
| 227 | AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ |
| 228 | AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ |
| 229 | AM33XX_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ |
| 230 | >; |
| 231 | }; |
| 232 | |
| 233 | ehrpwm1_pins: pinmux_ehrpwm1a_pins { |
| 234 | pinctrl-single,pins = < |
| 235 | AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE6) /* gpmc_a2.ehrpwm1a */ |
| 236 | AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.ehrpwm1b */ |
| 237 | >; |
| 238 | }; |
| 239 | |
| 240 | lwb_pins: pinmux_lwb_pins { |
| 241 | pinctrl-single,pins = < |
| 242 | AM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) /* SoundPA_en - mcasp0_fsr.gpio3_19 */ |
| 243 | AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* nKbdOnC - gpmc_ad10.gpio0_26 */ |
| 244 | AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ |
| 245 | AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ |
| 246 | AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7) /* nDispReset - gpmc_ad14.gpio1_14 */ |
| 247 | AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ |
| 248 | /* AVR Programming - SPI Bus (bit bang) - Screen and Keyboard */ |
| 249 | AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattMOSI spi0_d0.gpio0_3 */ |
| 250 | AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattMISO spi0_d1.gpio0_4 */ |
| 251 | AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattSCLK spi0_clk.gpio0_2 */ |
| 252 | /* PDI Bus - Battery system */ |
| 253 | AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ |
| 254 | AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ |
| 255 | >; |
| 256 | }; |
| 257 | }; |
| 258 | |
| 259 | &i2c0 { |
| 260 | status = "okay"; |
| 261 | pinctrl-names = "default"; |
| 262 | pinctrl-0 = <&i2c0_pins>; |
| 263 | |
| 264 | clock-frequency = <400000>; |
| 265 | |
| 266 | tps: tps@24 { |
| 267 | reg = <0x24>; |
| 268 | }; |
| 269 | |
| 270 | eeprom: eeprom@50 { |
| 271 | compatible = "at,24c256"; |
| 272 | reg = <0x50>; |
| 273 | }; |
| 274 | }; |
| 275 | |
| 276 | &i2c1 { |
| 277 | status = "okay"; |
| 278 | pinctrl-names = "default"; |
| 279 | pinctrl-0 = <&i2c1_pins>; |
| 280 | }; |
| 281 | |
| 282 | &i2c2 { |
| 283 | status = "okay"; |
| 284 | pinctrl-names = "default"; |
| 285 | pinctrl-0 = <&i2c2_pins>; |
| 286 | |
| 287 | clock-frequency = <400000>; |
| 288 | |
| 289 | audio_codec: tlv320aic3106@1b { |
| 290 | status = "okay"; |
| 291 | compatible = "ti,tlv320aic3106"; |
| 292 | reg = <0x1b>; |
| 293 | |
| 294 | AVDD-supply = <&ldo4_reg>; |
| 295 | IOVDD-supply = <&ldo4_reg>; |
| 296 | DRVDD-supply = <&ldo4_reg>; |
| 297 | DVDD-supply = <&ldo3_reg>; |
| 298 | }; |
| 299 | }; |
| 300 | |
| 301 | &usb { |
| 302 | status = "okay"; |
| 303 | }; |
| 304 | |
| 305 | &usb_ctrl_mod { |
| 306 | status = "okay"; |
| 307 | }; |
| 308 | |
| 309 | &usb0_phy { |
| 310 | status = "okay"; |
| 311 | }; |
| 312 | |
| 313 | &usb1_phy { |
| 314 | status = "okay"; |
| 315 | }; |
| 316 | |
| 317 | &usb0 { |
| 318 | status = "okay"; |
| 319 | dr_mode = "peripheral"; |
| 320 | }; |
| 321 | |
| 322 | &usb1 { |
| 323 | status = "okay"; |
| 324 | dr_mode = "host"; |
| 325 | }; |
| 326 | |
| 327 | &cppi41dma { |
| 328 | status = "okay"; |
| 329 | }; |
| 330 | |
| 331 | &mmc1 { |
| 332 | status = "okay"; |
| 333 | pinctrl-names = "default"; |
| 334 | pinctrl-0 = <&mmc1_pins>; |
| 335 | bus-width = <4>; |
| 336 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; |
| 337 | vmmc-supply = <&vmmcsd_fixed>; |
| 338 | }; |
| 339 | |
| 340 | &mmc2 { |
| 341 | status = "okay"; |
| 342 | pinctrl-names = "default"; |
| 343 | pinctrl-0 = <&emmc_pins>; |
| 344 | bus-width = <8>; |
| 345 | vmmc-supply = <&vmmcsd_fixed>; |
| 346 | mmc-pwrseq = <&emmc_pwrseq>; |
| 347 | }; |
| 348 | |
| 349 | &mcasp0 { |
| 350 | status = "okay"; |
| 351 | pinctrl-names = "default"; |
| 352 | pinctrl-0 = <&audio_pins>; |
| 353 | |
| 354 | op-mode = <0>; /* MCASP_ISS_MODE */ |
| 355 | tdm-slots = <2>; |
| 356 | serial-dir = < |
| 357 | 2 0 1 0 |
| 358 | 0 0 0 0 |
| 359 | 0 0 0 0 |
| 360 | 0 0 0 0 |
| 361 | >; |
| 362 | tx-num-evt = <1>; |
| 363 | rx-num-evt = <1>; |
| 364 | }; |
| 365 | |
| 366 | &uart0 { |
| 367 | status = "okay"; |
| 368 | pinctrl-names = "default"; |
| 369 | pinctrl-0 = <&uart0_pins>; |
| 370 | }; |
| 371 | |
| 372 | &uart4 { |
| 373 | status = "okay"; |
| 374 | pinctrl-names = "default"; |
| 375 | pinctrl-0 = <&uart4_pins>; |
| 376 | }; |
| 377 | |
Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 378 | &tps { |
Heiko Schocher | 8e6ebfa | 2015-10-27 13:36:36 +0100 | [diff] [blame] | 379 | compatible = "ti,tps65217"; |
Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 380 | ti,pmic-shutdown-controller; |
| 381 | |
| 382 | interrupt-parent = <&intc>; |
| 383 | interrupts = <7>; /* NNMI */ |
| 384 | |
| 385 | regulators { |
Heiko Schocher | 8e6ebfa | 2015-10-27 13:36:36 +0100 | [diff] [blame] | 386 | #address-cells = <1>; |
| 387 | #size-cells = <0>; |
| 388 | |
Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 389 | dcdc1_reg: regulator@0 { |
Heiko Schocher | 8e6ebfa | 2015-10-27 13:36:36 +0100 | [diff] [blame] | 390 | reg = <0>; |
Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 391 | /* VDDS_DDR */ |
| 392 | regulator-min-microvolt = <1500000>; |
| 393 | regulator-max-microvolt = <1500000>; |
| 394 | regulator-always-on; |
| 395 | }; |
| 396 | |
| 397 | dcdc2_reg: regulator@1 { |
Heiko Schocher | 8e6ebfa | 2015-10-27 13:36:36 +0100 | [diff] [blame] | 398 | reg = <1>; |
Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 399 | /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ |
| 400 | regulator-name = "vdd_mpu"; |
| 401 | regulator-min-microvolt = <925000>; |
| 402 | regulator-max-microvolt = <1325000>; |
| 403 | regulator-boot-on; |
| 404 | regulator-always-on; |
| 405 | }; |
| 406 | |
| 407 | dcdc3_reg: regulator@2 { |
Heiko Schocher | 8e6ebfa | 2015-10-27 13:36:36 +0100 | [diff] [blame] | 408 | reg = <2>; |
Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 409 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ |
| 410 | regulator-name = "vdd_core"; |
| 411 | regulator-min-microvolt = <925000>; |
| 412 | regulator-max-microvolt = <1150000>; |
| 413 | regulator-boot-on; |
| 414 | regulator-always-on; |
| 415 | }; |
| 416 | |
| 417 | ldo1_reg: regulator@3 { |
Heiko Schocher | 8e6ebfa | 2015-10-27 13:36:36 +0100 | [diff] [blame] | 418 | reg = <3>; |
Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 419 | /* VRTC / VIO / VDDS*/ |
| 420 | regulator-always-on; |
| 421 | regulator-min-microvolt = <1800000>; |
| 422 | regulator-max-microvolt = <1800000>; |
| 423 | }; |
| 424 | |
| 425 | ldo2_reg: regulator@4 { |
Heiko Schocher | 8e6ebfa | 2015-10-27 13:36:36 +0100 | [diff] [blame] | 426 | reg = <4>; |
Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 427 | /* VDD_3V3AUX */ |
| 428 | regulator-always-on; |
| 429 | regulator-min-microvolt = <3300000>; |
| 430 | regulator-max-microvolt = <3300000>; |
| 431 | }; |
| 432 | |
| 433 | ldo3_reg: regulator@5 { |
Heiko Schocher | 8e6ebfa | 2015-10-27 13:36:36 +0100 | [diff] [blame] | 434 | reg = <5>; |
Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 435 | /* VDD_1V8 */ |
| 436 | regulator-min-microvolt = <1800000>; |
| 437 | regulator-max-microvolt = <1800000>; |
| 438 | regulator-always-on; |
| 439 | }; |
| 440 | |
| 441 | ldo4_reg: regulator@6 { |
Heiko Schocher | 8e6ebfa | 2015-10-27 13:36:36 +0100 | [diff] [blame] | 442 | reg = <6>; |
Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 443 | /* VDD_3V3A */ |
| 444 | regulator-min-microvolt = <3300000>; |
| 445 | regulator-max-microvolt = <3300000>; |
| 446 | regulator-always-on; |
| 447 | }; |
| 448 | }; |
| 449 | }; |
| 450 | |
| 451 | &cpsw_emac0 { |
| 452 | phy_id = <&davinci_mdio>, <0>; |
| 453 | phy-mode = "mii"; |
| 454 | }; |
| 455 | |
| 456 | &cpsw_emac1 { |
| 457 | phy_id = <&davinci_mdio>, <1>; |
| 458 | phy-mode = "mii"; |
| 459 | }; |
| 460 | |
| 461 | &mac { |
| 462 | status = "okay"; |
| 463 | pinctrl-names = "default", "sleep"; |
| 464 | pinctrl-0 = <&cpsw_default>; |
| 465 | pinctrl-1 = <&cpsw_sleep>; |
| 466 | }; |
| 467 | |
| 468 | &davinci_mdio { |
| 469 | status = "okay"; |
| 470 | pinctrl-names = "default", "sleep"; |
| 471 | pinctrl-0 = <&davinci_mdio_default>; |
| 472 | pinctrl-1 = <&davinci_mdio_sleep>; |
| 473 | }; |
| 474 | |
| 475 | &sham { |
| 476 | status = "okay"; |
| 477 | }; |
| 478 | |
| 479 | &aes { |
| 480 | status = "okay"; |
| 481 | }; |
| 482 | |
| 483 | &epwmss1 { |
| 484 | status = "okay"; |
| 485 | }; |
| 486 | |
| 487 | &ehrpwm1 { |
| 488 | status = "okay"; |
| 489 | pinctrl-names = "default"; |
| 490 | pinctrl-0 = <&ehrpwm1_pins>; |
| 491 | }; |