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gerrit-public.fairphone.software / kernel / msm-4.19 / 25985edcedea6396277003854657b5f3cb31a628 / . / drivers / usb / gadget / fsl_usb2_udc.h
blob: e88cce5c2c0d707abd79bb9be61ce1ec46e7d23a [file] [log] [blame]
Li Yangb5048822007-04-23 10:54:25 -0700[diff] [blame]1/*
2 * Freescale USB device/endpoint management registers
3 */
4#ifndef __FSL_USB2_UDC_H
5#define __FSL_USB2_UDC_H
6
7/* ### define USB registers here
8 */
9#define USB_MAX_CTRL_PAYLOAD 64
10#define USB_DR_SYS_OFFSET 0x400
11
12 /* USB DR device mode registers (Little Endian) */
13struct usb_dr_device {
14 /* Capability register */
15 u8 res1[256];
16 u16 caplength; /* Capability Register Length */
17 u16 hciversion; /* Host Controller Interface Version */
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame^]18 u32 hcsparams; /* Host Controller Structural Parameters */
Li Yangb5048822007-04-23 10:54:25 -0700[diff] [blame]19 u32 hccparams; /* Host Controller Capability Parameters */
20 u8 res2[20];
21 u32 dciversion; /* Device Controller Interface Version */
22 u32 dccparams; /* Device Controller Capability Parameters */
23 u8 res3[24];
24 /* Operation register */
25 u32 usbcmd; /* USB Command Register */
26 u32 usbsts; /* USB Status Register */
27 u32 usbintr; /* USB Interrupt Enable Register */
28 u32 frindex; /* Frame Index Register */
29 u8 res4[4];
30 u32 deviceaddr; /* Device Address */
31 u32 endpointlistaddr; /* Endpoint List Address Register */
32 u8 res5[4];
33 u32 burstsize; /* Master Interface Data Burst Size Register */
34 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
35 u8 res6[24];
36 u32 configflag; /* Configure Flag Register */
37 u32 portsc1; /* Port 1 Status and Control Register */
38 u8 res7[28];
39 u32 otgsc; /* On-The-Go Status and Control */
40 u32 usbmode; /* USB Mode Register */
41 u32 endptsetupstat; /* Endpoint Setup Status Register */
42 u32 endpointprime; /* Endpoint Initialization Register */
43 u32 endptflush; /* Endpoint Flush Register */
44 u32 endptstatus; /* Endpoint Status Register */
45 u32 endptcomplete; /* Endpoint Complete Register */
46 u32 endptctrl[6]; /* Endpoint Control Registers */
47};
48
49 /* USB DR host mode registers (Little Endian) */
50struct usb_dr_host {
51 /* Capability register */
52 u8 res1[256];
53 u16 caplength; /* Capability Register Length */
54 u16 hciversion; /* Host Controller Interface Version */
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame^]55 u32 hcsparams; /* Host Controller Structural Parameters */
Li Yangb5048822007-04-23 10:54:25 -0700[diff] [blame]56 u32 hccparams; /* Host Controller Capability Parameters */
57 u8 res2[20];
58 u32 dciversion; /* Device Controller Interface Version */
59 u32 dccparams; /* Device Controller Capability Parameters */
60 u8 res3[24];
61 /* Operation register */
62 u32 usbcmd; /* USB Command Register */
63 u32 usbsts; /* USB Status Register */
64 u32 usbintr; /* USB Interrupt Enable Register */
65 u32 frindex; /* Frame Index Register */
66 u8 res4[4];
67 u32 periodiclistbase; /* Periodic Frame List Base Address Register */
68 u32 asynclistaddr; /* Current Asynchronous List Address Register */
69 u8 res5[4];
70 u32 burstsize; /* Master Interface Data Burst Size Register */
71 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
72 u8 res6[24];
73 u32 configflag; /* Configure Flag Register */
74 u32 portsc1; /* Port 1 Status and Control Register */
75 u8 res7[28];
76 u32 otgsc; /* On-The-Go Status and Control */
77 u32 usbmode; /* USB Mode Register */
78 u32 endptsetupstat; /* Endpoint Setup Status Register */
79 u32 endpointprime; /* Endpoint Initialization Register */
80 u32 endptflush; /* Endpoint Flush Register */
81 u32 endptstatus; /* Endpoint Status Register */
82 u32 endptcomplete; /* Endpoint Complete Register */
83 u32 endptctrl[6]; /* Endpoint Control Registers */
84};
85
86 /* non-EHCI USB system interface registers (Big Endian) */
87struct usb_sys_interface {
88 u32 snoop1;
89 u32 snoop2;
90 u32 age_cnt_thresh; /* Age Count Threshold Register */
91 u32 pri_ctrl; /* Priority Control Register */
92 u32 si_ctrl; /* System Interface Control Register */
93 u8 res[236];
94 u32 control; /* General Purpose Control Register */
95};
96
97/* ep0 transfer state */
98#define WAIT_FOR_SETUP 0
99#define DATA_STATE_XMIT 1
100#define DATA_STATE_NEED_ZLP 2
101#define WAIT_FOR_OUT_STATUS 3
102#define DATA_STATE_RECV 4
103
Li Yang43658312007-06-06 21:13:44 -0700[diff] [blame]104/* Device Controller Capability Parameter register */
105#define DCCPARAMS_DC 0x00000080
106#define DCCPARAMS_DEN_MASK 0x0000001f
107
Li Yangb5048822007-04-23 10:54:25 -0700[diff] [blame]108/* Frame Index Register Bit Masks */
109#define USB_FRINDEX_MASKS 0x3fff
110/* USB CMD Register Bit Masks */
111#define USB_CMD_RUN_STOP 0x00000001
112#define USB_CMD_CTRL_RESET 0x00000002
113#define USB_CMD_PERIODIC_SCHEDULE_EN 0x00000010
114#define USB_CMD_ASYNC_SCHEDULE_EN 0x00000020
115#define USB_CMD_INT_AA_DOORBELL 0x00000040
116#define USB_CMD_ASP 0x00000300
117#define USB_CMD_ASYNC_SCH_PARK_EN 0x00000800
118#define USB_CMD_SUTW 0x00002000
119#define USB_CMD_ATDTW 0x00004000
120#define USB_CMD_ITC 0x00FF0000
121
122/* bit 15,3,2 are frame list size */
123#define USB_CMD_FRAME_SIZE_1024 0x00000000
124#define USB_CMD_FRAME_SIZE_512 0x00000004
125#define USB_CMD_FRAME_SIZE_256 0x00000008
126#define USB_CMD_FRAME_SIZE_128 0x0000000C
127#define USB_CMD_FRAME_SIZE_64 0x00008000
128#define USB_CMD_FRAME_SIZE_32 0x00008004
129#define USB_CMD_FRAME_SIZE_16 0x00008008
130#define USB_CMD_FRAME_SIZE_8 0x0000800C
131
132/* bit 9-8 are async schedule park mode count */
133#define USB_CMD_ASP_00 0x00000000
134#define USB_CMD_ASP_01 0x00000100
135#define USB_CMD_ASP_10 0x00000200
136#define USB_CMD_ASP_11 0x00000300
137#define USB_CMD_ASP_BIT_POS 8
138
139/* bit 23-16 are interrupt threshold control */
140#define USB_CMD_ITC_NO_THRESHOLD 0x00000000
141#define USB_CMD_ITC_1_MICRO_FRM 0x00010000
142#define USB_CMD_ITC_2_MICRO_FRM 0x00020000
143#define USB_CMD_ITC_4_MICRO_FRM 0x00040000
144#define USB_CMD_ITC_8_MICRO_FRM 0x00080000
145#define USB_CMD_ITC_16_MICRO_FRM 0x00100000
146#define USB_CMD_ITC_32_MICRO_FRM 0x00200000
147#define USB_CMD_ITC_64_MICRO_FRM 0x00400000
148#define USB_CMD_ITC_BIT_POS 16
149
150/* USB STS Register Bit Masks */
151#define USB_STS_INT 0x00000001
152#define USB_STS_ERR 0x00000002
153#define USB_STS_PORT_CHANGE 0x00000004
154#define USB_STS_FRM_LST_ROLL 0x00000008
155#define USB_STS_SYS_ERR 0x00000010
156#define USB_STS_IAA 0x00000020
157#define USB_STS_RESET 0x00000040
158#define USB_STS_SOF 0x00000080
159#define USB_STS_SUSPEND 0x00000100
160#define USB_STS_HC_HALTED 0x00001000
161#define USB_STS_RCL 0x00002000
162#define USB_STS_PERIODIC_SCHEDULE 0x00004000
163#define USB_STS_ASYNC_SCHEDULE 0x00008000
164
165/* USB INTR Register Bit Masks */
166#define USB_INTR_INT_EN 0x00000001
167#define USB_INTR_ERR_INT_EN 0x00000002
168#define USB_INTR_PTC_DETECT_EN 0x00000004
169#define USB_INTR_FRM_LST_ROLL_EN 0x00000008
170#define USB_INTR_SYS_ERR_EN 0x00000010
171#define USB_INTR_ASYN_ADV_EN 0x00000020
172#define USB_INTR_RESET_EN 0x00000040
173#define USB_INTR_SOF_EN 0x00000080
174#define USB_INTR_DEVICE_SUSPEND 0x00000100
175
176/* Device Address bit masks */
177#define USB_DEVICE_ADDRESS_MASK 0xFE000000
178#define USB_DEVICE_ADDRESS_BIT_POS 25
179
180/* endpoint list address bit masks */
181#define USB_EP_LIST_ADDRESS_MASK 0xfffff800
182
183/* PORTSCX Register Bit Masks */
184#define PORTSCX_CURRENT_CONNECT_STATUS 0x00000001
185#define PORTSCX_CONNECT_STATUS_CHANGE 0x00000002
186#define PORTSCX_PORT_ENABLE 0x00000004
187#define PORTSCX_PORT_EN_DIS_CHANGE 0x00000008
188#define PORTSCX_OVER_CURRENT_ACT 0x00000010
189#define PORTSCX_OVER_CURRENT_CHG 0x00000020
190#define PORTSCX_PORT_FORCE_RESUME 0x00000040
191#define PORTSCX_PORT_SUSPEND 0x00000080
192#define PORTSCX_PORT_RESET 0x00000100
193#define PORTSCX_LINE_STATUS_BITS 0x00000C00
194#define PORTSCX_PORT_POWER 0x00001000
195#define PORTSCX_PORT_INDICTOR_CTRL 0x0000C000
196#define PORTSCX_PORT_TEST_CTRL 0x000F0000
197#define PORTSCX_WAKE_ON_CONNECT_EN 0x00100000
198#define PORTSCX_WAKE_ON_CONNECT_DIS 0x00200000
199#define PORTSCX_WAKE_ON_OVER_CURRENT 0x00400000
200#define PORTSCX_PHY_LOW_POWER_SPD 0x00800000
201#define PORTSCX_PORT_FORCE_FULL_SPEED 0x01000000
202#define PORTSCX_PORT_SPEED_MASK 0x0C000000
203#define PORTSCX_PORT_WIDTH 0x10000000
204#define PORTSCX_PHY_TYPE_SEL 0xC0000000
205
206/* bit 11-10 are line status */
207#define PORTSCX_LINE_STATUS_SE0 0x00000000
208#define PORTSCX_LINE_STATUS_JSTATE 0x00000400
209#define PORTSCX_LINE_STATUS_KSTATE 0x00000800
210#define PORTSCX_LINE_STATUS_UNDEF 0x00000C00
211#define PORTSCX_LINE_STATUS_BIT_POS 10
212
213/* bit 15-14 are port indicator control */
214#define PORTSCX_PIC_OFF 0x00000000
215#define PORTSCX_PIC_AMBER 0x00004000
216#define PORTSCX_PIC_GREEN 0x00008000
217#define PORTSCX_PIC_UNDEF 0x0000C000
218#define PORTSCX_PIC_BIT_POS 14
219
220/* bit 19-16 are port test control */
221#define PORTSCX_PTC_DISABLE 0x00000000
222#define PORTSCX_PTC_JSTATE 0x00010000
223#define PORTSCX_PTC_KSTATE 0x00020000
224#define PORTSCX_PTC_SEQNAK 0x00030000
225#define PORTSCX_PTC_PACKET 0x00040000
226#define PORTSCX_PTC_FORCE_EN 0x00050000
227#define PORTSCX_PTC_BIT_POS 16
228
229/* bit 27-26 are port speed */
230#define PORTSCX_PORT_SPEED_FULL 0x00000000
231#define PORTSCX_PORT_SPEED_LOW 0x04000000
232#define PORTSCX_PORT_SPEED_HIGH 0x08000000
233#define PORTSCX_PORT_SPEED_UNDEF 0x0C000000
234#define PORTSCX_SPEED_BIT_POS 26
235
236/* bit 28 is parallel transceiver width for UTMI interface */
237#define PORTSCX_PTW 0x10000000
238#define PORTSCX_PTW_8BIT 0x00000000
239#define PORTSCX_PTW_16BIT 0x10000000
240
241/* bit 31-30 are port transceiver select */
242#define PORTSCX_PTS_UTMI 0x00000000
243#define PORTSCX_PTS_ULPI 0x80000000
244#define PORTSCX_PTS_FSLS 0xC0000000
245#define PORTSCX_PTS_BIT_POS 30
246
247/* otgsc Register Bit Masks */
248#define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001
249#define OTGSC_CTRL_VUSB_CHARGE 0x00000002
250#define OTGSC_CTRL_OTG_TERM 0x00000008
251#define OTGSC_CTRL_DATA_PULSING 0x00000010
252#define OTGSC_STS_USB_ID 0x00000100
253#define OTGSC_STS_A_VBUS_VALID 0x00000200
254#define OTGSC_STS_A_SESSION_VALID 0x00000400
255#define OTGSC_STS_B_SESSION_VALID 0x00000800
256#define OTGSC_STS_B_SESSION_END 0x00001000
257#define OTGSC_STS_1MS_TOGGLE 0x00002000
258#define OTGSC_STS_DATA_PULSING 0x00004000
259#define OTGSC_INTSTS_USB_ID 0x00010000
260#define OTGSC_INTSTS_A_VBUS_VALID 0x00020000
261#define OTGSC_INTSTS_A_SESSION_VALID 0x00040000
262#define OTGSC_INTSTS_B_SESSION_VALID 0x00080000
263#define OTGSC_INTSTS_B_SESSION_END 0x00100000
264#define OTGSC_INTSTS_1MS 0x00200000
265#define OTGSC_INTSTS_DATA_PULSING 0x00400000
266#define OTGSC_INTR_USB_ID 0x01000000
267#define OTGSC_INTR_A_VBUS_VALID 0x02000000
268#define OTGSC_INTR_A_SESSION_VALID 0x04000000
269#define OTGSC_INTR_B_SESSION_VALID 0x08000000
270#define OTGSC_INTR_B_SESSION_END 0x10000000
271#define OTGSC_INTR_1MS_TIMER 0x20000000
272#define OTGSC_INTR_DATA_PULSING 0x40000000
273
274/* USB MODE Register Bit Masks */
275#define USB_MODE_CTRL_MODE_IDLE 0x00000000
276#define USB_MODE_CTRL_MODE_DEVICE 0x00000002
277#define USB_MODE_CTRL_MODE_HOST 0x00000003
278#define USB_MODE_CTRL_MODE_RSV 0x00000001
279#define USB_MODE_SETUP_LOCK_OFF 0x00000008
280#define USB_MODE_STREAM_DISABLE 0x00000010
281/* Endpoint Flush Register */
282#define EPFLUSH_TX_OFFSET 0x00010000
283#define EPFLUSH_RX_OFFSET 0x00000000
284
285/* Endpoint Setup Status bit masks */
286#define EP_SETUP_STATUS_MASK 0x0000003F
287#define EP_SETUP_STATUS_EP0 0x00000001
288
289/* ENDPOINTCTRLx Register Bit Masks */
290#define EPCTRL_TX_ENABLE 0x00800000
291#define EPCTRL_TX_DATA_TOGGLE_RST 0x00400000 /* Not EP0 */
292#define EPCTRL_TX_DATA_TOGGLE_INH 0x00200000 /* Not EP0 */
293#define EPCTRL_TX_TYPE 0x000C0000
294#define EPCTRL_TX_DATA_SOURCE 0x00020000 /* Not EP0 */
295#define EPCTRL_TX_EP_STALL 0x00010000
296#define EPCTRL_RX_ENABLE 0x00000080
297#define EPCTRL_RX_DATA_TOGGLE_RST 0x00000040 /* Not EP0 */
298#define EPCTRL_RX_DATA_TOGGLE_INH 0x00000020 /* Not EP0 */
299#define EPCTRL_RX_TYPE 0x0000000C
300#define EPCTRL_RX_DATA_SINK 0x00000002 /* Not EP0 */
301#define EPCTRL_RX_EP_STALL 0x00000001
302
303/* bit 19-18 and 3-2 are endpoint type */
304#define EPCTRL_EP_TYPE_CONTROL 0
305#define EPCTRL_EP_TYPE_ISO 1
306#define EPCTRL_EP_TYPE_BULK 2
307#define EPCTRL_EP_TYPE_INTERRUPT 3
308#define EPCTRL_TX_EP_TYPE_SHIFT 18
309#define EPCTRL_RX_EP_TYPE_SHIFT 2
310
311/* SNOOPn Register Bit Masks */
312#define SNOOP_ADDRESS_MASK 0xFFFFF000
313#define SNOOP_SIZE_ZERO 0x00 /* snooping disable */
314#define SNOOP_SIZE_4KB 0x0B /* 4KB snoop size */
315#define SNOOP_SIZE_8KB 0x0C
316#define SNOOP_SIZE_16KB 0x0D
317#define SNOOP_SIZE_32KB 0x0E
318#define SNOOP_SIZE_64KB 0x0F
319#define SNOOP_SIZE_128KB 0x10
320#define SNOOP_SIZE_256KB 0x11
321#define SNOOP_SIZE_512KB 0x12
322#define SNOOP_SIZE_1MB 0x13
323#define SNOOP_SIZE_2MB 0x14
324#define SNOOP_SIZE_4MB 0x15
325#define SNOOP_SIZE_8MB 0x16
326#define SNOOP_SIZE_16MB 0x17
327#define SNOOP_SIZE_32MB 0x18
328#define SNOOP_SIZE_64MB 0x19
329#define SNOOP_SIZE_128MB 0x1A
330#define SNOOP_SIZE_256MB 0x1B
331#define SNOOP_SIZE_512MB 0x1C
332#define SNOOP_SIZE_1GB 0x1D
333#define SNOOP_SIZE_2GB 0x1E /* 2GB snoop size */
334
335/* pri_ctrl Register Bit Masks */
336#define PRI_CTRL_PRI_LVL1 0x0000000C
337#define PRI_CTRL_PRI_LVL0 0x00000003
338
339/* si_ctrl Register Bit Masks */
340#define SI_CTRL_ERR_DISABLE 0x00000010
341#define SI_CTRL_IDRC_DISABLE 0x00000008
342#define SI_CTRL_RD_SAFE_EN 0x00000004
343#define SI_CTRL_RD_PREFETCH_DISABLE 0x00000002
344#define SI_CTRL_RD_PREFEFETCH_VAL 0x00000001
345
346/* control Register Bit Masks */
347#define USB_CTRL_IOENB 0x00000004
348#define USB_CTRL_ULPI_INT0EN 0x00000001
349
350/* Endpoint Queue Head data struct
351 * Rem: all the variables of qh are LittleEndian Mode
352 * and NEXT_POINTER_MASK should operate on a LittleEndian, Phy Addr
353 */
354struct ep_queue_head {
355 u32 max_pkt_length; /* Mult(31-30) , Zlt(29) , Max Pkt len
356 and IOS(15) */
357 u32 curr_dtd_ptr; /* Current dTD Pointer(31-5) */
358 u32 next_dtd_ptr; /* Next dTD Pointer(31-5), T(0) */
359 u32 size_ioc_int_sts; /* Total bytes (30-16), IOC (15),
360 MultO(11-10), STS (7-0) */
361 u32 buff_ptr0; /* Buffer pointer Page 0 (31-12) */
362 u32 buff_ptr1; /* Buffer pointer Page 1 (31-12) */
363 u32 buff_ptr2; /* Buffer pointer Page 2 (31-12) */
364 u32 buff_ptr3; /* Buffer pointer Page 3 (31-12) */
365 u32 buff_ptr4; /* Buffer pointer Page 4 (31-12) */
366 u32 res1;
367 u8 setup_buffer[8]; /* Setup data 8 bytes */
368 u32 res2[4];
369};
370
371/* Endpoint Queue Head Bit Masks */
372#define EP_QUEUE_HEAD_MULT_POS 30
373#define EP_QUEUE_HEAD_ZLT_SEL 0x20000000
374#define EP_QUEUE_HEAD_MAX_PKT_LEN_POS 16
375#define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff)
376#define EP_QUEUE_HEAD_IOS 0x00008000
377#define EP_QUEUE_HEAD_NEXT_TERMINATE 0x00000001
378#define EP_QUEUE_HEAD_IOC 0x00008000
379#define EP_QUEUE_HEAD_MULTO 0x00000C00
380#define EP_QUEUE_HEAD_STATUS_HALT 0x00000040
381#define EP_QUEUE_HEAD_STATUS_ACTIVE 0x00000080
382#define EP_QUEUE_CURRENT_OFFSET_MASK 0x00000FFF
383#define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0
384#define EP_QUEUE_FRINDEX_MASK 0x000007FF
385#define EP_MAX_LENGTH_TRANSFER 0x4000
386
387/* Endpoint Transfer Descriptor data struct */
388/* Rem: all the variables of td are LittleEndian Mode */
389struct ep_td_struct {
390 u32 next_td_ptr; /* Next TD pointer(31-5), T(0) set
391 indicate invalid */
392 u32 size_ioc_sts; /* Total bytes (30-16), IOC (15),
393 MultO(11-10), STS (7-0) */
394 u32 buff_ptr0; /* Buffer pointer Page 0 */
395 u32 buff_ptr1; /* Buffer pointer Page 1 */
396 u32 buff_ptr2; /* Buffer pointer Page 2 */
397 u32 buff_ptr3; /* Buffer pointer Page 3 */
398 u32 buff_ptr4; /* Buffer pointer Page 4 */
399 u32 res;
400 /* 32 bytes */
401 dma_addr_t td_dma; /* dma address for this td */
402 /* virtual address of next td specified in next_td_ptr */
403 struct ep_td_struct *next_td_virt;
404};
405
406/* Endpoint Transfer Descriptor bit Masks */
407#define DTD_NEXT_TERMINATE 0x00000001
408#define DTD_IOC 0x00008000
409#define DTD_STATUS_ACTIVE 0x00000080
410#define DTD_STATUS_HALTED 0x00000040
411#define DTD_STATUS_DATA_BUFF_ERR 0x00000020
412#define DTD_STATUS_TRANSACTION_ERR 0x00000008
413#define DTD_RESERVED_FIELDS 0x80007300
414#define DTD_ADDR_MASK 0xFFFFFFE0
415#define DTD_PACKET_SIZE 0x7FFF0000
416#define DTD_LENGTH_BIT_POS 16
417#define DTD_ERROR_MASK (DTD_STATUS_HALTED | \
418 DTD_STATUS_DATA_BUFF_ERR | \
419 DTD_STATUS_TRANSACTION_ERR)
420/* Alignment requirements; must be a power of two */
421#define DTD_ALIGNMENT 0x20
422#define QH_ALIGNMENT 2048
423
424/* Controller dma boundary */
425#define UDC_DMA_BOUNDARY 0x1000
426
Li Yangb5048822007-04-23 10:54:25 -0700[diff] [blame]427/*-------------------------------------------------------------------------*/
428
429/* ### driver private data
430 */
431struct fsl_req {
432 struct usb_request req;
433 struct list_head queue;
434 /* ep_queue() func will add
435 a request->queue into a udc_ep->queue 'd tail */
436 struct fsl_ep *ep;
437 unsigned mapped:1;
438
439 struct ep_td_struct *head, *tail; /* For dTD List
440 cpu endian Virtual addr */
441 unsigned int dtd_count;
442};
443
444#define REQ_UNCOMPLETE 1
445
446struct fsl_ep {
447 struct usb_ep ep;
448 struct list_head queue;
449 struct fsl_udc *udc;
450 struct ep_queue_head *qh;
451 const struct usb_endpoint_descriptor *desc;
452 struct usb_gadget *gadget;
453
454 char name[14];
455 unsigned stopped:1;
456};
457
458#define EP_DIR_IN 1
459#define EP_DIR_OUT 0
460
461struct fsl_udc {
Li Yangb5048822007-04-23 10:54:25 -0700[diff] [blame]462 struct usb_gadget gadget;
463 struct usb_gadget_driver *driver;
Will Newton7483cff82008-08-12 15:39:09 +0100[diff] [blame]464 struct completion *done; /* to make sure release() is done */
Li Yangb5048822007-04-23 10:54:25 -0700[diff] [blame]465 struct fsl_ep *eps;
466 unsigned int max_ep;
467 unsigned int irq;
468
469 struct usb_ctrlrequest local_setup_buff;
470 spinlock_t lock;
471 struct otg_transceiver *transceiver;
472 unsigned softconnect:1;
473 unsigned vbus_active:1;
474 unsigned stopped:1;
475 unsigned remote_wakeup:1;
476
477 struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */
478 struct fsl_req *status_req; /* ep0 status request */
479 struct dma_pool *td_pool; /* dma pool for DTD */
480 enum fsl_usb2_phy_modes phy_mode;
481
482 size_t ep_qh_size; /* size after alignment adjustment*/
483 dma_addr_t ep_qh_dma; /* dma address of QH */
484
Will Newton7483cff82008-08-12 15:39:09 +0100[diff] [blame]485 u32 max_pipes; /* Device max pipes */
Li Yangb5048822007-04-23 10:54:25 -0700[diff] [blame]486 u32 resume_state; /* USB state to resume */
487 u32 usb_state; /* USB current state */
Li Yangb5048822007-04-23 10:54:25 -0700[diff] [blame]488 u32 ep0_state; /* Endpoint zero state */
489 u32 ep0_dir; /* Endpoint zero direction: can be
490 USB_DIR_IN or USB_DIR_OUT */
Li Yangb5048822007-04-23 10:54:25 -0700[diff] [blame]491 u8 device_address; /* Device USB address */
Li Yangb5048822007-04-23 10:54:25 -0700[diff] [blame]492};
493
494/*-------------------------------------------------------------------------*/
495
496#ifdef DEBUG
497#define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt "\n", \
Harvey Harrison441b62c2008-03-03 16:08:34 -0800[diff] [blame]498 __func__, ## args)
Li Yangb5048822007-04-23 10:54:25 -0700[diff] [blame]499#else
500#define DBG(fmt, args...) do{}while(0)
501#endif
502
503#if 0
504static void dump_msg(const char *label, const u8 * buf, unsigned int length)
505{
506 unsigned int start, num, i;
507 char line[52], *p;
508
509 if (length >= 512)
510 return;
511 DBG("%s, length %u:\n", label, length);
512 start = 0;
513 while (length > 0) {
514 num = min(length, 16u);
515 p = line;
516 for (i = 0; i < num; ++i) {
517 if (i == 8)
518 *p++ = ' ';
519 sprintf(p, " %02x", buf[i]);
520 p += 3;
521 }
522 *p = 0;
523 printk(KERN_DEBUG "%6x: %s\n", start, line);
524 buf += num;
525 start += num;
526 length -= num;
527 }
528}
529#endif
530
531#ifdef VERBOSE
532#define VDBG DBG
533#else
534#define VDBG(stuff...) do{}while(0)
535#endif
536
David Brownell00274922007-11-19 12:58:36 -0800[diff] [blame]537#define ERR(stuff...) pr_err("udc: " stuff)
Arjan van de Venb6c63932008-07-25 01:45:52 -0700[diff] [blame]538#define WARNING(stuff...) pr_warning("udc: " stuff)
David Brownell00274922007-11-19 12:58:36 -0800[diff] [blame]539#define INFO(stuff...) pr_info("udc: " stuff)
Li Yangb5048822007-04-23 10:54:25 -0700[diff] [blame]540
541/*-------------------------------------------------------------------------*/
542
543/* ### Add board specific defines here
544 */
545
546/*
547 * ### pipe direction macro from device view
548 */
549#define USB_RECV 0 /* OUT EP */
550#define USB_SEND 1 /* IN EP */
551
552/*
553 * ### internal used help routines.
554 */
555#define ep_index(EP) ((EP)->desc->bEndpointAddress&0xF)
556#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
557#define ep_is_in(EP) ( (ep_index(EP) == 0) ? (EP->udc->ep0_dir == \
558 USB_DIR_IN ):((EP)->desc->bEndpointAddress \
559 & USB_DIR_IN)==USB_DIR_IN)
560#define get_ep_by_pipe(udc, pipe) ((pipe == 1)? &udc->eps[0]: \
561 &udc->eps[pipe])
562#define get_pipe_by_windex(windex) ((windex & USB_ENDPOINT_NUMBER_MASK) \
563 * 2 + ((windex & USB_DIR_IN) ? 1 : 0))
564#define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP))
565
Guennadi Liakhovetski54e4026b2009-04-15 14:25:33 +0200[diff] [blame]566struct platform_device;
567#ifdef CONFIG_ARCH_MXC
568int fsl_udc_clk_init(struct platform_device *pdev);
569void fsl_udc_clk_finalize(struct platform_device *pdev);
570void fsl_udc_clk_release(void);
571#else
572static inline int fsl_udc_clk_init(struct platform_device *pdev)
573{
574 return 0;
575}
576static inline void fsl_udc_clk_finalize(struct platform_device *pdev)
577{
578}
579static inline void fsl_udc_clk_release(void)
580{
581}
582#endif
583
Li Yangb5048822007-04-23 10:54:25 -0700[diff] [blame]584#endif