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Jan Engelhardtb5114312007-07-15 23:39:36 -07001
2menuconfig CRYPTO_HW
3 bool "Hardware crypto devices"
4 default y
Jan Engelhardt06bfb7e2007-08-18 12:56:21 +02005 ---help---
6 Say Y here to get to see options for hardware crypto devices and
7 processors. This option alone does not add any kernel code.
8
9 If you say N, all options in this submenu will be skipped and disabled.
Jan Engelhardtb5114312007-07-15 23:39:36 -070010
11if CRYPTO_HW
Linus Torvalds1da177e2005-04-16 15:20:36 -070012
13config CRYPTO_DEV_PADLOCK
Herbert Xud1583252007-05-18 13:17:22 +100014 tristate "Support for VIA PadLock ACE"
Herbert Xu2f817412009-04-22 13:00:15 +080015 depends on X86 && !UML
Linus Torvalds1da177e2005-04-16 15:20:36 -070016 help
17 Some VIA processors come with an integrated crypto engine
18 (so called VIA PadLock ACE, Advanced Cryptography Engine)
Michal Ludvig1191f0a2006-08-06 22:46:20 +100019 that provides instructions for very fast cryptographic
20 operations with supported algorithms.
Linus Torvalds1da177e2005-04-16 15:20:36 -070021
22 The instructions are used only when the CPU supports them.
Michal Ludvig5644bda2006-08-06 22:50:30 +100023 Otherwise software encryption is used.
24
Linus Torvalds1da177e2005-04-16 15:20:36 -070025config CRYPTO_DEV_PADLOCK_AES
Michal Ludvig1191f0a2006-08-06 22:46:20 +100026 tristate "PadLock driver for AES algorithm"
Linus Torvalds1da177e2005-04-16 15:20:36 -070027 depends on CRYPTO_DEV_PADLOCK
Herbert Xu28ce7282006-08-21 21:38:42 +100028 select CRYPTO_BLKCIPHER
Sebastian Siewior7dc748e2008-04-01 21:24:50 +080029 select CRYPTO_AES
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 help
31 Use VIA PadLock for AES algorithm.
32
Michal Ludvig1191f0a2006-08-06 22:46:20 +100033 Available in VIA C3 and newer CPUs.
34
35 If unsure say M. The compiled module will be
Pavel Machek4737f092009-06-05 00:44:53 +020036 called padlock-aes.
Michal Ludvig1191f0a2006-08-06 22:46:20 +100037
Michal Ludvig6c833272006-07-12 12:29:38 +100038config CRYPTO_DEV_PADLOCK_SHA
39 tristate "PadLock driver for SHA1 and SHA256 algorithms"
40 depends on CRYPTO_DEV_PADLOCK
Herbert Xubbbee462009-07-11 18:16:16 +080041 select CRYPTO_HASH
Michal Ludvig6c833272006-07-12 12:29:38 +100042 select CRYPTO_SHA1
43 select CRYPTO_SHA256
Michal Ludvig6c833272006-07-12 12:29:38 +100044 help
45 Use VIA PadLock for SHA1/SHA256 algorithms.
46
47 Available in VIA C7 and newer processors.
48
49 If unsure say M. The compiled module will be
Pavel Machek4737f092009-06-05 00:44:53 +020050 called padlock-sha.
Michal Ludvig6c833272006-07-12 12:29:38 +100051
Jordan Crouse9fe757b2006-10-04 18:48:57 +100052config CRYPTO_DEV_GEODE
53 tristate "Support for the Geode LX AES engine"
Simon Arlottf6259de2007-05-02 22:08:26 +100054 depends on X86_32 && PCI
Jordan Crouse9fe757b2006-10-04 18:48:57 +100055 select CRYPTO_ALGAPI
56 select CRYPTO_BLKCIPHER
Jordan Crouse9fe757b2006-10-04 18:48:57 +100057 help
58 Say 'Y' here to use the AMD Geode LX processor on-board AES
David Sterba3dde6ad2007-05-09 07:12:20 +020059 engine for the CryptoAPI AES algorithm.
Jordan Crouse9fe757b2006-10-04 18:48:57 +100060
61 To compile this driver as a module, choose M here: the module
62 will be called geode-aes.
63
Martin Schwidefsky61d48c22007-05-10 15:46:00 +020064config ZCRYPT
65 tristate "Support for PCI-attached cryptographic adapters"
66 depends on S390
Ralph Wuerthner2f7c8bd2008-04-17 07:46:15 +020067 select HW_RANDOM
Martin Schwidefsky61d48c22007-05-10 15:46:00 +020068 help
69 Select this option if you want to use a PCI-attached cryptographic
70 adapter like:
71 + PCI Cryptographic Accelerator (PCICA)
72 + PCI Cryptographic Coprocessor (PCICC)
73 + PCI-X Cryptographic Coprocessor (PCIXCC)
74 + Crypto Express2 Coprocessor (CEX2C)
75 + Crypto Express2 Accelerator (CEX2A)
Holger Denglercf2d0072011-05-23 10:24:30 +020076 + Crypto Express3 Coprocessor (CEX3C)
77 + Crypto Express3 Accelerator (CEX3A)
Martin Schwidefsky61d48c22007-05-10 15:46:00 +020078
Jan Glauber3f5615e2008-01-26 14:11:07 +010079config CRYPTO_SHA1_S390
80 tristate "SHA1 digest algorithm"
81 depends on S390
Herbert Xu563f3462009-01-18 20:33:33 +110082 select CRYPTO_HASH
Jan Glauber3f5615e2008-01-26 14:11:07 +010083 help
84 This is the s390 hardware accelerated implementation of the
85 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
86
Jan Glauberd393d9b2011-04-19 21:29:19 +020087 It is available as of z990.
88
Jan Glauber3f5615e2008-01-26 14:11:07 +010089config CRYPTO_SHA256_S390
90 tristate "SHA256 digest algorithm"
91 depends on S390
Herbert Xu563f3462009-01-18 20:33:33 +110092 select CRYPTO_HASH
Jan Glauber3f5615e2008-01-26 14:11:07 +010093 help
94 This is the s390 hardware accelerated implementation of the
95 SHA256 secure hash standard (DFIPS 180-2).
96
Jan Glauberd393d9b2011-04-19 21:29:19 +020097 It is available as of z9.
Jan Glauber3f5615e2008-01-26 14:11:07 +010098
Jan Glauber291dc7c2008-03-06 19:52:00 +080099config CRYPTO_SHA512_S390
Jan Glauber4e2c6d72008-03-06 19:53:50 +0800100 tristate "SHA384 and SHA512 digest algorithm"
Jan Glauber291dc7c2008-03-06 19:52:00 +0800101 depends on S390
Herbert Xu563f3462009-01-18 20:33:33 +1100102 select CRYPTO_HASH
Jan Glauber291dc7c2008-03-06 19:52:00 +0800103 help
104 This is the s390 hardware accelerated implementation of the
105 SHA512 secure hash standard.
106
Jan Glauberd393d9b2011-04-19 21:29:19 +0200107 It is available as of z10.
Jan Glauber291dc7c2008-03-06 19:52:00 +0800108
Jan Glauber3f5615e2008-01-26 14:11:07 +0100109config CRYPTO_DES_S390
110 tristate "DES and Triple DES cipher algorithms"
111 depends on S390
112 select CRYPTO_ALGAPI
113 select CRYPTO_BLKCIPHER
114 help
Gerald Schaefer0200f3e2011-05-04 15:09:44 +1000115 This is the s390 hardware accelerated implementation of the
Jan Glauber3f5615e2008-01-26 14:11:07 +0100116 DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
117
Gerald Schaefer0200f3e2011-05-04 15:09:44 +1000118 As of z990 the ECB and CBC mode are hardware accelerated.
119 As of z196 the CTR mode is hardware accelerated.
120
Jan Glauber3f5615e2008-01-26 14:11:07 +0100121config CRYPTO_AES_S390
122 tristate "AES cipher algorithms"
123 depends on S390
124 select CRYPTO_ALGAPI
125 select CRYPTO_BLKCIPHER
126 help
127 This is the s390 hardware accelerated implementation of the
Gerald Schaefer99d97222011-04-26 16:12:42 +1000128 AES cipher algorithms (FIPS-197).
Jan Glauber3f5615e2008-01-26 14:11:07 +0100129
Gerald Schaefer99d97222011-04-26 16:12:42 +1000130 As of z9 the ECB and CBC modes are hardware accelerated
131 for 128 bit keys.
132 As of z10 the ECB and CBC modes are hardware accelerated
133 for all AES key sizes.
Gerald Schaefer0200f3e2011-05-04 15:09:44 +1000134 As of z196 the CTR mode is hardware accelerated for all AES
135 key sizes and XTS mode is hardware accelerated for 256 and
Gerald Schaefer99d97222011-04-26 16:12:42 +1000136 512 bit keys.
Jan Glauber3f5615e2008-01-26 14:11:07 +0100137
138config S390_PRNG
139 tristate "Pseudo random number generator device driver"
140 depends on S390
141 default "m"
142 help
143 Select this option if you want to use the s390 pseudo random number
144 generator. The PRNG is part of the cryptographic processor functions
145 and uses triple-DES to generate secure random numbers like the
Jan Glauberd393d9b2011-04-19 21:29:19 +0200146 ANSI X9.17 standard. User-space programs access the
147 pseudo-random-number device through the char device /dev/prandom.
148
149 It is available as of z9.
Jan Glauber3f5615e2008-01-26 14:11:07 +0100150
Gerald Schaeferdf1309c2011-04-19 21:29:18 +0200151config CRYPTO_GHASH_S390
152 tristate "GHASH digest algorithm"
153 depends on S390
154 select CRYPTO_HASH
155 help
156 This is the s390 hardware accelerated implementation of the
157 GHASH message digest algorithm for GCM (Galois/Counter Mode).
158
159 It is available as of z196.
160
Sebastian Andrzej Siewior85a7f0a2009-08-10 12:50:03 +1000161config CRYPTO_DEV_MV_CESA
162 tristate "Marvell's Cryptographic Engine"
163 depends on PLAT_ORION
164 select CRYPTO_ALGAPI
165 select CRYPTO_AES
166 select CRYPTO_BLKCIPHER2
167 help
168 This driver allows you to utilize the Cryptographic Engines and
169 Security Accelerator (CESA) which can be found on the Marvell Orion
170 and Kirkwood SoCs, such as QNAP's TS-209.
171
172 Currently the driver supports AES in ECB and CBC mode without DMA.
173
David S. Miller0a625fd22010-05-19 14:14:04 +1000174config CRYPTO_DEV_NIAGARA2
175 tristate "Niagara2 Stream Processing Unit driver"
David S. Miller50e78162010-09-12 10:44:21 +0800176 select CRYPTO_DES
David S. Miller0a625fd22010-05-19 14:14:04 +1000177 select CRYPTO_ALGAPI
178 depends on SPARC64
179 help
180 Each core of a Niagara2 processor contains a Stream
181 Processing Unit, which itself contains several cryptographic
182 sub-units. One set provides the Modular Arithmetic Unit,
183 used for SSL offload. The other set provides the Cipher
184 Group, which can perform encryption, decryption, hashing,
185 checksumming, and raw copies.
186
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800187config CRYPTO_DEV_HIFN_795X
188 tristate "Driver HIFN 795x crypto accelerator chips"
Evgeniy Polyakovc3041f92007-10-11 19:58:16 +0800189 select CRYPTO_DES
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800190 select CRYPTO_ALGAPI
Herbert Xu653ebd92007-11-27 19:48:27 +0800191 select CRYPTO_BLKCIPHER
Herbert Xu946fef42008-01-26 09:48:44 +1100192 select HW_RANDOM if CRYPTO_DEV_HIFN_795X_RNG
Jan Glauber2707b932007-11-12 21:56:38 +0800193 depends on PCI
Richard Weinberger75b76622011-10-10 12:55:41 +0200194 depends on !ARCH_DMA_ADDR_T_64BIT
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800195 help
196 This option allows you to have support for HIFN 795x crypto adapters.
197
Herbert Xu946fef42008-01-26 09:48:44 +1100198config CRYPTO_DEV_HIFN_795X_RNG
199 bool "HIFN 795x random number generator"
200 depends on CRYPTO_DEV_HIFN_795X
201 help
202 Select this option if you want to enable the random number generator
203 on the HIFN 795x crypto adapters.
Evgeniy Polyakovf7d05612007-10-26 21:31:14 +0800204
Kim Phillips8e8ec592011-03-13 16:54:26 +0800205source drivers/crypto/caam/Kconfig
206
Kim Phillips9c4a7962008-06-23 19:50:15 +0800207config CRYPTO_DEV_TALITOS
208 tristate "Talitos Freescale Security Engine (SEC)"
209 select CRYPTO_ALGAPI
210 select CRYPTO_AUTHENC
211 select HW_RANDOM
212 depends on FSL_SOC
213 help
214 Say 'Y' here to use the Freescale Security Engine (SEC)
215 to offload cryptographic algorithm computation.
216
217 The Freescale SEC is present on PowerQUICC 'E' processors, such
218 as the MPC8349E and MPC8548E.
219
220 To compile this driver as a module, choose M here: the module
221 will be called talitos.
222
Christian Hohnstaedt81bef012008-06-25 14:38:47 +0800223config CRYPTO_DEV_IXP4XX
224 tristate "Driver for IXP4xx crypto hardware acceleration"
225 depends on ARCH_IXP4XX
226 select CRYPTO_DES
227 select CRYPTO_ALGAPI
Imre Kaloz090657e2008-07-13 20:12:11 +0800228 select CRYPTO_AUTHENC
Christian Hohnstaedt81bef012008-06-25 14:38:47 +0800229 select CRYPTO_BLKCIPHER
230 help
231 Driver for the IXP4xx NPE crypto engine.
232
James Hsiao049359d2009-02-05 16:18:13 +1100233config CRYPTO_DEV_PPC4XX
234 tristate "Driver AMCC PPC4xx crypto accelerator"
235 depends on PPC && 4xx
236 select CRYPTO_HASH
237 select CRYPTO_ALGAPI
238 select CRYPTO_BLKCIPHER
239 help
240 This option allows you to have support for AMCC crypto acceleration.
241
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800242config CRYPTO_DEV_OMAP_SHAM
243 tristate "Support for OMAP SHA1/MD5 hw accelerator"
244 depends on ARCH_OMAP2 || ARCH_OMAP3
245 select CRYPTO_SHA1
246 select CRYPTO_MD5
247 help
248 OMAP processors have SHA1/MD5 hw accelerator. Select this if you
249 want to use the OMAP module for SHA1/MD5 algorithms.
250
Dmitry Kasatkin537559a2010-09-03 19:16:02 +0800251config CRYPTO_DEV_OMAP_AES
252 tristate "Support for OMAP AES hw engine"
253 depends on ARCH_OMAP2 || ARCH_OMAP3
254 select CRYPTO_AES
255 help
256 OMAP processors have AES module accelerator. Select this if you
257 want to use the OMAP module for AES algorithms.
258
Jamie Ilesce921362011-02-21 16:43:21 +1100259config CRYPTO_DEV_PICOXCELL
260 tristate "Support for picoXcell IPSEC and Layer2 crypto engines"
Jamie Ilesfad8fa42011-10-20 14:10:26 +0200261 depends on ARCH_PICOXCELL && HAVE_CLK
Jamie Ilesce921362011-02-21 16:43:21 +1100262 select CRYPTO_AES
263 select CRYPTO_AUTHENC
264 select CRYPTO_ALGAPI
265 select CRYPTO_DES
266 select CRYPTO_CBC
267 select CRYPTO_ECB
268 select CRYPTO_SEQIV
269 help
270 This option enables support for the hardware offload engines in the
271 Picochip picoXcell SoC devices. Select this for IPSEC ESP offload
272 and for 3gpp Layer 2 ciphering support.
273
274 Saying m here will build a module named pipcoxcell_crypto.
275
Vladimir Zapolskiya49e4902011-04-08 20:40:51 +0800276config CRYPTO_DEV_S5P
277 tristate "Support for Samsung S5PV210 crypto accelerator"
278 depends on ARCH_S5PV210
279 select CRYPTO_AES
280 select CRYPTO_ALGAPI
281 select CRYPTO_BLKCIPHER
282 help
283 This option allows you to have support for S5P crypto acceleration.
284 Select this to offload Samsung S5PV210 or S5PC110 from AES
285 algorithms execution.
286
Varun Wadekarf1df57d2012-01-13 16:38:37 +1100287config CRYPTO_DEV_TEGRA_AES
288 tristate "Support for TEGRA AES hw engine"
289 depends on ARCH_TEGRA
290 select CRYPTO_AES
291 help
292 TEGRA processors have AES module accelerator. Select this if you
293 want to use the TEGRA module for AES algorithms.
294
295 To compile this driver as a module, choose M here: the module
296 will be called tegra-aes.
297
Andreas Westin2789c082012-04-30 10:11:17 +0200298config CRYPTO_DEV_UX500
299 tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration"
300 depends on ARCH_U8500
301 select CRYPTO_ALGAPI
302 help
303 Driver for ST-Ericsson UX500 crypto engine.
304
305if CRYPTO_DEV_UX500
306 source "drivers/crypto/ux500/Kconfig"
307endif # if CRYPTO_DEV_UX500
308
Jan Engelhardtb5114312007-07-15 23:39:36 -0700309endif # CRYPTO_HW