Christoffer Dall | 64a959d | 2015-11-24 16:51:12 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015, 2016 ARM Ltd. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | #ifndef __KVM_ARM_VGIC_NEW_H__ |
| 17 | #define __KVM_ARM_VGIC_NEW_H__ |
| 18 | |
Eric Auger | 9097773 | 2015-12-01 15:02:35 +0100 | [diff] [blame] | 19 | #include <linux/irqchip/arm-gic-common.h> |
| 20 | |
Marc Zyngier | 2b0cda8 | 2016-04-26 11:06:47 +0100 | [diff] [blame] | 21 | #define PRODUCT_ID_KVM 0x4b /* ASCII code K */ |
| 22 | #define IMPLEMENTER_ARM 0x43b |
| 23 | |
Eric Auger | e2c1f9a | 2015-12-21 16:36:04 +0100 | [diff] [blame] | 24 | #define VGIC_ADDR_UNDEF (-1) |
| 25 | #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF) |
| 26 | |
Andre Przywara | fd59ed3 | 2016-01-27 14:54:30 +0000 | [diff] [blame] | 27 | #define INTERRUPT_ID_BITS_SPIS 10 |
Andre Przywara | 33d3bc9 | 2016-07-15 12:43:34 +0100 | [diff] [blame] | 28 | #define INTERRUPT_ID_BITS_ITS 16 |
Andre Przywara | 055658b | 2015-12-01 14:34:02 +0000 | [diff] [blame] | 29 | #define VGIC_PRI_BITS 5 |
| 30 | |
Marc Zyngier | 0919e84 | 2015-11-26 17:19:25 +0000 | [diff] [blame] | 31 | #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) |
| 32 | |
Vijaya Kumar K | 94574c9 | 2017-01-26 19:50:47 +0530 | [diff] [blame] | 33 | #define VGIC_AFFINITY_0_SHIFT 0 |
| 34 | #define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT) |
| 35 | #define VGIC_AFFINITY_1_SHIFT 8 |
| 36 | #define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT) |
| 37 | #define VGIC_AFFINITY_2_SHIFT 16 |
| 38 | #define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT) |
| 39 | #define VGIC_AFFINITY_3_SHIFT 24 |
| 40 | #define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT) |
| 41 | |
| 42 | #define VGIC_AFFINITY_LEVEL(reg, level) \ |
| 43 | ((((reg) & VGIC_AFFINITY_## level ##_MASK) \ |
| 44 | >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level)) |
| 45 | |
| 46 | /* |
| 47 | * The Userspace encodes the affinity differently from the MPIDR, |
| 48 | * Below macro converts vgic userspace format to MPIDR reg format. |
| 49 | */ |
| 50 | #define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \ |
| 51 | VGIC_AFFINITY_LEVEL(val, 1) | \ |
| 52 | VGIC_AFFINITY_LEVEL(val, 2) | \ |
| 53 | VGIC_AFFINITY_LEVEL(val, 3)) |
| 54 | |
Vijaya Kumar K | d017d7b | 2017-01-26 19:50:51 +0530 | [diff] [blame] | 55 | /* |
| 56 | * As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt, |
| 57 | * below macros are defined for CPUREG encoding. |
| 58 | */ |
| 59 | #define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK 0x000000000000c000 |
| 60 | #define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT 14 |
| 61 | #define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK 0x0000000000003800 |
| 62 | #define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT 11 |
| 63 | #define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK 0x0000000000000780 |
| 64 | #define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT 7 |
| 65 | #define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK 0x0000000000000078 |
| 66 | #define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT 3 |
| 67 | #define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK 0x0000000000000007 |
| 68 | #define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT 0 |
| 69 | |
| 70 | #define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \ |
| 71 | KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \ |
| 72 | KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \ |
| 73 | KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \ |
| 74 | KVM_REG_ARM_VGIC_SYSREG_OP2_MASK) |
| 75 | |
Eric Auger | ea1ad53 | 2017-01-09 16:19:41 +0100 | [diff] [blame] | 76 | /* |
| 77 | * As per Documentation/virtual/kvm/devices/arm-vgic-its.txt, |
| 78 | * below macros are defined for ITS table entry encoding. |
| 79 | */ |
| 80 | #define KVM_ITS_CTE_VALID_SHIFT 63 |
| 81 | #define KVM_ITS_CTE_VALID_MASK BIT_ULL(63) |
| 82 | #define KVM_ITS_CTE_RDBASE_SHIFT 16 |
| 83 | #define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0) |
Eric Auger | eff484e | 2017-05-03 17:38:01 +0200 | [diff] [blame] | 84 | #define KVM_ITS_ITE_NEXT_SHIFT 48 |
| 85 | #define KVM_ITS_ITE_PINTID_SHIFT 16 |
| 86 | #define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16) |
| 87 | #define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0) |
Eric Auger | 57a9a11 | 2017-01-09 16:27:07 +0100 | [diff] [blame] | 88 | #define KVM_ITS_DTE_VALID_SHIFT 63 |
| 89 | #define KVM_ITS_DTE_VALID_MASK BIT_ULL(63) |
| 90 | #define KVM_ITS_DTE_NEXT_SHIFT 49 |
| 91 | #define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49) |
| 92 | #define KVM_ITS_DTE_ITTADDR_SHIFT 5 |
| 93 | #define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5) |
| 94 | #define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0) |
| 95 | #define KVM_ITS_L1E_VALID_MASK BIT_ULL(63) |
| 96 | /* we only support 64 kB translation table page size */ |
| 97 | #define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16) |
Eric Auger | ea1ad53 | 2017-01-09 16:19:41 +0100 | [diff] [blame] | 98 | |
Christoffer Dall | 8694e4d | 2017-01-23 14:07:18 +0100 | [diff] [blame] | 99 | static inline bool irq_is_pending(struct vgic_irq *irq) |
| 100 | { |
| 101 | if (irq->config == VGIC_CONFIG_EDGE) |
| 102 | return irq->pending_latch; |
| 103 | else |
| 104 | return irq->pending_latch || irq->line_level; |
| 105 | } |
| 106 | |
Andre Przywara | e4823a7 | 2015-12-03 11:47:37 +0000 | [diff] [blame] | 107 | struct vgic_vmcr { |
| 108 | u32 ctlr; |
| 109 | u32 abpr; |
| 110 | u32 bpr; |
| 111 | u32 pmr; |
Vijaya Kumar K | 5fb247d | 2017-01-26 19:50:50 +0530 | [diff] [blame] | 112 | /* Below member variable are valid only for GICv3 */ |
| 113 | u32 grpen0; |
| 114 | u32 grpen1; |
Andre Przywara | e4823a7 | 2015-12-03 11:47:37 +0000 | [diff] [blame] | 115 | }; |
| 116 | |
Vijaya Kumar K | 94574c9 | 2017-01-26 19:50:47 +0530 | [diff] [blame] | 117 | struct vgic_reg_attr { |
| 118 | struct kvm_vcpu *vcpu; |
| 119 | gpa_t addr; |
| 120 | }; |
| 121 | |
| 122 | int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr, |
| 123 | struct vgic_reg_attr *reg_attr); |
| 124 | int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr, |
| 125 | struct vgic_reg_attr *reg_attr); |
| 126 | const struct vgic_register_region * |
| 127 | vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev, |
| 128 | gpa_t addr, int len); |
Christoffer Dall | 64a959d | 2015-11-24 16:51:12 +0100 | [diff] [blame] | 129 | struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu, |
| 130 | u32 intid); |
Andre Przywara | 5dd4b92 | 2016-07-15 12:43:27 +0100 | [diff] [blame] | 131 | void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq); |
Christoffer Dall | 81eeb95 | 2015-11-25 10:02:16 -0800 | [diff] [blame] | 132 | bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq); |
Marc Zyngier | 2b0cda8 | 2016-04-26 11:06:47 +0100 | [diff] [blame] | 133 | void vgic_kick_vcpus(struct kvm *kvm); |
Christoffer Dall | 64a959d | 2015-11-24 16:51:12 +0100 | [diff] [blame] | 134 | |
Andre Przywara | 1085fdc | 2016-07-15 12:43:31 +0100 | [diff] [blame] | 135 | int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr, |
| 136 | phys_addr_t addr, phys_addr_t alignment); |
| 137 | |
Marc Zyngier | 140b086 | 2015-11-26 17:19:25 +0000 | [diff] [blame] | 138 | void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu); |
| 139 | void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr); |
| 140 | void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr); |
| 141 | void vgic_v2_set_underflow(struct kvm_vcpu *vcpu); |
Eric Auger | f94591e | 2015-12-21 17:34:52 +0100 | [diff] [blame] | 142 | int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr); |
Christoffer Dall | c3199f2 | 2016-04-25 01:11:37 +0200 | [diff] [blame] | 143 | int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, |
| 144 | int offset, u32 *val); |
Andre Przywara | 878c569 | 2015-12-03 11:48:42 +0000 | [diff] [blame] | 145 | int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write, |
| 146 | int offset, u32 *val); |
Andre Przywara | e4823a7 | 2015-12-03 11:47:37 +0000 | [diff] [blame] | 147 | void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
| 148 | void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
Eric Auger | ad275b8b | 2015-12-21 18:09:38 +0100 | [diff] [blame] | 149 | void vgic_v2_enable(struct kvm_vcpu *vcpu); |
Eric Auger | 9097773 | 2015-12-01 15:02:35 +0100 | [diff] [blame] | 150 | int vgic_v2_probe(const struct gic_kvm_info *info); |
Eric Auger | b0442ee | 2015-12-21 15:04:42 +0100 | [diff] [blame] | 151 | int vgic_v2_map_resources(struct kvm *kvm); |
Andre Przywara | fb848db | 2016-04-26 21:32:49 +0100 | [diff] [blame] | 152 | int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address, |
| 153 | enum vgic_type); |
Marc Zyngier | 140b086 | 2015-11-26 17:19:25 +0000 | [diff] [blame] | 154 | |
Christoffer Dall | 328e566 | 2016-03-24 11:21:04 +0100 | [diff] [blame] | 155 | void vgic_v2_load(struct kvm_vcpu *vcpu); |
| 156 | void vgic_v2_put(struct kvm_vcpu *vcpu); |
| 157 | |
Marc Zyngier | d97594e | 2016-07-17 11:27:23 +0100 | [diff] [blame] | 158 | static inline void vgic_get_irq_kref(struct vgic_irq *irq) |
| 159 | { |
| 160 | if (irq->intid < VGIC_MIN_LPI) |
| 161 | return; |
| 162 | |
| 163 | kref_get(&irq->refcount); |
| 164 | } |
| 165 | |
Marc Zyngier | 59529f6 | 2015-11-30 13:09:53 +0000 | [diff] [blame] | 166 | void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu); |
| 167 | void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr); |
| 168 | void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr); |
| 169 | void vgic_v3_set_underflow(struct kvm_vcpu *vcpu); |
Andre Przywara | e4823a7 | 2015-12-03 11:47:37 +0000 | [diff] [blame] | 170 | void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
| 171 | void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
Eric Auger | ad275b8b | 2015-12-21 18:09:38 +0100 | [diff] [blame] | 172 | void vgic_v3_enable(struct kvm_vcpu *vcpu); |
Eric Auger | 9097773 | 2015-12-01 15:02:35 +0100 | [diff] [blame] | 173 | int vgic_v3_probe(const struct gic_kvm_info *info); |
Eric Auger | b0442ee | 2015-12-21 15:04:42 +0100 | [diff] [blame] | 174 | int vgic_v3_map_resources(struct kvm *kvm); |
Eric Auger | 44de9d6 | 2017-05-04 11:19:52 +0200 | [diff] [blame] | 175 | int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq); |
Eric Auger | 2807712 | 2017-01-09 16:28:27 +0100 | [diff] [blame^] | 176 | int vgic_v3_save_pending_tables(struct kvm *kvm); |
Andre Przywara | ed9b8ce | 2015-12-01 14:34:34 +0000 | [diff] [blame] | 177 | int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t dist_base_address); |
Vladimir Murzin | 7a1ff70 | 2016-09-12 15:49:18 +0100 | [diff] [blame] | 178 | |
Christoffer Dall | 328e566 | 2016-03-24 11:21:04 +0100 | [diff] [blame] | 179 | void vgic_v3_load(struct kvm_vcpu *vcpu); |
| 180 | void vgic_v3_put(struct kvm_vcpu *vcpu); |
| 181 | |
Andre Przywara | c773576 | 2016-08-08 16:45:43 +0100 | [diff] [blame] | 182 | int vgic_register_its_iodevs(struct kvm *kvm); |
Andre Przywara | 59c5ab4 | 2016-07-15 12:43:30 +0100 | [diff] [blame] | 183 | bool vgic_has_its(struct kvm *kvm); |
Andre Przywara | 0e4e82f | 2016-07-15 12:43:38 +0100 | [diff] [blame] | 184 | int kvm_vgic_register_its_device(void); |
Andre Przywara | 33d3bc9 | 2016-07-15 12:43:34 +0100 | [diff] [blame] | 185 | void vgic_enable_lpis(struct kvm_vcpu *vcpu); |
Andre Przywara | 2891a7d | 2016-07-15 12:43:37 +0100 | [diff] [blame] | 186 | int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi); |
Vijaya Kumar K | 94574c9 | 2017-01-26 19:50:47 +0530 | [diff] [blame] | 187 | int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr); |
| 188 | int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, |
| 189 | int offset, u32 *val); |
| 190 | int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write, |
| 191 | int offset, u32 *val); |
Vijaya Kumar K | d017d7b | 2017-01-26 19:50:51 +0530 | [diff] [blame] | 192 | int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write, |
| 193 | u64 id, u64 *val); |
| 194 | int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id, |
| 195 | u64 *reg); |
Vijaya Kumar K | e96a006 | 2017-01-26 19:50:52 +0530 | [diff] [blame] | 196 | int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write, |
| 197 | u32 intid, u64 *val); |
Andre Przywara | 42c8870 | 2016-07-15 12:43:23 +0100 | [diff] [blame] | 198 | int kvm_register_vgic_device(unsigned long type); |
Vijaya Kumar K | 5fb247d | 2017-01-26 19:50:50 +0530 | [diff] [blame] | 199 | void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
| 200 | void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); |
Eric Auger | ad275b8b | 2015-12-21 18:09:38 +0100 | [diff] [blame] | 201 | int vgic_lazy_init(struct kvm *kvm); |
| 202 | int vgic_init(struct kvm *kvm); |
Eric Auger | c86c772 | 2015-11-30 14:01:58 +0100 | [diff] [blame] | 203 | |
Christoffer Dall | 10f92c4 | 2017-01-17 23:09:13 +0100 | [diff] [blame] | 204 | int vgic_debug_init(struct kvm *kvm); |
| 205 | int vgic_debug_destroy(struct kvm *kvm); |
| 206 | |
Eric Auger | dfc99f8 | 2017-03-23 11:51:52 +0100 | [diff] [blame] | 207 | bool lock_all_vcpus(struct kvm *kvm); |
| 208 | void unlock_all_vcpus(struct kvm *kvm); |
| 209 | |
Christoffer Dall | 64a959d | 2015-11-24 16:51:12 +0100 | [diff] [blame] | 210 | #endif |