John Crispin | 2809b31 | 2013-01-20 22:03:46 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This program is free software; you can redistribute it and/or modify it |
| 3 | * under the terms of the GNU General Public License version 2 as published |
| 4 | * by the Free Software Foundation. |
| 5 | * |
| 6 | * Parts of this file are based on Ralink's 2.6.21 BSP |
| 7 | * |
| 8 | * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> |
| 9 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
| 10 | * Copyright (C) 2013 John Crispin <blogic@openwrt.org> |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/module.h> |
| 16 | |
| 17 | #include <asm/mipsregs.h> |
| 18 | #include <asm/mach-ralink/ralink_regs.h> |
| 19 | #include <asm/mach-ralink/rt305x.h> |
| 20 | |
| 21 | #include "common.h" |
| 22 | |
| 23 | enum rt305x_soc_type rt305x_soc; |
| 24 | |
| 25 | struct ralink_pinmux_grp mode_mux[] = { |
| 26 | { |
| 27 | .name = "i2c", |
| 28 | .mask = RT305X_GPIO_MODE_I2C, |
| 29 | .gpio_first = RT305X_GPIO_I2C_SD, |
| 30 | .gpio_last = RT305X_GPIO_I2C_SCLK, |
| 31 | }, { |
| 32 | .name = "spi", |
| 33 | .mask = RT305X_GPIO_MODE_SPI, |
| 34 | .gpio_first = RT305X_GPIO_SPI_EN, |
| 35 | .gpio_last = RT305X_GPIO_SPI_CLK, |
| 36 | }, { |
| 37 | .name = "uartlite", |
| 38 | .mask = RT305X_GPIO_MODE_UART1, |
| 39 | .gpio_first = RT305X_GPIO_UART1_TXD, |
| 40 | .gpio_last = RT305X_GPIO_UART1_RXD, |
| 41 | }, { |
| 42 | .name = "jtag", |
| 43 | .mask = RT305X_GPIO_MODE_JTAG, |
| 44 | .gpio_first = RT305X_GPIO_JTAG_TDO, |
| 45 | .gpio_last = RT305X_GPIO_JTAG_TDI, |
| 46 | }, { |
| 47 | .name = "mdio", |
| 48 | .mask = RT305X_GPIO_MODE_MDIO, |
| 49 | .gpio_first = RT305X_GPIO_MDIO_MDC, |
| 50 | .gpio_last = RT305X_GPIO_MDIO_MDIO, |
| 51 | }, { |
| 52 | .name = "sdram", |
| 53 | .mask = RT305X_GPIO_MODE_SDRAM, |
| 54 | .gpio_first = RT305X_GPIO_SDRAM_MD16, |
| 55 | .gpio_last = RT305X_GPIO_SDRAM_MD31, |
| 56 | }, { |
| 57 | .name = "rgmii", |
| 58 | .mask = RT305X_GPIO_MODE_RGMII, |
| 59 | .gpio_first = RT305X_GPIO_GE0_TXD0, |
| 60 | .gpio_last = RT305X_GPIO_GE0_RXCLK, |
| 61 | }, {0} |
| 62 | }; |
| 63 | |
| 64 | struct ralink_pinmux_grp uart_mux[] = { |
| 65 | { |
| 66 | .name = "uartf", |
| 67 | .mask = RT305X_GPIO_MODE_UARTF, |
| 68 | .gpio_first = RT305X_GPIO_7, |
| 69 | .gpio_last = RT305X_GPIO_14, |
| 70 | }, { |
| 71 | .name = "pcm uartf", |
| 72 | .mask = RT305X_GPIO_MODE_PCM_UARTF, |
| 73 | .gpio_first = RT305X_GPIO_7, |
| 74 | .gpio_last = RT305X_GPIO_14, |
| 75 | }, { |
| 76 | .name = "pcm i2s", |
| 77 | .mask = RT305X_GPIO_MODE_PCM_I2S, |
| 78 | .gpio_first = RT305X_GPIO_7, |
| 79 | .gpio_last = RT305X_GPIO_14, |
| 80 | }, { |
| 81 | .name = "i2s uartf", |
| 82 | .mask = RT305X_GPIO_MODE_I2S_UARTF, |
| 83 | .gpio_first = RT305X_GPIO_7, |
| 84 | .gpio_last = RT305X_GPIO_14, |
| 85 | }, { |
| 86 | .name = "pcm gpio", |
| 87 | .mask = RT305X_GPIO_MODE_PCM_GPIO, |
| 88 | .gpio_first = RT305X_GPIO_10, |
| 89 | .gpio_last = RT305X_GPIO_14, |
| 90 | }, { |
| 91 | .name = "gpio uartf", |
| 92 | .mask = RT305X_GPIO_MODE_GPIO_UARTF, |
| 93 | .gpio_first = RT305X_GPIO_7, |
| 94 | .gpio_last = RT305X_GPIO_14, |
| 95 | }, { |
| 96 | .name = "gpio i2s", |
| 97 | .mask = RT305X_GPIO_MODE_GPIO_I2S, |
| 98 | .gpio_first = RT305X_GPIO_7, |
| 99 | .gpio_last = RT305X_GPIO_14, |
| 100 | }, { |
| 101 | .name = "gpio", |
| 102 | .mask = RT305X_GPIO_MODE_GPIO, |
| 103 | }, {0} |
| 104 | }; |
| 105 | |
| 106 | void rt305x_wdt_reset(void) |
| 107 | { |
| 108 | u32 t; |
| 109 | |
| 110 | /* enable WDT reset output on pin SRAM_CS_N */ |
| 111 | t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); |
| 112 | t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT << |
| 113 | RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT; |
| 114 | rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG); |
| 115 | } |
| 116 | |
| 117 | struct ralink_pinmux gpio_pinmux = { |
| 118 | .mode = mode_mux, |
| 119 | .uart = uart_mux, |
| 120 | .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT, |
| 121 | .wdt_reset = rt305x_wdt_reset, |
| 122 | }; |
| 123 | |
| 124 | void __init ralink_clk_init(void) |
| 125 | { |
| 126 | unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate; |
| 127 | u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); |
| 128 | |
| 129 | if (soc_is_rt305x() || soc_is_rt3350()) { |
| 130 | t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & |
| 131 | RT305X_SYSCFG_CPUCLK_MASK; |
| 132 | switch (t) { |
| 133 | case RT305X_SYSCFG_CPUCLK_LOW: |
| 134 | cpu_rate = 320000000; |
| 135 | break; |
| 136 | case RT305X_SYSCFG_CPUCLK_HIGH: |
| 137 | cpu_rate = 384000000; |
| 138 | break; |
| 139 | } |
| 140 | sys_rate = uart_rate = wdt_rate = cpu_rate / 3; |
| 141 | } else if (soc_is_rt3352()) { |
| 142 | t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & |
| 143 | RT3352_SYSCFG0_CPUCLK_MASK; |
| 144 | switch (t) { |
| 145 | case RT3352_SYSCFG0_CPUCLK_LOW: |
| 146 | cpu_rate = 384000000; |
| 147 | break; |
| 148 | case RT3352_SYSCFG0_CPUCLK_HIGH: |
| 149 | cpu_rate = 400000000; |
| 150 | break; |
| 151 | } |
| 152 | sys_rate = wdt_rate = cpu_rate / 3; |
| 153 | uart_rate = 40000000; |
| 154 | } else if (soc_is_rt5350()) { |
| 155 | t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & |
| 156 | RT5350_SYSCFG0_CPUCLK_MASK; |
| 157 | switch (t) { |
| 158 | case RT5350_SYSCFG0_CPUCLK_360: |
| 159 | cpu_rate = 360000000; |
| 160 | sys_rate = cpu_rate / 3; |
| 161 | break; |
| 162 | case RT5350_SYSCFG0_CPUCLK_320: |
| 163 | cpu_rate = 320000000; |
| 164 | sys_rate = cpu_rate / 4; |
| 165 | break; |
| 166 | case RT5350_SYSCFG0_CPUCLK_300: |
| 167 | cpu_rate = 300000000; |
| 168 | sys_rate = cpu_rate / 3; |
| 169 | break; |
| 170 | default: |
| 171 | BUG(); |
| 172 | } |
| 173 | uart_rate = 40000000; |
| 174 | wdt_rate = sys_rate; |
| 175 | } else { |
| 176 | BUG(); |
| 177 | } |
| 178 | |
| 179 | ralink_clk_add("cpu", cpu_rate); |
| 180 | ralink_clk_add("10000b00.spi", sys_rate); |
| 181 | ralink_clk_add("10000100.timer", wdt_rate); |
| 182 | ralink_clk_add("10000500.uart", uart_rate); |
| 183 | ralink_clk_add("10000c00.uartlite", uart_rate); |
| 184 | } |
| 185 | |
| 186 | void __init ralink_of_remap(void) |
| 187 | { |
| 188 | rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc"); |
| 189 | rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc"); |
| 190 | |
| 191 | if (!rt_sysc_membase || !rt_memc_membase) |
| 192 | panic("Failed to remap core resources"); |
| 193 | } |
| 194 | |
| 195 | void prom_soc_init(struct ralink_soc_info *soc_info) |
| 196 | { |
| 197 | void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); |
| 198 | unsigned char *name; |
| 199 | u32 n0; |
| 200 | u32 n1; |
| 201 | u32 id; |
| 202 | |
| 203 | n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); |
| 204 | n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); |
| 205 | |
| 206 | if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) { |
| 207 | unsigned long icache_sets; |
| 208 | |
| 209 | icache_sets = (read_c0_config1() >> 22) & 7; |
| 210 | if (icache_sets == 1) { |
| 211 | rt305x_soc = RT305X_SOC_RT3050; |
| 212 | name = "RT3050"; |
| 213 | soc_info->compatible = "ralink,rt3050-soc"; |
| 214 | } else { |
| 215 | rt305x_soc = RT305X_SOC_RT3052; |
| 216 | name = "RT3052"; |
| 217 | soc_info->compatible = "ralink,rt3052-soc"; |
| 218 | } |
| 219 | } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { |
| 220 | rt305x_soc = RT305X_SOC_RT3350; |
| 221 | name = "RT3350"; |
| 222 | soc_info->compatible = "ralink,rt3350-soc"; |
| 223 | } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { |
| 224 | rt305x_soc = RT305X_SOC_RT3352; |
| 225 | name = "RT3352"; |
| 226 | soc_info->compatible = "ralink,rt3352-soc"; |
| 227 | } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { |
| 228 | rt305x_soc = RT305X_SOC_RT5350; |
| 229 | name = "RT5350"; |
| 230 | soc_info->compatible = "ralink,rt5350-soc"; |
| 231 | } else { |
| 232 | panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); |
| 233 | } |
| 234 | |
| 235 | id = __raw_readl(sysc + SYSC_REG_CHIP_ID); |
| 236 | |
| 237 | snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, |
| 238 | "Ralink %s id:%u rev:%u", |
| 239 | name, |
| 240 | (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, |
| 241 | (id & CHIP_ID_REV_MASK)); |
| 242 | } |