Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2016 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include "intel_drv.h" |
| 25 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame^] | 26 | /** |
| 27 | * DOC: Display PLLs |
| 28 | * |
| 29 | * Display PLLs used for driving outputs vary by platform. While some have |
| 30 | * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL |
| 31 | * from a pool. In the latter scenario, it is possible that multiple pipes |
| 32 | * share a PLL if their configurations match. |
| 33 | * |
| 34 | * This file provides an abstraction over display PLLs. The function |
| 35 | * intel_shared_dpll_init() initializes the PLLs for the given platform. The |
| 36 | * users of a PLL are tracked and that tracking is integrated with the atomic |
| 37 | * modest interface. During an atomic operation, a PLL can be requested for a |
| 38 | * given CRTC and encoder configuration by calling intel_get_shared_dpll() and |
| 39 | * a previously used PLL can be released with intel_release_shared_dpll(). |
| 40 | * Changes to the users are first staged in the atomic state, and then made |
| 41 | * effective by calling intel_shared_dpll_swap_state() during the atomic |
| 42 | * commit phase. |
| 43 | */ |
| 44 | |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 45 | struct intel_shared_dpll * |
Jim Bride | f169660 | 2016-09-07 15:47:34 -0700 | [diff] [blame] | 46 | skl_find_link_pll(struct drm_i915_private *dev_priv, int clock) |
| 47 | { |
| 48 | struct intel_shared_dpll *pll = NULL; |
| 49 | struct intel_dpll_hw_state dpll_hw_state; |
| 50 | enum intel_dpll_id i; |
| 51 | bool found = false; |
| 52 | |
| 53 | if (!skl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state)) |
| 54 | return pll; |
| 55 | |
| 56 | for (i = DPLL_ID_SKL_DPLL1; i <= DPLL_ID_SKL_DPLL3; i++) { |
| 57 | pll = &dev_priv->shared_dplls[i]; |
| 58 | |
| 59 | /* Only want to check enabled timings first */ |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 60 | if (pll->state.crtc_mask == 0) |
Jim Bride | f169660 | 2016-09-07 15:47:34 -0700 | [diff] [blame] | 61 | continue; |
| 62 | |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 63 | if (memcmp(&dpll_hw_state, &pll->state.hw_state, |
| 64 | sizeof(pll->state.hw_state)) == 0) { |
Jim Bride | f169660 | 2016-09-07 15:47:34 -0700 | [diff] [blame] | 65 | found = true; |
| 66 | break; |
| 67 | } |
| 68 | } |
| 69 | |
| 70 | /* Ok no matching timings, maybe there's a free one? */ |
| 71 | for (i = DPLL_ID_SKL_DPLL1; |
| 72 | ((found == false) && (i <= DPLL_ID_SKL_DPLL3)); i++) { |
| 73 | pll = &dev_priv->shared_dplls[i]; |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 74 | if (pll->state.crtc_mask == 0) { |
| 75 | pll->state.hw_state = dpll_hw_state; |
Jim Bride | f169660 | 2016-09-07 15:47:34 -0700 | [diff] [blame] | 76 | break; |
| 77 | } |
| 78 | } |
| 79 | |
| 80 | return pll; |
| 81 | } |
| 82 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame^] | 83 | /** |
| 84 | * intel_get_shared_dpll_by_id - get a DPLL given its id |
| 85 | * @dev_priv: i915 device instance |
| 86 | * @id: pll id |
| 87 | * |
| 88 | * Returns: |
| 89 | * A pointer to the DPLL with @id |
| 90 | */ |
Jim Bride | f169660 | 2016-09-07 15:47:34 -0700 | [diff] [blame] | 91 | struct intel_shared_dpll * |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 92 | intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, |
| 93 | enum intel_dpll_id id) |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 94 | { |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 95 | return &dev_priv->shared_dplls[id]; |
| 96 | } |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 97 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame^] | 98 | /** |
| 99 | * intel_get_shared_dpll_id - get the id of a DPLL |
| 100 | * @dev_priv: i915 device instance |
| 101 | * @pll: the DPLL |
| 102 | * |
| 103 | * Returns: |
| 104 | * The id of @pll |
| 105 | */ |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 106 | enum intel_dpll_id |
| 107 | intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, |
| 108 | struct intel_shared_dpll *pll) |
| 109 | { |
| 110 | if (WARN_ON(pll < dev_priv->shared_dplls|| |
| 111 | pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll])) |
| 112 | return -1; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 113 | |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 114 | return (enum intel_dpll_id) (pll - dev_priv->shared_dplls); |
| 115 | } |
| 116 | |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 117 | /* For ILK+ */ |
| 118 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| 119 | struct intel_shared_dpll *pll, |
| 120 | bool state) |
| 121 | { |
| 122 | bool cur_state; |
| 123 | struct intel_dpll_hw_state hw_state; |
| 124 | |
| 125 | if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) |
| 126 | return; |
| 127 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 128 | cur_state = pll->funcs.get_hw_state(dev_priv, pll, &hw_state); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 129 | I915_STATE_WARN(cur_state != state, |
| 130 | "%s assertion failure (expected %s, current %s)\n", |
| 131 | pll->name, onoff(state), onoff(cur_state)); |
| 132 | } |
| 133 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame^] | 134 | /** |
| 135 | * intel_prepare_shared_dpll - call a dpll's prepare hook |
| 136 | * @crtc: CRTC which has a shared dpll |
| 137 | * |
| 138 | * This calls the PLL's prepare hook if it has one and if the PLL is not |
| 139 | * already enabled. The prepare hook is platform specific. |
| 140 | */ |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 141 | void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
| 142 | { |
| 143 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 144 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 145 | struct intel_shared_dpll *pll = crtc->config->shared_dpll; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 146 | |
| 147 | if (WARN_ON(pll == NULL)) |
| 148 | return; |
| 149 | |
Maarten Lankhorst | fbf6d87 | 2016-03-23 14:51:12 +0100 | [diff] [blame] | 150 | mutex_lock(&dev_priv->dpll_lock); |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 151 | WARN_ON(!pll->state.crtc_mask); |
Maarten Lankhorst | fbf6d87 | 2016-03-23 14:51:12 +0100 | [diff] [blame] | 152 | if (!pll->active_mask) { |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 153 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
| 154 | WARN_ON(pll->on); |
| 155 | assert_shared_dpll_disabled(dev_priv, pll); |
| 156 | |
Ander Conselvan de Oliveira | eac6176 | 2016-12-29 17:22:10 +0200 | [diff] [blame] | 157 | pll->funcs.prepare(dev_priv, pll); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 158 | } |
Maarten Lankhorst | fbf6d87 | 2016-03-23 14:51:12 +0100 | [diff] [blame] | 159 | mutex_unlock(&dev_priv->dpll_lock); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 160 | } |
| 161 | |
| 162 | /** |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame^] | 163 | * intel_enable_shared_dpll - enable a CRTC's shared DPLL |
| 164 | * @crtc: CRTC which has a shared DPLL |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 165 | * |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame^] | 166 | * Enable the shared DPLL used by @crtc. |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 167 | */ |
| 168 | void intel_enable_shared_dpll(struct intel_crtc *crtc) |
| 169 | { |
| 170 | struct drm_device *dev = crtc->base.dev; |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 171 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 172 | struct intel_shared_dpll *pll = crtc->config->shared_dpll; |
Maarten Lankhorst | 2dd66ebd | 2016-03-14 09:27:52 +0100 | [diff] [blame] | 173 | unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base); |
Maarten Lankhorst | fbf6d87 | 2016-03-23 14:51:12 +0100 | [diff] [blame] | 174 | unsigned old_mask; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 175 | |
| 176 | if (WARN_ON(pll == NULL)) |
| 177 | return; |
| 178 | |
Maarten Lankhorst | fbf6d87 | 2016-03-23 14:51:12 +0100 | [diff] [blame] | 179 | mutex_lock(&dev_priv->dpll_lock); |
| 180 | old_mask = pll->active_mask; |
| 181 | |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 182 | if (WARN_ON(!(pll->state.crtc_mask & crtc_mask)) || |
Maarten Lankhorst | 2dd66ebd | 2016-03-14 09:27:52 +0100 | [diff] [blame] | 183 | WARN_ON(pll->active_mask & crtc_mask)) |
Maarten Lankhorst | fbf6d87 | 2016-03-23 14:51:12 +0100 | [diff] [blame] | 184 | goto out; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 185 | |
Maarten Lankhorst | 2dd66ebd | 2016-03-14 09:27:52 +0100 | [diff] [blame] | 186 | pll->active_mask |= crtc_mask; |
| 187 | |
| 188 | DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n", |
| 189 | pll->name, pll->active_mask, pll->on, |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 190 | crtc->base.base.id); |
| 191 | |
Maarten Lankhorst | 2dd66ebd | 2016-03-14 09:27:52 +0100 | [diff] [blame] | 192 | if (old_mask) { |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 193 | WARN_ON(!pll->on); |
| 194 | assert_shared_dpll_enabled(dev_priv, pll); |
Maarten Lankhorst | fbf6d87 | 2016-03-23 14:51:12 +0100 | [diff] [blame] | 195 | goto out; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 196 | } |
| 197 | WARN_ON(pll->on); |
| 198 | |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 199 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 200 | pll->funcs.enable(dev_priv, pll); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 201 | pll->on = true; |
Maarten Lankhorst | fbf6d87 | 2016-03-23 14:51:12 +0100 | [diff] [blame] | 202 | |
| 203 | out: |
| 204 | mutex_unlock(&dev_priv->dpll_lock); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 205 | } |
| 206 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame^] | 207 | /** |
| 208 | * intel_disable_shared_dpll - disable a CRTC's shared DPLL |
| 209 | * @crtc: CRTC which has a shared DPLL |
| 210 | * |
| 211 | * Disable the shared DPLL used by @crtc. |
| 212 | */ |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 213 | void intel_disable_shared_dpll(struct intel_crtc *crtc) |
| 214 | { |
Tvrtko Ursulin | 6647847 | 2016-11-16 08:55:40 +0000 | [diff] [blame] | 215 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 216 | struct intel_shared_dpll *pll = crtc->config->shared_dpll; |
Maarten Lankhorst | 2dd66ebd | 2016-03-14 09:27:52 +0100 | [diff] [blame] | 217 | unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 218 | |
| 219 | /* PCH only available on ILK+ */ |
Tvrtko Ursulin | 6647847 | 2016-11-16 08:55:40 +0000 | [diff] [blame] | 220 | if (INTEL_GEN(dev_priv) < 5) |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 221 | return; |
| 222 | |
| 223 | if (pll == NULL) |
| 224 | return; |
| 225 | |
Maarten Lankhorst | fbf6d87 | 2016-03-23 14:51:12 +0100 | [diff] [blame] | 226 | mutex_lock(&dev_priv->dpll_lock); |
Maarten Lankhorst | a1475e7 | 2016-03-14 09:27:53 +0100 | [diff] [blame] | 227 | if (WARN_ON(!(pll->active_mask & crtc_mask))) |
Maarten Lankhorst | fbf6d87 | 2016-03-23 14:51:12 +0100 | [diff] [blame] | 228 | goto out; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 229 | |
Maarten Lankhorst | 2dd66ebd | 2016-03-14 09:27:52 +0100 | [diff] [blame] | 230 | DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n", |
| 231 | pll->name, pll->active_mask, pll->on, |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 232 | crtc->base.base.id); |
| 233 | |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 234 | assert_shared_dpll_enabled(dev_priv, pll); |
| 235 | WARN_ON(!pll->on); |
Maarten Lankhorst | 2dd66ebd | 2016-03-14 09:27:52 +0100 | [diff] [blame] | 236 | |
| 237 | pll->active_mask &= ~crtc_mask; |
| 238 | if (pll->active_mask) |
Maarten Lankhorst | fbf6d87 | 2016-03-23 14:51:12 +0100 | [diff] [blame] | 239 | goto out; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 240 | |
| 241 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 242 | pll->funcs.disable(dev_priv, pll); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 243 | pll->on = false; |
Maarten Lankhorst | fbf6d87 | 2016-03-23 14:51:12 +0100 | [diff] [blame] | 244 | |
| 245 | out: |
| 246 | mutex_unlock(&dev_priv->dpll_lock); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 247 | } |
| 248 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 249 | static struct intel_shared_dpll * |
Ander Conselvan de Oliveira | a4780b7 | 2016-03-08 17:46:17 +0200 | [diff] [blame] | 250 | intel_find_shared_dpll(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 251 | struct intel_crtc_state *crtc_state, |
| 252 | enum intel_dpll_id range_min, |
| 253 | enum intel_dpll_id range_max) |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 254 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 255 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 256 | struct intel_shared_dpll *pll; |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 257 | struct intel_shared_dpll_state *shared_dpll; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 258 | enum intel_dpll_id i; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 259 | |
Ander Conselvan de Oliveira | a4780b7 | 2016-03-08 17:46:17 +0200 | [diff] [blame] | 260 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
| 261 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 262 | for (i = range_min; i <= range_max; i++) { |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 263 | pll = &dev_priv->shared_dplls[i]; |
| 264 | |
| 265 | /* Only want to check enabled timings first */ |
| 266 | if (shared_dpll[i].crtc_mask == 0) |
| 267 | continue; |
| 268 | |
| 269 | if (memcmp(&crtc_state->dpll_hw_state, |
| 270 | &shared_dpll[i].hw_state, |
| 271 | sizeof(crtc_state->dpll_hw_state)) == 0) { |
Ville Syrjälä | 78108b7 | 2016-05-27 20:59:19 +0300 | [diff] [blame] | 272 | DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n", |
| 273 | crtc->base.base.id, crtc->base.name, pll->name, |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 274 | shared_dpll[i].crtc_mask, |
Maarten Lankhorst | 2dd66ebd | 2016-03-14 09:27:52 +0100 | [diff] [blame] | 275 | pll->active_mask); |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 276 | return pll; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 277 | } |
| 278 | } |
| 279 | |
| 280 | /* Ok no matching timings, maybe there's a free one? */ |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 281 | for (i = range_min; i <= range_max; i++) { |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 282 | pll = &dev_priv->shared_dplls[i]; |
| 283 | if (shared_dpll[i].crtc_mask == 0) { |
Ville Syrjälä | 78108b7 | 2016-05-27 20:59:19 +0300 | [diff] [blame] | 284 | DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n", |
| 285 | crtc->base.base.id, crtc->base.name, pll->name); |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 286 | return pll; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 287 | } |
| 288 | } |
| 289 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 290 | return NULL; |
Ander Conselvan de Oliveira | a4780b7 | 2016-03-08 17:46:17 +0200 | [diff] [blame] | 291 | } |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 292 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 293 | static void |
| 294 | intel_reference_shared_dpll(struct intel_shared_dpll *pll, |
| 295 | struct intel_crtc_state *crtc_state) |
Ander Conselvan de Oliveira | a4780b7 | 2016-03-08 17:46:17 +0200 | [diff] [blame] | 296 | { |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 297 | struct intel_shared_dpll_state *shared_dpll; |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 298 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
| 299 | enum intel_dpll_id i = pll->id; |
Ander Conselvan de Oliveira | a4780b7 | 2016-03-08 17:46:17 +0200 | [diff] [blame] | 300 | |
| 301 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
| 302 | |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 303 | if (shared_dpll[i].crtc_mask == 0) |
| 304 | shared_dpll[i].hw_state = |
| 305 | crtc_state->dpll_hw_state; |
| 306 | |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 307 | crtc_state->shared_dpll = pll; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 308 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
| 309 | pipe_name(crtc->pipe)); |
| 310 | |
Ander Conselvan de Oliveira | a1c414e | 2016-12-29 17:22:07 +0200 | [diff] [blame] | 311 | shared_dpll[pll->id].crtc_mask |= 1 << crtc->pipe; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 312 | } |
| 313 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame^] | 314 | /** |
| 315 | * intel_shared_dpll_swap_state - make atomic DPLL configuration effective |
| 316 | * @state: atomic state |
| 317 | * |
| 318 | * This is the dpll version of drm_atomic_helper_swap_state() since the |
| 319 | * helper does not handle driver-specific global state. |
| 320 | * |
| 321 | * For consistency with atomic helpers this function does a complete swap, |
| 322 | * i.e. it also puts the current state into @state, even though there is no |
| 323 | * need for that at this moment. |
| 324 | */ |
Ander Conselvan de Oliveira | 3c0fb58 | 2016-12-29 17:22:08 +0200 | [diff] [blame] | 325 | void intel_shared_dpll_swap_state(struct drm_atomic_state *state) |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 326 | { |
| 327 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 328 | struct intel_shared_dpll_state *shared_dpll; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 329 | struct intel_shared_dpll *pll; |
| 330 | enum intel_dpll_id i; |
| 331 | |
| 332 | if (!to_intel_atomic_state(state)->dpll_set) |
| 333 | return; |
| 334 | |
| 335 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
| 336 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 337 | struct intel_shared_dpll_state tmp; |
Ander Conselvan de Oliveira | 3c0fb58 | 2016-12-29 17:22:08 +0200 | [diff] [blame] | 338 | |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 339 | pll = &dev_priv->shared_dplls[i]; |
Ander Conselvan de Oliveira | 3c0fb58 | 2016-12-29 17:22:08 +0200 | [diff] [blame] | 340 | |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 341 | tmp = pll->state; |
| 342 | pll->state = shared_dpll[i]; |
Ander Conselvan de Oliveira | 3c0fb58 | 2016-12-29 17:22:08 +0200 | [diff] [blame] | 343 | shared_dpll[i] = tmp; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 344 | } |
| 345 | } |
| 346 | |
| 347 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
| 348 | struct intel_shared_dpll *pll, |
| 349 | struct intel_dpll_hw_state *hw_state) |
| 350 | { |
| 351 | uint32_t val; |
| 352 | |
| 353 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 354 | return false; |
| 355 | |
| 356 | val = I915_READ(PCH_DPLL(pll->id)); |
| 357 | hw_state->dpll = val; |
| 358 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); |
| 359 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); |
| 360 | |
| 361 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 362 | |
| 363 | return val & DPLL_VCO_ENABLE; |
| 364 | } |
| 365 | |
Ander Conselvan de Oliveira | eac6176 | 2016-12-29 17:22:10 +0200 | [diff] [blame] | 366 | static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv, |
| 367 | struct intel_shared_dpll *pll) |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 368 | { |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 369 | I915_WRITE(PCH_FP0(pll->id), pll->state.hw_state.fp0); |
| 370 | I915_WRITE(PCH_FP1(pll->id), pll->state.hw_state.fp1); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 371 | } |
| 372 | |
| 373 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
| 374 | { |
| 375 | u32 val; |
| 376 | bool enabled; |
| 377 | |
Joonas Lahtinen | 2d1fe07 | 2016-04-07 11:08:05 +0300 | [diff] [blame] | 378 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 379 | |
| 380 | val = I915_READ(PCH_DREF_CONTROL); |
| 381 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | |
| 382 | DREF_SUPERSPREAD_SOURCE_MASK)); |
| 383 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
| 384 | } |
| 385 | |
| 386 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
| 387 | struct intel_shared_dpll *pll) |
| 388 | { |
| 389 | /* PCH refclock must be enabled first */ |
| 390 | ibx_assert_pch_refclk_enabled(dev_priv); |
| 391 | |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 392 | I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 393 | |
| 394 | /* Wait for the clocks to stabilize. */ |
| 395 | POSTING_READ(PCH_DPLL(pll->id)); |
| 396 | udelay(150); |
| 397 | |
| 398 | /* The pixel multiplier can only be updated once the |
| 399 | * DPLL is enabled and the clocks are stable. |
| 400 | * |
| 401 | * So write it again. |
| 402 | */ |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 403 | I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 404 | POSTING_READ(PCH_DPLL(pll->id)); |
| 405 | udelay(200); |
| 406 | } |
| 407 | |
| 408 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, |
| 409 | struct intel_shared_dpll *pll) |
| 410 | { |
Chris Wilson | 91c8a32 | 2016-07-05 10:40:23 +0100 | [diff] [blame] | 411 | struct drm_device *dev = &dev_priv->drm; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 412 | struct intel_crtc *crtc; |
| 413 | |
| 414 | /* Make sure no transcoder isn't still depending on us. */ |
| 415 | for_each_intel_crtc(dev, crtc) { |
Ander Conselvan de Oliveira | 8106ddb | 2016-03-08 17:46:18 +0200 | [diff] [blame] | 416 | if (crtc->config->shared_dpll == pll) |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 417 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
| 418 | } |
| 419 | |
| 420 | I915_WRITE(PCH_DPLL(pll->id), 0); |
| 421 | POSTING_READ(PCH_DPLL(pll->id)); |
| 422 | udelay(200); |
| 423 | } |
| 424 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 425 | static struct intel_shared_dpll * |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 426 | ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, |
| 427 | struct intel_encoder *encoder) |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 428 | { |
| 429 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 430 | struct intel_shared_dpll *pll; |
| 431 | enum intel_dpll_id i; |
| 432 | |
| 433 | if (HAS_PCH_IBX(dev_priv)) { |
| 434 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
| 435 | i = (enum intel_dpll_id) crtc->pipe; |
| 436 | pll = &dev_priv->shared_dplls[i]; |
| 437 | |
Ville Syrjälä | 78108b7 | 2016-05-27 20:59:19 +0300 | [diff] [blame] | 438 | DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n", |
| 439 | crtc->base.base.id, crtc->base.name, pll->name); |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 440 | } else { |
| 441 | pll = intel_find_shared_dpll(crtc, crtc_state, |
| 442 | DPLL_ID_PCH_PLL_A, |
| 443 | DPLL_ID_PCH_PLL_B); |
| 444 | } |
| 445 | |
Ander Conselvan de Oliveira | bb14316 | 2016-05-20 15:47:06 +0300 | [diff] [blame] | 446 | if (!pll) |
| 447 | return NULL; |
| 448 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 449 | /* reference the pll */ |
| 450 | intel_reference_shared_dpll(pll, crtc_state); |
| 451 | |
| 452 | return pll; |
| 453 | } |
| 454 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 455 | static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = { |
Ander Conselvan de Oliveira | eac6176 | 2016-12-29 17:22:10 +0200 | [diff] [blame] | 456 | .prepare = ibx_pch_dpll_prepare, |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 457 | .enable = ibx_pch_dpll_enable, |
| 458 | .disable = ibx_pch_dpll_disable, |
| 459 | .get_hw_state = ibx_pch_dpll_get_hw_state, |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 460 | }; |
| 461 | |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 462 | static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, |
| 463 | struct intel_shared_dpll *pll) |
| 464 | { |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 465 | I915_WRITE(WRPLL_CTL(pll->id), pll->state.hw_state.wrpll); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 466 | POSTING_READ(WRPLL_CTL(pll->id)); |
| 467 | udelay(20); |
| 468 | } |
| 469 | |
| 470 | static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, |
| 471 | struct intel_shared_dpll *pll) |
| 472 | { |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 473 | I915_WRITE(SPLL_CTL, pll->state.hw_state.spll); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 474 | POSTING_READ(SPLL_CTL); |
| 475 | udelay(20); |
| 476 | } |
| 477 | |
| 478 | static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, |
| 479 | struct intel_shared_dpll *pll) |
| 480 | { |
| 481 | uint32_t val; |
| 482 | |
| 483 | val = I915_READ(WRPLL_CTL(pll->id)); |
| 484 | I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); |
| 485 | POSTING_READ(WRPLL_CTL(pll->id)); |
| 486 | } |
| 487 | |
| 488 | static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, |
| 489 | struct intel_shared_dpll *pll) |
| 490 | { |
| 491 | uint32_t val; |
| 492 | |
| 493 | val = I915_READ(SPLL_CTL); |
| 494 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); |
| 495 | POSTING_READ(SPLL_CTL); |
| 496 | } |
| 497 | |
| 498 | static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, |
| 499 | struct intel_shared_dpll *pll, |
| 500 | struct intel_dpll_hw_state *hw_state) |
| 501 | { |
| 502 | uint32_t val; |
| 503 | |
| 504 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 505 | return false; |
| 506 | |
| 507 | val = I915_READ(WRPLL_CTL(pll->id)); |
| 508 | hw_state->wrpll = val; |
| 509 | |
| 510 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 511 | |
| 512 | return val & WRPLL_PLL_ENABLE; |
| 513 | } |
| 514 | |
| 515 | static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, |
| 516 | struct intel_shared_dpll *pll, |
| 517 | struct intel_dpll_hw_state *hw_state) |
| 518 | { |
| 519 | uint32_t val; |
| 520 | |
| 521 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 522 | return false; |
| 523 | |
| 524 | val = I915_READ(SPLL_CTL); |
| 525 | hw_state->spll = val; |
| 526 | |
| 527 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 528 | |
| 529 | return val & SPLL_PLL_ENABLE; |
| 530 | } |
| 531 | |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 532 | #define LC_FREQ 2700 |
| 533 | #define LC_FREQ_2K U64_C(LC_FREQ * 2000) |
| 534 | |
| 535 | #define P_MIN 2 |
| 536 | #define P_MAX 64 |
| 537 | #define P_INC 2 |
| 538 | |
| 539 | /* Constraints for PLL good behavior */ |
| 540 | #define REF_MIN 48 |
| 541 | #define REF_MAX 400 |
| 542 | #define VCO_MIN 2400 |
| 543 | #define VCO_MAX 4800 |
| 544 | |
| 545 | struct hsw_wrpll_rnp { |
| 546 | unsigned p, n2, r2; |
| 547 | }; |
| 548 | |
| 549 | static unsigned hsw_wrpll_get_budget_for_freq(int clock) |
| 550 | { |
| 551 | unsigned budget; |
| 552 | |
| 553 | switch (clock) { |
| 554 | case 25175000: |
| 555 | case 25200000: |
| 556 | case 27000000: |
| 557 | case 27027000: |
| 558 | case 37762500: |
| 559 | case 37800000: |
| 560 | case 40500000: |
| 561 | case 40541000: |
| 562 | case 54000000: |
| 563 | case 54054000: |
| 564 | case 59341000: |
| 565 | case 59400000: |
| 566 | case 72000000: |
| 567 | case 74176000: |
| 568 | case 74250000: |
| 569 | case 81000000: |
| 570 | case 81081000: |
| 571 | case 89012000: |
| 572 | case 89100000: |
| 573 | case 108000000: |
| 574 | case 108108000: |
| 575 | case 111264000: |
| 576 | case 111375000: |
| 577 | case 148352000: |
| 578 | case 148500000: |
| 579 | case 162000000: |
| 580 | case 162162000: |
| 581 | case 222525000: |
| 582 | case 222750000: |
| 583 | case 296703000: |
| 584 | case 297000000: |
| 585 | budget = 0; |
| 586 | break; |
| 587 | case 233500000: |
| 588 | case 245250000: |
| 589 | case 247750000: |
| 590 | case 253250000: |
| 591 | case 298000000: |
| 592 | budget = 1500; |
| 593 | break; |
| 594 | case 169128000: |
| 595 | case 169500000: |
| 596 | case 179500000: |
| 597 | case 202000000: |
| 598 | budget = 2000; |
| 599 | break; |
| 600 | case 256250000: |
| 601 | case 262500000: |
| 602 | case 270000000: |
| 603 | case 272500000: |
| 604 | case 273750000: |
| 605 | case 280750000: |
| 606 | case 281250000: |
| 607 | case 286000000: |
| 608 | case 291750000: |
| 609 | budget = 4000; |
| 610 | break; |
| 611 | case 267250000: |
| 612 | case 268500000: |
| 613 | budget = 5000; |
| 614 | break; |
| 615 | default: |
| 616 | budget = 1000; |
| 617 | break; |
| 618 | } |
| 619 | |
| 620 | return budget; |
| 621 | } |
| 622 | |
| 623 | static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget, |
| 624 | unsigned r2, unsigned n2, unsigned p, |
| 625 | struct hsw_wrpll_rnp *best) |
| 626 | { |
| 627 | uint64_t a, b, c, d, diff, diff_best; |
| 628 | |
| 629 | /* No best (r,n,p) yet */ |
| 630 | if (best->p == 0) { |
| 631 | best->p = p; |
| 632 | best->n2 = n2; |
| 633 | best->r2 = r2; |
| 634 | return; |
| 635 | } |
| 636 | |
| 637 | /* |
| 638 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to |
| 639 | * freq2k. |
| 640 | * |
| 641 | * delta = 1e6 * |
| 642 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / |
| 643 | * freq2k; |
| 644 | * |
| 645 | * and we would like delta <= budget. |
| 646 | * |
| 647 | * If the discrepancy is above the PPM-based budget, always prefer to |
| 648 | * improve upon the previous solution. However, if you're within the |
| 649 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). |
| 650 | */ |
| 651 | a = freq2k * budget * p * r2; |
| 652 | b = freq2k * budget * best->p * best->r2; |
| 653 | diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); |
| 654 | diff_best = abs_diff(freq2k * best->p * best->r2, |
| 655 | LC_FREQ_2K * best->n2); |
| 656 | c = 1000000 * diff; |
| 657 | d = 1000000 * diff_best; |
| 658 | |
| 659 | if (a < c && b < d) { |
| 660 | /* If both are above the budget, pick the closer */ |
| 661 | if (best->p * best->r2 * diff < p * r2 * diff_best) { |
| 662 | best->p = p; |
| 663 | best->n2 = n2; |
| 664 | best->r2 = r2; |
| 665 | } |
| 666 | } else if (a >= c && b < d) { |
| 667 | /* If A is below the threshold but B is above it? Update. */ |
| 668 | best->p = p; |
| 669 | best->n2 = n2; |
| 670 | best->r2 = r2; |
| 671 | } else if (a >= c && b >= d) { |
| 672 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ |
| 673 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { |
| 674 | best->p = p; |
| 675 | best->n2 = n2; |
| 676 | best->r2 = r2; |
| 677 | } |
| 678 | } |
| 679 | /* Otherwise a < c && b >= d, do nothing */ |
| 680 | } |
| 681 | |
| 682 | static void |
| 683 | hsw_ddi_calculate_wrpll(int clock /* in Hz */, |
| 684 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) |
| 685 | { |
| 686 | uint64_t freq2k; |
| 687 | unsigned p, n2, r2; |
| 688 | struct hsw_wrpll_rnp best = { 0, 0, 0 }; |
| 689 | unsigned budget; |
| 690 | |
| 691 | freq2k = clock / 100; |
| 692 | |
| 693 | budget = hsw_wrpll_get_budget_for_freq(clock); |
| 694 | |
| 695 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely |
| 696 | * and directly pass the LC PLL to it. */ |
| 697 | if (freq2k == 5400000) { |
| 698 | *n2_out = 2; |
| 699 | *p_out = 1; |
| 700 | *r2_out = 2; |
| 701 | return; |
| 702 | } |
| 703 | |
| 704 | /* |
| 705 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by |
| 706 | * the WR PLL. |
| 707 | * |
| 708 | * We want R so that REF_MIN <= Ref <= REF_MAX. |
| 709 | * Injecting R2 = 2 * R gives: |
| 710 | * REF_MAX * r2 > LC_FREQ * 2 and |
| 711 | * REF_MIN * r2 < LC_FREQ * 2 |
| 712 | * |
| 713 | * Which means the desired boundaries for r2 are: |
| 714 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN |
| 715 | * |
| 716 | */ |
| 717 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; |
| 718 | r2 <= LC_FREQ * 2 / REF_MIN; |
| 719 | r2++) { |
| 720 | |
| 721 | /* |
| 722 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R |
| 723 | * |
| 724 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. |
| 725 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: |
| 726 | * VCO_MAX * r2 > n2 * LC_FREQ and |
| 727 | * VCO_MIN * r2 < n2 * LC_FREQ) |
| 728 | * |
| 729 | * Which means the desired boundaries for n2 are: |
| 730 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ |
| 731 | */ |
| 732 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; |
| 733 | n2 <= VCO_MAX * r2 / LC_FREQ; |
| 734 | n2++) { |
| 735 | |
| 736 | for (p = P_MIN; p <= P_MAX; p += P_INC) |
| 737 | hsw_wrpll_update_rnp(freq2k, budget, |
| 738 | r2, n2, p, &best); |
| 739 | } |
| 740 | } |
| 741 | |
| 742 | *n2_out = best.n2; |
| 743 | *p_out = best.p; |
| 744 | *r2_out = best.r2; |
| 745 | } |
| 746 | |
Manasi Navare | 81b9fd8 | 2016-09-01 15:08:11 -0700 | [diff] [blame] | 747 | static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int clock, |
| 748 | struct intel_crtc *crtc, |
| 749 | struct intel_crtc_state *crtc_state) |
| 750 | { |
| 751 | struct intel_shared_dpll *pll; |
| 752 | uint32_t val; |
| 753 | unsigned int p, n2, r2; |
| 754 | |
| 755 | hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
| 756 | |
| 757 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | |
| 758 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | |
| 759 | WRPLL_DIVIDER_POST(p); |
| 760 | |
| 761 | crtc_state->dpll_hw_state.wrpll = val; |
| 762 | |
| 763 | pll = intel_find_shared_dpll(crtc, crtc_state, |
| 764 | DPLL_ID_WRPLL1, DPLL_ID_WRPLL2); |
| 765 | |
| 766 | if (!pll) |
| 767 | return NULL; |
| 768 | |
| 769 | return pll; |
| 770 | } |
| 771 | |
| 772 | struct intel_shared_dpll *hsw_ddi_dp_get_dpll(struct intel_encoder *encoder, |
| 773 | int clock) |
| 774 | { |
| 775 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 776 | struct intel_shared_dpll *pll; |
| 777 | enum intel_dpll_id pll_id; |
| 778 | |
| 779 | switch (clock / 2) { |
| 780 | case 81000: |
| 781 | pll_id = DPLL_ID_LCPLL_810; |
| 782 | break; |
| 783 | case 135000: |
| 784 | pll_id = DPLL_ID_LCPLL_1350; |
| 785 | break; |
| 786 | case 270000: |
| 787 | pll_id = DPLL_ID_LCPLL_2700; |
| 788 | break; |
| 789 | default: |
| 790 | DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock); |
| 791 | return NULL; |
| 792 | } |
| 793 | |
| 794 | pll = intel_get_shared_dpll_by_id(dev_priv, pll_id); |
| 795 | |
| 796 | if (!pll) |
| 797 | return NULL; |
| 798 | |
| 799 | return pll; |
| 800 | } |
| 801 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 802 | static struct intel_shared_dpll * |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 803 | hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, |
| 804 | struct intel_encoder *encoder) |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 805 | { |
| 806 | struct intel_shared_dpll *pll; |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 807 | int clock = crtc_state->port_clock; |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 808 | |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 809 | memset(&crtc_state->dpll_hw_state, 0, |
| 810 | sizeof(crtc_state->dpll_hw_state)); |
| 811 | |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 812 | if (encoder->type == INTEL_OUTPUT_HDMI) { |
Manasi Navare | 81b9fd8 | 2016-09-01 15:08:11 -0700 | [diff] [blame] | 813 | pll = hsw_ddi_hdmi_get_dpll(clock, crtc, crtc_state); |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 814 | |
Ville Syrjälä | cca0502 | 2016-06-22 21:57:06 +0300 | [diff] [blame] | 815 | } else if (encoder->type == INTEL_OUTPUT_DP || |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 816 | encoder->type == INTEL_OUTPUT_DP_MST || |
| 817 | encoder->type == INTEL_OUTPUT_EDP) { |
Manasi Navare | 81b9fd8 | 2016-09-01 15:08:11 -0700 | [diff] [blame] | 818 | pll = hsw_ddi_dp_get_dpll(encoder, clock); |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 819 | |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 820 | } else if (encoder->type == INTEL_OUTPUT_ANALOG) { |
| 821 | if (WARN_ON(crtc_state->port_clock / 2 != 135000)) |
| 822 | return NULL; |
| 823 | |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 824 | crtc_state->dpll_hw_state.spll = |
| 825 | SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; |
| 826 | |
| 827 | pll = intel_find_shared_dpll(crtc, crtc_state, |
| 828 | DPLL_ID_SPLL, DPLL_ID_SPLL); |
| 829 | } else { |
| 830 | return NULL; |
| 831 | } |
| 832 | |
| 833 | if (!pll) |
| 834 | return NULL; |
| 835 | |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 836 | intel_reference_shared_dpll(pll, crtc_state); |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 837 | |
| 838 | return pll; |
| 839 | } |
| 840 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 841 | static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = { |
| 842 | .enable = hsw_ddi_wrpll_enable, |
| 843 | .disable = hsw_ddi_wrpll_disable, |
| 844 | .get_hw_state = hsw_ddi_wrpll_get_hw_state, |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 845 | }; |
| 846 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 847 | static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = { |
| 848 | .enable = hsw_ddi_spll_enable, |
| 849 | .disable = hsw_ddi_spll_disable, |
| 850 | .get_hw_state = hsw_ddi_spll_get_hw_state, |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 851 | }; |
| 852 | |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 853 | static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv, |
| 854 | struct intel_shared_dpll *pll) |
| 855 | { |
| 856 | } |
| 857 | |
| 858 | static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv, |
| 859 | struct intel_shared_dpll *pll) |
| 860 | { |
| 861 | } |
| 862 | |
| 863 | static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv, |
| 864 | struct intel_shared_dpll *pll, |
| 865 | struct intel_dpll_hw_state *hw_state) |
| 866 | { |
| 867 | return true; |
| 868 | } |
| 869 | |
| 870 | static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = { |
| 871 | .enable = hsw_ddi_lcpll_enable, |
| 872 | .disable = hsw_ddi_lcpll_disable, |
| 873 | .get_hw_state = hsw_ddi_lcpll_get_hw_state, |
| 874 | }; |
| 875 | |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 876 | struct skl_dpll_regs { |
| 877 | i915_reg_t ctl, cfgcr1, cfgcr2; |
| 878 | }; |
| 879 | |
| 880 | /* this array is indexed by the *shared* pll id */ |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 881 | static const struct skl_dpll_regs skl_dpll_regs[4] = { |
| 882 | { |
| 883 | /* DPLL 0 */ |
| 884 | .ctl = LCPLL1_CTL, |
| 885 | /* DPLL 0 doesn't support HDMI mode */ |
| 886 | }, |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 887 | { |
| 888 | /* DPLL 1 */ |
| 889 | .ctl = LCPLL2_CTL, |
| 890 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1), |
| 891 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1), |
| 892 | }, |
| 893 | { |
| 894 | /* DPLL 2 */ |
| 895 | .ctl = WRPLL_CTL(0), |
| 896 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), |
| 897 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2), |
| 898 | }, |
| 899 | { |
| 900 | /* DPLL 3 */ |
| 901 | .ctl = WRPLL_CTL(1), |
| 902 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), |
| 903 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3), |
| 904 | }, |
| 905 | }; |
| 906 | |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 907 | static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv, |
| 908 | struct intel_shared_dpll *pll) |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 909 | { |
| 910 | uint32_t val; |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 911 | |
| 912 | val = I915_READ(DPLL_CTRL1); |
| 913 | |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 914 | val &= ~(DPLL_CTRL1_HDMI_MODE(pll->id) | DPLL_CTRL1_SSC(pll->id) | |
| 915 | DPLL_CTRL1_LINK_RATE_MASK(pll->id)); |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 916 | val |= pll->state.hw_state.ctrl1 << (pll->id * 6); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 917 | |
| 918 | I915_WRITE(DPLL_CTRL1, val); |
| 919 | POSTING_READ(DPLL_CTRL1); |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 920 | } |
| 921 | |
| 922 | static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, |
| 923 | struct intel_shared_dpll *pll) |
| 924 | { |
| 925 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
| 926 | |
| 927 | skl_ddi_pll_write_ctrl1(dev_priv, pll); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 928 | |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 929 | I915_WRITE(regs[pll->id].cfgcr1, pll->state.hw_state.cfgcr1); |
| 930 | I915_WRITE(regs[pll->id].cfgcr2, pll->state.hw_state.cfgcr2); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 931 | POSTING_READ(regs[pll->id].cfgcr1); |
| 932 | POSTING_READ(regs[pll->id].cfgcr2); |
| 933 | |
| 934 | /* the enable bit is always bit 31 */ |
| 935 | I915_WRITE(regs[pll->id].ctl, |
| 936 | I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); |
| 937 | |
Chris Wilson | 27bf23a | 2016-06-30 15:33:12 +0100 | [diff] [blame] | 938 | if (intel_wait_for_register(dev_priv, |
| 939 | DPLL_STATUS, |
| 940 | DPLL_LOCK(pll->id), |
| 941 | DPLL_LOCK(pll->id), |
| 942 | 5)) |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 943 | DRM_ERROR("DPLL %d not locked\n", pll->id); |
| 944 | } |
| 945 | |
| 946 | static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv, |
| 947 | struct intel_shared_dpll *pll) |
| 948 | { |
| 949 | skl_ddi_pll_write_ctrl1(dev_priv, pll); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 950 | } |
| 951 | |
| 952 | static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, |
| 953 | struct intel_shared_dpll *pll) |
| 954 | { |
| 955 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
| 956 | |
| 957 | /* the enable bit is always bit 31 */ |
| 958 | I915_WRITE(regs[pll->id].ctl, |
| 959 | I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); |
| 960 | POSTING_READ(regs[pll->id].ctl); |
| 961 | } |
| 962 | |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 963 | static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv, |
| 964 | struct intel_shared_dpll *pll) |
| 965 | { |
| 966 | } |
| 967 | |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 968 | static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
| 969 | struct intel_shared_dpll *pll, |
| 970 | struct intel_dpll_hw_state *hw_state) |
| 971 | { |
| 972 | uint32_t val; |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 973 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
| 974 | bool ret; |
| 975 | |
| 976 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 977 | return false; |
| 978 | |
| 979 | ret = false; |
| 980 | |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 981 | val = I915_READ(regs[pll->id].ctl); |
| 982 | if (!(val & LCPLL_PLL_ENABLE)) |
| 983 | goto out; |
| 984 | |
| 985 | val = I915_READ(DPLL_CTRL1); |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 986 | hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f; |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 987 | |
| 988 | /* avoid reading back stale values if HDMI mode is not enabled */ |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 989 | if (val & DPLL_CTRL1_HDMI_MODE(pll->id)) { |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 990 | hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); |
| 991 | hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); |
| 992 | } |
| 993 | ret = true; |
| 994 | |
| 995 | out: |
| 996 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 997 | |
| 998 | return ret; |
| 999 | } |
| 1000 | |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 1001 | static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv, |
| 1002 | struct intel_shared_dpll *pll, |
| 1003 | struct intel_dpll_hw_state *hw_state) |
| 1004 | { |
| 1005 | uint32_t val; |
| 1006 | const struct skl_dpll_regs *regs = skl_dpll_regs; |
| 1007 | bool ret; |
| 1008 | |
| 1009 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 1010 | return false; |
| 1011 | |
| 1012 | ret = false; |
| 1013 | |
| 1014 | /* DPLL0 is always enabled since it drives CDCLK */ |
| 1015 | val = I915_READ(regs[pll->id].ctl); |
| 1016 | if (WARN_ON(!(val & LCPLL_PLL_ENABLE))) |
| 1017 | goto out; |
| 1018 | |
| 1019 | val = I915_READ(DPLL_CTRL1); |
| 1020 | hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f; |
| 1021 | |
| 1022 | ret = true; |
| 1023 | |
| 1024 | out: |
| 1025 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 1026 | |
| 1027 | return ret; |
| 1028 | } |
| 1029 | |
Ander Conselvan de Oliveira | 304b65c | 2016-03-08 17:46:24 +0200 | [diff] [blame] | 1030 | struct skl_wrpll_context { |
| 1031 | uint64_t min_deviation; /* current minimal deviation */ |
| 1032 | uint64_t central_freq; /* chosen central freq */ |
| 1033 | uint64_t dco_freq; /* chosen dco freq */ |
| 1034 | unsigned int p; /* chosen divider */ |
| 1035 | }; |
| 1036 | |
| 1037 | static void skl_wrpll_context_init(struct skl_wrpll_context *ctx) |
| 1038 | { |
| 1039 | memset(ctx, 0, sizeof(*ctx)); |
| 1040 | |
| 1041 | ctx->min_deviation = U64_MAX; |
| 1042 | } |
| 1043 | |
| 1044 | /* DCO freq must be within +1%/-6% of the DCO central freq */ |
| 1045 | #define SKL_DCO_MAX_PDEVIATION 100 |
| 1046 | #define SKL_DCO_MAX_NDEVIATION 600 |
| 1047 | |
| 1048 | static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx, |
| 1049 | uint64_t central_freq, |
| 1050 | uint64_t dco_freq, |
| 1051 | unsigned int divider) |
| 1052 | { |
| 1053 | uint64_t deviation; |
| 1054 | |
| 1055 | deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq), |
| 1056 | central_freq); |
| 1057 | |
| 1058 | /* positive deviation */ |
| 1059 | if (dco_freq >= central_freq) { |
| 1060 | if (deviation < SKL_DCO_MAX_PDEVIATION && |
| 1061 | deviation < ctx->min_deviation) { |
| 1062 | ctx->min_deviation = deviation; |
| 1063 | ctx->central_freq = central_freq; |
| 1064 | ctx->dco_freq = dco_freq; |
| 1065 | ctx->p = divider; |
| 1066 | } |
| 1067 | /* negative deviation */ |
| 1068 | } else if (deviation < SKL_DCO_MAX_NDEVIATION && |
| 1069 | deviation < ctx->min_deviation) { |
| 1070 | ctx->min_deviation = deviation; |
| 1071 | ctx->central_freq = central_freq; |
| 1072 | ctx->dco_freq = dco_freq; |
| 1073 | ctx->p = divider; |
| 1074 | } |
| 1075 | } |
| 1076 | |
| 1077 | static void skl_wrpll_get_multipliers(unsigned int p, |
| 1078 | unsigned int *p0 /* out */, |
| 1079 | unsigned int *p1 /* out */, |
| 1080 | unsigned int *p2 /* out */) |
| 1081 | { |
| 1082 | /* even dividers */ |
| 1083 | if (p % 2 == 0) { |
| 1084 | unsigned int half = p / 2; |
| 1085 | |
| 1086 | if (half == 1 || half == 2 || half == 3 || half == 5) { |
| 1087 | *p0 = 2; |
| 1088 | *p1 = 1; |
| 1089 | *p2 = half; |
| 1090 | } else if (half % 2 == 0) { |
| 1091 | *p0 = 2; |
| 1092 | *p1 = half / 2; |
| 1093 | *p2 = 2; |
| 1094 | } else if (half % 3 == 0) { |
| 1095 | *p0 = 3; |
| 1096 | *p1 = half / 3; |
| 1097 | *p2 = 2; |
| 1098 | } else if (half % 7 == 0) { |
| 1099 | *p0 = 7; |
| 1100 | *p1 = half / 7; |
| 1101 | *p2 = 2; |
| 1102 | } |
| 1103 | } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */ |
| 1104 | *p0 = 3; |
| 1105 | *p1 = 1; |
| 1106 | *p2 = p / 3; |
| 1107 | } else if (p == 5 || p == 7) { |
| 1108 | *p0 = p; |
| 1109 | *p1 = 1; |
| 1110 | *p2 = 1; |
| 1111 | } else if (p == 15) { |
| 1112 | *p0 = 3; |
| 1113 | *p1 = 1; |
| 1114 | *p2 = 5; |
| 1115 | } else if (p == 21) { |
| 1116 | *p0 = 7; |
| 1117 | *p1 = 1; |
| 1118 | *p2 = 3; |
| 1119 | } else if (p == 35) { |
| 1120 | *p0 = 7; |
| 1121 | *p1 = 1; |
| 1122 | *p2 = 5; |
| 1123 | } |
| 1124 | } |
| 1125 | |
| 1126 | struct skl_wrpll_params { |
| 1127 | uint32_t dco_fraction; |
| 1128 | uint32_t dco_integer; |
| 1129 | uint32_t qdiv_ratio; |
| 1130 | uint32_t qdiv_mode; |
| 1131 | uint32_t kdiv; |
| 1132 | uint32_t pdiv; |
| 1133 | uint32_t central_freq; |
| 1134 | }; |
| 1135 | |
| 1136 | static void skl_wrpll_params_populate(struct skl_wrpll_params *params, |
| 1137 | uint64_t afe_clock, |
| 1138 | uint64_t central_freq, |
| 1139 | uint32_t p0, uint32_t p1, uint32_t p2) |
| 1140 | { |
| 1141 | uint64_t dco_freq; |
| 1142 | |
| 1143 | switch (central_freq) { |
| 1144 | case 9600000000ULL: |
| 1145 | params->central_freq = 0; |
| 1146 | break; |
| 1147 | case 9000000000ULL: |
| 1148 | params->central_freq = 1; |
| 1149 | break; |
| 1150 | case 8400000000ULL: |
| 1151 | params->central_freq = 3; |
| 1152 | } |
| 1153 | |
| 1154 | switch (p0) { |
| 1155 | case 1: |
| 1156 | params->pdiv = 0; |
| 1157 | break; |
| 1158 | case 2: |
| 1159 | params->pdiv = 1; |
| 1160 | break; |
| 1161 | case 3: |
| 1162 | params->pdiv = 2; |
| 1163 | break; |
| 1164 | case 7: |
| 1165 | params->pdiv = 4; |
| 1166 | break; |
| 1167 | default: |
| 1168 | WARN(1, "Incorrect PDiv\n"); |
| 1169 | } |
| 1170 | |
| 1171 | switch (p2) { |
| 1172 | case 5: |
| 1173 | params->kdiv = 0; |
| 1174 | break; |
| 1175 | case 2: |
| 1176 | params->kdiv = 1; |
| 1177 | break; |
| 1178 | case 3: |
| 1179 | params->kdiv = 2; |
| 1180 | break; |
| 1181 | case 1: |
| 1182 | params->kdiv = 3; |
| 1183 | break; |
| 1184 | default: |
| 1185 | WARN(1, "Incorrect KDiv\n"); |
| 1186 | } |
| 1187 | |
| 1188 | params->qdiv_ratio = p1; |
| 1189 | params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; |
| 1190 | |
| 1191 | dco_freq = p0 * p1 * p2 * afe_clock; |
| 1192 | |
| 1193 | /* |
| 1194 | * Intermediate values are in Hz. |
| 1195 | * Divide by MHz to match bsepc |
| 1196 | */ |
| 1197 | params->dco_integer = div_u64(dco_freq, 24 * MHz(1)); |
| 1198 | params->dco_fraction = |
| 1199 | div_u64((div_u64(dco_freq, 24) - |
| 1200 | params->dco_integer * MHz(1)) * 0x8000, MHz(1)); |
| 1201 | } |
| 1202 | |
| 1203 | static bool |
| 1204 | skl_ddi_calculate_wrpll(int clock /* in Hz */, |
| 1205 | struct skl_wrpll_params *wrpll_params) |
| 1206 | { |
| 1207 | uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ |
| 1208 | uint64_t dco_central_freq[3] = {8400000000ULL, |
| 1209 | 9000000000ULL, |
| 1210 | 9600000000ULL}; |
| 1211 | static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20, |
| 1212 | 24, 28, 30, 32, 36, 40, 42, 44, |
| 1213 | 48, 52, 54, 56, 60, 64, 66, 68, |
| 1214 | 70, 72, 76, 78, 80, 84, 88, 90, |
| 1215 | 92, 96, 98 }; |
| 1216 | static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 }; |
| 1217 | static const struct { |
| 1218 | const int *list; |
| 1219 | int n_dividers; |
| 1220 | } dividers[] = { |
| 1221 | { even_dividers, ARRAY_SIZE(even_dividers) }, |
| 1222 | { odd_dividers, ARRAY_SIZE(odd_dividers) }, |
| 1223 | }; |
| 1224 | struct skl_wrpll_context ctx; |
| 1225 | unsigned int dco, d, i; |
| 1226 | unsigned int p0, p1, p2; |
| 1227 | |
| 1228 | skl_wrpll_context_init(&ctx); |
| 1229 | |
| 1230 | for (d = 0; d < ARRAY_SIZE(dividers); d++) { |
| 1231 | for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) { |
| 1232 | for (i = 0; i < dividers[d].n_dividers; i++) { |
| 1233 | unsigned int p = dividers[d].list[i]; |
| 1234 | uint64_t dco_freq = p * afe_clock; |
| 1235 | |
| 1236 | skl_wrpll_try_divider(&ctx, |
| 1237 | dco_central_freq[dco], |
| 1238 | dco_freq, |
| 1239 | p); |
| 1240 | /* |
| 1241 | * Skip the remaining dividers if we're sure to |
| 1242 | * have found the definitive divider, we can't |
| 1243 | * improve a 0 deviation. |
| 1244 | */ |
| 1245 | if (ctx.min_deviation == 0) |
| 1246 | goto skip_remaining_dividers; |
| 1247 | } |
| 1248 | } |
| 1249 | |
| 1250 | skip_remaining_dividers: |
| 1251 | /* |
| 1252 | * If a solution is found with an even divider, prefer |
| 1253 | * this one. |
| 1254 | */ |
| 1255 | if (d == 0 && ctx.p) |
| 1256 | break; |
| 1257 | } |
| 1258 | |
| 1259 | if (!ctx.p) { |
| 1260 | DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock); |
| 1261 | return false; |
| 1262 | } |
| 1263 | |
| 1264 | /* |
| 1265 | * gcc incorrectly analyses that these can be used without being |
| 1266 | * initialized. To be fair, it's hard to guess. |
| 1267 | */ |
| 1268 | p0 = p1 = p2 = 0; |
| 1269 | skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); |
| 1270 | skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq, |
| 1271 | p0, p1, p2); |
| 1272 | |
| 1273 | return true; |
| 1274 | } |
| 1275 | |
Jim Bride | 9a4edad | 2016-09-01 15:08:10 -0700 | [diff] [blame] | 1276 | static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc, |
| 1277 | struct intel_crtc_state *crtc_state, |
| 1278 | int clock) |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1279 | { |
Ander Conselvan de Oliveira | 304b65c | 2016-03-08 17:46:24 +0200 | [diff] [blame] | 1280 | uint32_t ctrl1, cfgcr1, cfgcr2; |
Jim Bride | 9a4edad | 2016-09-01 15:08:10 -0700 | [diff] [blame] | 1281 | struct skl_wrpll_params wrpll_params = { 0, }; |
Ander Conselvan de Oliveira | 304b65c | 2016-03-08 17:46:24 +0200 | [diff] [blame] | 1282 | |
| 1283 | /* |
| 1284 | * See comment in intel_dpll_hw_state to understand why we always use 0 |
| 1285 | * as the DPLL id in this function. |
| 1286 | */ |
Ander Conselvan de Oliveira | 304b65c | 2016-03-08 17:46:24 +0200 | [diff] [blame] | 1287 | ctrl1 = DPLL_CTRL1_OVERRIDE(0); |
| 1288 | |
Jim Bride | 9a4edad | 2016-09-01 15:08:10 -0700 | [diff] [blame] | 1289 | ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); |
Ander Conselvan de Oliveira | 304b65c | 2016-03-08 17:46:24 +0200 | [diff] [blame] | 1290 | |
Jim Bride | 9a4edad | 2016-09-01 15:08:10 -0700 | [diff] [blame] | 1291 | if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params)) |
| 1292 | return false; |
Ander Conselvan de Oliveira | 304b65c | 2016-03-08 17:46:24 +0200 | [diff] [blame] | 1293 | |
Jim Bride | 9a4edad | 2016-09-01 15:08:10 -0700 | [diff] [blame] | 1294 | cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | |
| 1295 | DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | |
| 1296 | wrpll_params.dco_integer; |
Ander Conselvan de Oliveira | 304b65c | 2016-03-08 17:46:24 +0200 | [diff] [blame] | 1297 | |
Jim Bride | 9a4edad | 2016-09-01 15:08:10 -0700 | [diff] [blame] | 1298 | cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | |
| 1299 | DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | |
| 1300 | DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | |
| 1301 | DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | |
| 1302 | wrpll_params.central_freq; |
Ander Conselvan de Oliveira | 304b65c | 2016-03-08 17:46:24 +0200 | [diff] [blame] | 1303 | |
| 1304 | memset(&crtc_state->dpll_hw_state, 0, |
| 1305 | sizeof(crtc_state->dpll_hw_state)); |
| 1306 | |
| 1307 | crtc_state->dpll_hw_state.ctrl1 = ctrl1; |
| 1308 | crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; |
| 1309 | crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; |
Jim Bride | 9a4edad | 2016-09-01 15:08:10 -0700 | [diff] [blame] | 1310 | return true; |
| 1311 | } |
| 1312 | |
| 1313 | |
| 1314 | bool skl_ddi_dp_set_dpll_hw_state(int clock, |
| 1315 | struct intel_dpll_hw_state *dpll_hw_state) |
| 1316 | { |
| 1317 | uint32_t ctrl1; |
| 1318 | |
| 1319 | /* |
| 1320 | * See comment in intel_dpll_hw_state to understand why we always use 0 |
| 1321 | * as the DPLL id in this function. |
| 1322 | */ |
| 1323 | ctrl1 = DPLL_CTRL1_OVERRIDE(0); |
| 1324 | switch (clock / 2) { |
| 1325 | case 81000: |
| 1326 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); |
| 1327 | break; |
| 1328 | case 135000: |
| 1329 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); |
| 1330 | break; |
| 1331 | case 270000: |
| 1332 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); |
| 1333 | break; |
| 1334 | /* eDP 1.4 rates */ |
| 1335 | case 162000: |
| 1336 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0); |
| 1337 | break; |
| 1338 | case 108000: |
| 1339 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0); |
| 1340 | break; |
| 1341 | case 216000: |
| 1342 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0); |
| 1343 | break; |
| 1344 | } |
| 1345 | |
| 1346 | dpll_hw_state->ctrl1 = ctrl1; |
| 1347 | return true; |
| 1348 | } |
| 1349 | |
| 1350 | static struct intel_shared_dpll * |
| 1351 | skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, |
| 1352 | struct intel_encoder *encoder) |
| 1353 | { |
| 1354 | struct intel_shared_dpll *pll; |
| 1355 | int clock = crtc_state->port_clock; |
| 1356 | bool bret; |
| 1357 | struct intel_dpll_hw_state dpll_hw_state; |
| 1358 | |
| 1359 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
| 1360 | |
| 1361 | if (encoder->type == INTEL_OUTPUT_HDMI) { |
| 1362 | bret = skl_ddi_hdmi_pll_dividers(crtc, crtc_state, clock); |
| 1363 | if (!bret) { |
| 1364 | DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n"); |
| 1365 | return NULL; |
| 1366 | } |
| 1367 | } else if (encoder->type == INTEL_OUTPUT_DP || |
| 1368 | encoder->type == INTEL_OUTPUT_DP_MST || |
| 1369 | encoder->type == INTEL_OUTPUT_EDP) { |
| 1370 | bret = skl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state); |
| 1371 | if (!bret) { |
| 1372 | DRM_DEBUG_KMS("Could not set DP dpll HW state.\n"); |
| 1373 | return NULL; |
| 1374 | } |
| 1375 | crtc_state->dpll_hw_state = dpll_hw_state; |
| 1376 | } else { |
| 1377 | return NULL; |
| 1378 | } |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1379 | |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 1380 | if (encoder->type == INTEL_OUTPUT_EDP) |
| 1381 | pll = intel_find_shared_dpll(crtc, crtc_state, |
| 1382 | DPLL_ID_SKL_DPLL0, |
| 1383 | DPLL_ID_SKL_DPLL0); |
| 1384 | else |
| 1385 | pll = intel_find_shared_dpll(crtc, crtc_state, |
| 1386 | DPLL_ID_SKL_DPLL1, |
| 1387 | DPLL_ID_SKL_DPLL3); |
Ander Conselvan de Oliveira | 304b65c | 2016-03-08 17:46:24 +0200 | [diff] [blame] | 1388 | if (!pll) |
| 1389 | return NULL; |
| 1390 | |
Ander Conselvan de Oliveira | 304b65c | 2016-03-08 17:46:24 +0200 | [diff] [blame] | 1391 | intel_reference_shared_dpll(pll, crtc_state); |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1392 | |
| 1393 | return pll; |
| 1394 | } |
| 1395 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1396 | static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = { |
| 1397 | .enable = skl_ddi_pll_enable, |
| 1398 | .disable = skl_ddi_pll_disable, |
| 1399 | .get_hw_state = skl_ddi_pll_get_hw_state, |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1400 | }; |
| 1401 | |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 1402 | static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = { |
| 1403 | .enable = skl_ddi_dpll0_enable, |
| 1404 | .disable = skl_ddi_dpll0_disable, |
| 1405 | .get_hw_state = skl_ddi_dpll0_get_hw_state, |
| 1406 | }; |
| 1407 | |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1408 | static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, |
| 1409 | struct intel_shared_dpll *pll) |
| 1410 | { |
| 1411 | uint32_t temp; |
| 1412 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1413 | enum dpio_phy phy; |
| 1414 | enum dpio_channel ch; |
| 1415 | |
Ander Conselvan de Oliveira | 0a116ce | 2016-12-02 10:23:51 +0200 | [diff] [blame] | 1416 | bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1417 | |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1418 | /* Non-SSC reference */ |
Dongwon Kim | da6110b | 2016-04-14 15:37:43 -0700 | [diff] [blame] | 1419 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
| 1420 | temp |= PORT_PLL_REF_SEL; |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1421 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); |
| 1422 | |
Madhav Chauhan | f7044dd | 2016-12-02 10:23:53 +0200 | [diff] [blame] | 1423 | if (IS_GEMINILAKE(dev_priv)) { |
| 1424 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
| 1425 | temp |= PORT_PLL_POWER_ENABLE; |
| 1426 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); |
| 1427 | |
| 1428 | if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & |
| 1429 | PORT_PLL_POWER_STATE), 200)) |
| 1430 | DRM_ERROR("Power state not set for PLL:%d\n", port); |
| 1431 | } |
| 1432 | |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1433 | /* Disable 10 bit clock */ |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1434 | temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1435 | temp &= ~PORT_PLL_10BIT_CLK_ENABLE; |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1436 | I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1437 | |
| 1438 | /* Write P1 & P2 */ |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1439 | temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1440 | temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 1441 | temp |= pll->state.hw_state.ebb0; |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1442 | I915_WRITE(BXT_PORT_PLL_EBB_0(phy, ch), temp); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1443 | |
| 1444 | /* Write M2 integer */ |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1445 | temp = I915_READ(BXT_PORT_PLL(phy, ch, 0)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1446 | temp &= ~PORT_PLL_M2_MASK; |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 1447 | temp |= pll->state.hw_state.pll0; |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1448 | I915_WRITE(BXT_PORT_PLL(phy, ch, 0), temp); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1449 | |
| 1450 | /* Write N */ |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1451 | temp = I915_READ(BXT_PORT_PLL(phy, ch, 1)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1452 | temp &= ~PORT_PLL_N_MASK; |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 1453 | temp |= pll->state.hw_state.pll1; |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1454 | I915_WRITE(BXT_PORT_PLL(phy, ch, 1), temp); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1455 | |
| 1456 | /* Write M2 fraction */ |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1457 | temp = I915_READ(BXT_PORT_PLL(phy, ch, 2)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1458 | temp &= ~PORT_PLL_M2_FRAC_MASK; |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 1459 | temp |= pll->state.hw_state.pll2; |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1460 | I915_WRITE(BXT_PORT_PLL(phy, ch, 2), temp); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1461 | |
| 1462 | /* Write M2 fraction enable */ |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1463 | temp = I915_READ(BXT_PORT_PLL(phy, ch, 3)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1464 | temp &= ~PORT_PLL_M2_FRAC_ENABLE; |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 1465 | temp |= pll->state.hw_state.pll3; |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1466 | I915_WRITE(BXT_PORT_PLL(phy, ch, 3), temp); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1467 | |
| 1468 | /* Write coeff */ |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1469 | temp = I915_READ(BXT_PORT_PLL(phy, ch, 6)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1470 | temp &= ~PORT_PLL_PROP_COEFF_MASK; |
| 1471 | temp &= ~PORT_PLL_INT_COEFF_MASK; |
| 1472 | temp &= ~PORT_PLL_GAIN_CTL_MASK; |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 1473 | temp |= pll->state.hw_state.pll6; |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1474 | I915_WRITE(BXT_PORT_PLL(phy, ch, 6), temp); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1475 | |
| 1476 | /* Write calibration val */ |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1477 | temp = I915_READ(BXT_PORT_PLL(phy, ch, 8)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1478 | temp &= ~PORT_PLL_TARGET_CNT_MASK; |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 1479 | temp |= pll->state.hw_state.pll8; |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1480 | I915_WRITE(BXT_PORT_PLL(phy, ch, 8), temp); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1481 | |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1482 | temp = I915_READ(BXT_PORT_PLL(phy, ch, 9)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1483 | temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 1484 | temp |= pll->state.hw_state.pll9; |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1485 | I915_WRITE(BXT_PORT_PLL(phy, ch, 9), temp); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1486 | |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1487 | temp = I915_READ(BXT_PORT_PLL(phy, ch, 10)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1488 | temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; |
| 1489 | temp &= ~PORT_PLL_DCO_AMP_MASK; |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 1490 | temp |= pll->state.hw_state.pll10; |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1491 | I915_WRITE(BXT_PORT_PLL(phy, ch, 10), temp); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1492 | |
| 1493 | /* Recalibrate with new settings */ |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1494 | temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1495 | temp |= PORT_PLL_RECALIBRATE; |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1496 | I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1497 | temp &= ~PORT_PLL_10BIT_CLK_ENABLE; |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 1498 | temp |= pll->state.hw_state.ebb4; |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1499 | I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1500 | |
| 1501 | /* Enable PLL */ |
| 1502 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
| 1503 | temp |= PORT_PLL_ENABLE; |
| 1504 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); |
| 1505 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); |
| 1506 | |
Imre Deak | 0b786e4 | 2016-06-28 13:37:30 +0300 | [diff] [blame] | 1507 | if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), |
| 1508 | 200)) |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1509 | DRM_ERROR("PLL %d not locked\n", port); |
| 1510 | |
Ander Conselvan de Oliveira | 51b3ee3 | 2016-12-02 10:23:52 +0200 | [diff] [blame] | 1511 | if (IS_GEMINILAKE(dev_priv)) { |
| 1512 | temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch)); |
| 1513 | temp |= DCC_DELAY_RANGE_2; |
| 1514 | I915_WRITE(BXT_PORT_TX_DW5_GRP(phy, ch), temp); |
| 1515 | } |
| 1516 | |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1517 | /* |
| 1518 | * While we write to the group register to program all lanes at once we |
| 1519 | * can read only lane registers and we pick lanes 0/1 for that. |
| 1520 | */ |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1521 | temp = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1522 | temp &= ~LANE_STAGGER_MASK; |
| 1523 | temp &= ~LANESTAGGER_STRAP_OVRD; |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 1524 | temp |= pll->state.hw_state.pcsdw12; |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1525 | I915_WRITE(BXT_PORT_PCS_DW12_GRP(phy, ch), temp); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1526 | } |
| 1527 | |
| 1528 | static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, |
| 1529 | struct intel_shared_dpll *pll) |
| 1530 | { |
| 1531 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ |
| 1532 | uint32_t temp; |
| 1533 | |
| 1534 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
| 1535 | temp &= ~PORT_PLL_ENABLE; |
| 1536 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); |
| 1537 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); |
Madhav Chauhan | f7044dd | 2016-12-02 10:23:53 +0200 | [diff] [blame] | 1538 | |
| 1539 | if (IS_GEMINILAKE(dev_priv)) { |
| 1540 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
| 1541 | temp &= ~PORT_PLL_POWER_ENABLE; |
| 1542 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); |
| 1543 | |
| 1544 | if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) & |
| 1545 | PORT_PLL_POWER_STATE), 200)) |
| 1546 | DRM_ERROR("Power state not reset for PLL:%d\n", port); |
| 1547 | } |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1548 | } |
| 1549 | |
| 1550 | static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
| 1551 | struct intel_shared_dpll *pll, |
| 1552 | struct intel_dpll_hw_state *hw_state) |
| 1553 | { |
| 1554 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ |
| 1555 | uint32_t val; |
| 1556 | bool ret; |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1557 | enum dpio_phy phy; |
| 1558 | enum dpio_channel ch; |
| 1559 | |
Ander Conselvan de Oliveira | 0a116ce | 2016-12-02 10:23:51 +0200 | [diff] [blame] | 1560 | bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1561 | |
| 1562 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
| 1563 | return false; |
| 1564 | |
| 1565 | ret = false; |
| 1566 | |
| 1567 | val = I915_READ(BXT_PORT_PLL_ENABLE(port)); |
| 1568 | if (!(val & PORT_PLL_ENABLE)) |
| 1569 | goto out; |
| 1570 | |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1571 | hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1572 | hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; |
| 1573 | |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1574 | hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1575 | hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; |
| 1576 | |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1577 | hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1578 | hw_state->pll0 &= PORT_PLL_M2_MASK; |
| 1579 | |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1580 | hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1581 | hw_state->pll1 &= PORT_PLL_N_MASK; |
| 1582 | |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1583 | hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1584 | hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; |
| 1585 | |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1586 | hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1587 | hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; |
| 1588 | |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1589 | hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1590 | hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | |
| 1591 | PORT_PLL_INT_COEFF_MASK | |
| 1592 | PORT_PLL_GAIN_CTL_MASK; |
| 1593 | |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1594 | hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1595 | hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; |
| 1596 | |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1597 | hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1598 | hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; |
| 1599 | |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1600 | hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10)); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1601 | hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | |
| 1602 | PORT_PLL_DCO_AMP_MASK; |
| 1603 | |
| 1604 | /* |
| 1605 | * While we write to the group register to program all lanes at once we |
| 1606 | * can read only lane registers. We configure all lanes the same way, so |
| 1607 | * here just read out lanes 0/1 and output a note if lanes 2/3 differ. |
| 1608 | */ |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1609 | hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch)); |
| 1610 | if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1611 | DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", |
| 1612 | hw_state->pcsdw12, |
Ander Conselvan de Oliveira | ed37892 | 2016-10-19 10:59:00 +0300 | [diff] [blame] | 1613 | I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch))); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1614 | hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; |
| 1615 | |
| 1616 | ret = true; |
| 1617 | |
| 1618 | out: |
| 1619 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
| 1620 | |
| 1621 | return ret; |
| 1622 | } |
| 1623 | |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1624 | /* bxt clock parameters */ |
| 1625 | struct bxt_clk_div { |
| 1626 | int clock; |
| 1627 | uint32_t p1; |
| 1628 | uint32_t p2; |
| 1629 | uint32_t m2_int; |
| 1630 | uint32_t m2_frac; |
| 1631 | bool m2_frac_en; |
| 1632 | uint32_t n; |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1633 | |
| 1634 | int vco; |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1635 | }; |
| 1636 | |
| 1637 | /* pre-calculated values for DP linkrates */ |
| 1638 | static const struct bxt_clk_div bxt_dp_clk_val[] = { |
| 1639 | {162000, 4, 2, 32, 1677722, 1, 1}, |
| 1640 | {270000, 4, 1, 27, 0, 0, 1}, |
| 1641 | {540000, 2, 1, 27, 0, 0, 1}, |
| 1642 | {216000, 3, 2, 32, 1677722, 1, 1}, |
| 1643 | {243000, 4, 1, 24, 1258291, 1, 1}, |
| 1644 | {324000, 4, 1, 32, 1677722, 1, 1}, |
| 1645 | {432000, 3, 1, 32, 1677722, 1, 1} |
| 1646 | }; |
| 1647 | |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1648 | static bool |
| 1649 | bxt_ddi_hdmi_pll_dividers(struct intel_crtc *intel_crtc, |
| 1650 | struct intel_crtc_state *crtc_state, int clock, |
| 1651 | struct bxt_clk_div *clk_div) |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1652 | { |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1653 | struct dpll best_clock; |
| 1654 | |
| 1655 | /* Calculate HDMI div */ |
| 1656 | /* |
| 1657 | * FIXME: tie the following calculation into |
| 1658 | * i9xx_crtc_compute_clock |
| 1659 | */ |
| 1660 | if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { |
| 1661 | DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", |
| 1662 | clock, pipe_name(intel_crtc->pipe)); |
| 1663 | return false; |
| 1664 | } |
| 1665 | |
| 1666 | clk_div->p1 = best_clock.p1; |
| 1667 | clk_div->p2 = best_clock.p2; |
| 1668 | WARN_ON(best_clock.m1 != 2); |
| 1669 | clk_div->n = best_clock.n; |
| 1670 | clk_div->m2_int = best_clock.m2 >> 22; |
| 1671 | clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1); |
| 1672 | clk_div->m2_frac_en = clk_div->m2_frac != 0; |
| 1673 | |
| 1674 | clk_div->vco = best_clock.vco; |
| 1675 | |
| 1676 | return true; |
| 1677 | } |
| 1678 | |
| 1679 | static void bxt_ddi_dp_pll_dividers(int clock, struct bxt_clk_div *clk_div) |
| 1680 | { |
| 1681 | int i; |
| 1682 | |
| 1683 | *clk_div = bxt_dp_clk_val[0]; |
| 1684 | for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { |
| 1685 | if (bxt_dp_clk_val[i].clock == clock) { |
| 1686 | *clk_div = bxt_dp_clk_val[i]; |
| 1687 | break; |
| 1688 | } |
| 1689 | } |
| 1690 | |
| 1691 | clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2; |
| 1692 | } |
| 1693 | |
| 1694 | static bool bxt_ddi_set_dpll_hw_state(int clock, |
| 1695 | struct bxt_clk_div *clk_div, |
| 1696 | struct intel_dpll_hw_state *dpll_hw_state) |
| 1697 | { |
| 1698 | int vco = clk_div->vco; |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1699 | uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; |
| 1700 | uint32_t lanestagger; |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1701 | |
| 1702 | if (vco >= 6200000 && vco <= 6700000) { |
| 1703 | prop_coef = 4; |
| 1704 | int_coef = 9; |
| 1705 | gain_ctl = 3; |
| 1706 | targ_cnt = 8; |
| 1707 | } else if ((vco > 5400000 && vco < 6200000) || |
| 1708 | (vco >= 4800000 && vco < 5400000)) { |
| 1709 | prop_coef = 5; |
| 1710 | int_coef = 11; |
| 1711 | gain_ctl = 3; |
| 1712 | targ_cnt = 9; |
| 1713 | } else if (vco == 5400000) { |
| 1714 | prop_coef = 3; |
| 1715 | int_coef = 8; |
| 1716 | gain_ctl = 1; |
| 1717 | targ_cnt = 9; |
| 1718 | } else { |
| 1719 | DRM_ERROR("Invalid VCO\n"); |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1720 | return false; |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1721 | } |
| 1722 | |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1723 | if (clock > 270000) |
| 1724 | lanestagger = 0x18; |
| 1725 | else if (clock > 135000) |
| 1726 | lanestagger = 0x0d; |
| 1727 | else if (clock > 67000) |
| 1728 | lanestagger = 0x07; |
| 1729 | else if (clock > 33000) |
| 1730 | lanestagger = 0x04; |
| 1731 | else |
| 1732 | lanestagger = 0x02; |
| 1733 | |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1734 | dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2); |
| 1735 | dpll_hw_state->pll0 = clk_div->m2_int; |
| 1736 | dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n); |
| 1737 | dpll_hw_state->pll2 = clk_div->m2_frac; |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1738 | |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1739 | if (clk_div->m2_frac_en) |
| 1740 | dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE; |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1741 | |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1742 | dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef); |
| 1743 | dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl); |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1744 | |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1745 | dpll_hw_state->pll8 = targ_cnt; |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1746 | |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1747 | dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT; |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1748 | |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1749 | dpll_hw_state->pll10 = |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1750 | PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) |
| 1751 | | PORT_PLL_DCO_AMP_OVR_EN_H; |
| 1752 | |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1753 | dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE; |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1754 | |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1755 | dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger; |
| 1756 | |
| 1757 | return true; |
| 1758 | } |
| 1759 | |
| 1760 | bool bxt_ddi_dp_set_dpll_hw_state(int clock, |
| 1761 | struct intel_dpll_hw_state *dpll_hw_state) |
| 1762 | { |
| 1763 | struct bxt_clk_div clk_div = {0}; |
| 1764 | |
| 1765 | bxt_ddi_dp_pll_dividers(clock, &clk_div); |
| 1766 | |
| 1767 | return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state); |
| 1768 | } |
| 1769 | |
Imre Deak | a04139c | 2016-09-26 17:54:31 +0300 | [diff] [blame] | 1770 | static bool |
| 1771 | bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc *intel_crtc, |
| 1772 | struct intel_crtc_state *crtc_state, int clock, |
| 1773 | struct intel_dpll_hw_state *dpll_hw_state) |
| 1774 | { |
| 1775 | struct bxt_clk_div clk_div = { }; |
| 1776 | |
| 1777 | bxt_ddi_hdmi_pll_dividers(intel_crtc, crtc_state, clock, &clk_div); |
| 1778 | |
| 1779 | return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state); |
| 1780 | } |
| 1781 | |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1782 | static struct intel_shared_dpll * |
| 1783 | bxt_get_dpll(struct intel_crtc *crtc, |
| 1784 | struct intel_crtc_state *crtc_state, |
| 1785 | struct intel_encoder *encoder) |
| 1786 | { |
Imre Deak | a04139c | 2016-09-26 17:54:31 +0300 | [diff] [blame] | 1787 | struct intel_dpll_hw_state dpll_hw_state = { }; |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1788 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 1789 | struct intel_digital_port *intel_dig_port; |
| 1790 | struct intel_shared_dpll *pll; |
| 1791 | int i, clock = crtc_state->port_clock; |
| 1792 | |
Imre Deak | a04139c | 2016-09-26 17:54:31 +0300 | [diff] [blame] | 1793 | if (encoder->type == INTEL_OUTPUT_HDMI && |
| 1794 | !bxt_ddi_hdmi_set_dpll_hw_state(crtc, crtc_state, clock, |
| 1795 | &dpll_hw_state)) |
Jani Nikula | bcbfcc3 | 2016-09-15 16:28:53 +0300 | [diff] [blame] | 1796 | return NULL; |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1797 | |
| 1798 | if ((encoder->type == INTEL_OUTPUT_DP || |
| 1799 | encoder->type == INTEL_OUTPUT_EDP) && |
| 1800 | !bxt_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state)) |
Jani Nikula | bcbfcc3 | 2016-09-15 16:28:53 +0300 | [diff] [blame] | 1801 | return NULL; |
Durgadoss R | a277ca7 | 2016-09-01 15:08:09 -0700 | [diff] [blame] | 1802 | |
| 1803 | memset(&crtc_state->dpll_hw_state, 0, |
| 1804 | sizeof(crtc_state->dpll_hw_state)); |
| 1805 | |
| 1806 | crtc_state->dpll_hw_state = dpll_hw_state; |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1807 | |
Maarten Lankhorst | a79e8cc | 2016-08-09 17:04:00 +0200 | [diff] [blame] | 1808 | if (encoder->type == INTEL_OUTPUT_DP_MST) { |
| 1809 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); |
| 1810 | |
| 1811 | intel_dig_port = intel_mst->primary; |
| 1812 | } else |
| 1813 | intel_dig_port = enc_to_dig_port(&encoder->base); |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1814 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1815 | /* 1:1 mapping between ports and PLLs */ |
Ander Conselvan de Oliveira | 34177c2 | 2016-03-08 17:46:25 +0200 | [diff] [blame] | 1816 | i = (enum intel_dpll_id) intel_dig_port->port; |
| 1817 | pll = intel_get_shared_dpll_by_id(dev_priv, i); |
| 1818 | |
Ville Syrjälä | 78108b7 | 2016-05-27 20:59:19 +0300 | [diff] [blame] | 1819 | DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n", |
| 1820 | crtc->base.base.id, crtc->base.name, pll->name); |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1821 | |
| 1822 | intel_reference_shared_dpll(pll, crtc_state); |
| 1823 | |
| 1824 | return pll; |
| 1825 | } |
| 1826 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1827 | static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = { |
| 1828 | .enable = bxt_ddi_pll_enable, |
| 1829 | .disable = bxt_ddi_pll_disable, |
| 1830 | .get_hw_state = bxt_ddi_pll_get_hw_state, |
| 1831 | }; |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1832 | |
| 1833 | static void intel_ddi_pll_init(struct drm_device *dev) |
| 1834 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1835 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1836 | |
Ville Syrjälä | 9f7eb31 | 2016-05-13 23:41:29 +0300 | [diff] [blame] | 1837 | if (INTEL_GEN(dev_priv) < 9) { |
| 1838 | uint32_t val = I915_READ(LCPLL_CTL); |
Ville Syrjälä | b204535 | 2016-05-13 23:41:27 +0300 | [diff] [blame] | 1839 | |
Ander Conselvan de Oliveira | 55be2f0 | 2016-03-08 17:46:16 +0200 | [diff] [blame] | 1840 | /* |
| 1841 | * The LCPLL register should be turned on by the BIOS. For now |
| 1842 | * let's just check its state and print errors in case |
| 1843 | * something is wrong. Don't even try to turn it on. |
| 1844 | */ |
| 1845 | |
| 1846 | if (val & LCPLL_CD_SOURCE_FCLK) |
| 1847 | DRM_ERROR("CDCLK source is not LCPLL\n"); |
| 1848 | |
| 1849 | if (val & LCPLL_PLL_DISABLE) |
| 1850 | DRM_ERROR("LCPLL is disabled\n"); |
| 1851 | } |
| 1852 | } |
| 1853 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1854 | struct dpll_info { |
| 1855 | const char *name; |
| 1856 | const int id; |
| 1857 | const struct intel_shared_dpll_funcs *funcs; |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 1858 | uint32_t flags; |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1859 | }; |
| 1860 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1861 | struct intel_dpll_mgr { |
| 1862 | const struct dpll_info *dpll_info; |
| 1863 | |
| 1864 | struct intel_shared_dpll *(*get_dpll)(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 1865 | struct intel_crtc_state *crtc_state, |
| 1866 | struct intel_encoder *encoder); |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1867 | }; |
| 1868 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1869 | static const struct dpll_info pch_plls[] = { |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 1870 | { "PCH DPLL A", DPLL_ID_PCH_PLL_A, &ibx_pch_dpll_funcs, 0 }, |
| 1871 | { "PCH DPLL B", DPLL_ID_PCH_PLL_B, &ibx_pch_dpll_funcs, 0 }, |
| 1872 | { NULL, -1, NULL, 0 }, |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1873 | }; |
| 1874 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1875 | static const struct intel_dpll_mgr pch_pll_mgr = { |
| 1876 | .dpll_info = pch_plls, |
| 1877 | .get_dpll = ibx_get_dpll, |
| 1878 | }; |
| 1879 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1880 | static const struct dpll_info hsw_plls[] = { |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 1881 | { "WRPLL 1", DPLL_ID_WRPLL1, &hsw_ddi_wrpll_funcs, 0 }, |
| 1882 | { "WRPLL 2", DPLL_ID_WRPLL2, &hsw_ddi_wrpll_funcs, 0 }, |
| 1883 | { "SPLL", DPLL_ID_SPLL, &hsw_ddi_spll_funcs, 0 }, |
| 1884 | { "LCPLL 810", DPLL_ID_LCPLL_810, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON }, |
| 1885 | { "LCPLL 1350", DPLL_ID_LCPLL_1350, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON }, |
| 1886 | { "LCPLL 2700", DPLL_ID_LCPLL_2700, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON }, |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1887 | { NULL, -1, NULL, }, |
| 1888 | }; |
| 1889 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1890 | static const struct intel_dpll_mgr hsw_pll_mgr = { |
| 1891 | .dpll_info = hsw_plls, |
| 1892 | .get_dpll = hsw_get_dpll, |
| 1893 | }; |
| 1894 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1895 | static const struct dpll_info skl_plls[] = { |
Ander Conselvan de Oliveira | a3c988e | 2016-03-08 17:46:27 +0200 | [diff] [blame] | 1896 | { "DPLL 0", DPLL_ID_SKL_DPLL0, &skl_ddi_dpll0_funcs, INTEL_DPLL_ALWAYS_ON }, |
Ville Syrjälä | d5aab9d | 2016-05-11 22:04:33 +0300 | [diff] [blame] | 1897 | { "DPLL 1", DPLL_ID_SKL_DPLL1, &skl_ddi_pll_funcs, 0 }, |
| 1898 | { "DPLL 2", DPLL_ID_SKL_DPLL2, &skl_ddi_pll_funcs, 0 }, |
| 1899 | { "DPLL 3", DPLL_ID_SKL_DPLL3, &skl_ddi_pll_funcs, 0 }, |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1900 | { NULL, -1, NULL, }, |
| 1901 | }; |
| 1902 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1903 | static const struct intel_dpll_mgr skl_pll_mgr = { |
| 1904 | .dpll_info = skl_plls, |
| 1905 | .get_dpll = skl_get_dpll, |
| 1906 | }; |
| 1907 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1908 | static const struct dpll_info bxt_plls[] = { |
Imre Deak | 08250c4 | 2016-03-14 19:55:34 +0200 | [diff] [blame] | 1909 | { "PORT PLL A", DPLL_ID_SKL_DPLL0, &bxt_ddi_pll_funcs, 0 }, |
| 1910 | { "PORT PLL B", DPLL_ID_SKL_DPLL1, &bxt_ddi_pll_funcs, 0 }, |
| 1911 | { "PORT PLL C", DPLL_ID_SKL_DPLL2, &bxt_ddi_pll_funcs, 0 }, |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1912 | { NULL, -1, NULL, }, |
| 1913 | }; |
| 1914 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1915 | static const struct intel_dpll_mgr bxt_pll_mgr = { |
| 1916 | .dpll_info = bxt_plls, |
| 1917 | .get_dpll = bxt_get_dpll, |
| 1918 | }; |
| 1919 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame^] | 1920 | /** |
| 1921 | * intel_shared_dpll_init - Initialize shared DPLLs |
| 1922 | * @dev: drm device |
| 1923 | * |
| 1924 | * Initialize shared DPLLs for @dev. |
| 1925 | */ |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 1926 | void intel_shared_dpll_init(struct drm_device *dev) |
| 1927 | { |
Chris Wilson | fac5e23 | 2016-07-04 11:34:36 +0100 | [diff] [blame] | 1928 | struct drm_i915_private *dev_priv = to_i915(dev); |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1929 | const struct intel_dpll_mgr *dpll_mgr = NULL; |
| 1930 | const struct dpll_info *dpll_info; |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1931 | int i; |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 1932 | |
Tvrtko Ursulin | 0853723 | 2016-10-13 11:03:02 +0100 | [diff] [blame] | 1933 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1934 | dpll_mgr = &skl_pll_mgr; |
Ander Conselvan de Oliveira | cc3f90f | 2016-12-02 10:23:49 +0200 | [diff] [blame] | 1935 | else if (IS_GEN9_LP(dev_priv)) |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1936 | dpll_mgr = &bxt_pll_mgr; |
Tvrtko Ursulin | 4f8036a | 2016-10-13 11:02:52 +0100 | [diff] [blame] | 1937 | else if (HAS_DDI(dev_priv)) |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1938 | dpll_mgr = &hsw_pll_mgr; |
Tvrtko Ursulin | 6e26695 | 2016-10-13 11:02:53 +0100 | [diff] [blame] | 1939 | else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1940 | dpll_mgr = &pch_pll_mgr; |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1941 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1942 | if (!dpll_mgr) { |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 1943 | dev_priv->num_shared_dpll = 0; |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1944 | return; |
| 1945 | } |
| 1946 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1947 | dpll_info = dpll_mgr->dpll_info; |
| 1948 | |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1949 | for (i = 0; dpll_info[i].id >= 0; i++) { |
| 1950 | WARN_ON(i != dpll_info[i].id); |
| 1951 | |
| 1952 | dev_priv->shared_dplls[i].id = dpll_info[i].id; |
| 1953 | dev_priv->shared_dplls[i].name = dpll_info[i].name; |
| 1954 | dev_priv->shared_dplls[i].funcs = *dpll_info[i].funcs; |
Ander Conselvan de Oliveira | 9d16da6 | 2016-03-08 17:46:26 +0200 | [diff] [blame] | 1955 | dev_priv->shared_dplls[i].flags = dpll_info[i].flags; |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1956 | } |
| 1957 | |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1958 | dev_priv->dpll_mgr = dpll_mgr; |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1959 | dev_priv->num_shared_dpll = i; |
Maarten Lankhorst | fbf6d87 | 2016-03-23 14:51:12 +0100 | [diff] [blame] | 1960 | mutex_init(&dev_priv->dpll_lock); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 1961 | |
| 1962 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1963 | |
| 1964 | /* FIXME: Move this to a more suitable place */ |
Tvrtko Ursulin | 4f8036a | 2016-10-13 11:02:52 +0100 | [diff] [blame] | 1965 | if (HAS_DDI(dev_priv)) |
Ander Conselvan de Oliveira | 2edd644 | 2016-03-08 17:46:21 +0200 | [diff] [blame] | 1966 | intel_ddi_pll_init(dev); |
Ander Conselvan de Oliveira | 7abd4b3 | 2016-03-08 17:46:15 +0200 | [diff] [blame] | 1967 | } |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1968 | |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame^] | 1969 | /** |
| 1970 | * intel_get_shared_dpll - get a shared DPLL for CRTC and encoder combination |
| 1971 | * @crtc: CRTC |
| 1972 | * @crtc_state: atomic state for @crtc |
| 1973 | * @encoder: encoder |
| 1974 | * |
| 1975 | * Find an appropriate DPLL for the given CRTC and encoder combination. A |
| 1976 | * reference from the @crtc to the returned pll is registered in the atomic |
| 1977 | * state. That configuration is made effective by calling |
| 1978 | * intel_shared_dpll_swap_state(). The reference should be released by calling |
| 1979 | * intel_release_shared_dpll(). |
| 1980 | * |
| 1981 | * Returns: |
| 1982 | * A shared DPLL to be used by @crtc and @encoder with the given @crtc_state. |
| 1983 | */ |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1984 | struct intel_shared_dpll * |
| 1985 | intel_get_shared_dpll(struct intel_crtc *crtc, |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 1986 | struct intel_crtc_state *crtc_state, |
| 1987 | struct intel_encoder *encoder) |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1988 | { |
| 1989 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 1990 | const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr; |
| 1991 | |
| 1992 | if (WARN_ON(!dpll_mgr)) |
| 1993 | return NULL; |
| 1994 | |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 1995 | return dpll_mgr->get_dpll(crtc, crtc_state, encoder); |
Ander Conselvan de Oliveira | f9476a6 | 2016-03-08 17:46:22 +0200 | [diff] [blame] | 1996 | } |
Ander Conselvan de Oliveira | a1c414e | 2016-12-29 17:22:07 +0200 | [diff] [blame] | 1997 | |
| 1998 | /** |
| 1999 | * intel_release_shared_dpll - end use of DPLL by CRTC in atomic state |
| 2000 | * @dpll: dpll in use by @crtc |
| 2001 | * @crtc: crtc |
| 2002 | * @state: atomic state |
| 2003 | * |
Ander Conselvan de Oliveira | 294591c | 2016-12-29 17:22:11 +0200 | [diff] [blame^] | 2004 | * This function releases the reference from @crtc to @dpll from the |
| 2005 | * atomic @state. The new configuration is made effective by calling |
| 2006 | * intel_shared_dpll_swap_state(). |
Ander Conselvan de Oliveira | a1c414e | 2016-12-29 17:22:07 +0200 | [diff] [blame] | 2007 | */ |
| 2008 | void intel_release_shared_dpll(struct intel_shared_dpll *dpll, |
| 2009 | struct intel_crtc *crtc, |
| 2010 | struct drm_atomic_state *state) |
| 2011 | { |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 2012 | struct intel_shared_dpll_state *shared_dpll_state; |
Ander Conselvan de Oliveira | a1c414e | 2016-12-29 17:22:07 +0200 | [diff] [blame] | 2013 | |
Ander Conselvan de Oliveira | 2c42e53 | 2016-12-29 17:22:09 +0200 | [diff] [blame] | 2014 | shared_dpll_state = intel_atomic_get_shared_dpll_state(state); |
| 2015 | shared_dpll_state[dpll->id].crtc_mask &= ~(1 << crtc->pipe); |
Ander Conselvan de Oliveira | a1c414e | 2016-12-29 17:22:07 +0200 | [diff] [blame] | 2016 | } |