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gerrit-public.fairphone.software / kernel / msm-4.19 / 29aa37cddfb9b721013ff28608200d73a9426368 / . / sound / soc / codecs / wm8962.c
blob: 5522d2566c6742d5ee19f91b4358b30f51276b62 [file] [log] [blame]
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1/*
2 * wm8962.c -- WM8962 ALSA SoC Audio driver
3 *
Mark Brown656baae2012-05-23 12:39:07 +0100[diff] [blame]4 * Copyright 2010-2 Wolfson Microelectronics plc
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]20#include <linux/gpio.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]21#include <linux/i2c.h>
22#include <linux/input.h>
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]23#include <linux/pm_runtime.h>
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]24#include <linux/regmap.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]25#include <linux/regulator/consumer.h>
26#include <linux/slab.h>
27#include <linux/workqueue.h>
28#include <sound/core.h>
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]29#include <sound/jack.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/soc.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]33#include <sound/initval.h>
34#include <sound/tlv.h>
35#include <sound/wm8962.h>
Mark Brown2bbb5d62010-12-05 12:50:12 +0000[diff] [blame]36#include <trace/events/asoc.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]37
38#include "wm8962.h"
39
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]40#define WM8962_NUM_SUPPLIES 8
41static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
42 "DCVDD",
43 "DBVDD",
44 "AVDD",
45 "CPVDD",
46 "MICVDD",
47 "PLLVDD",
48 "SPKVDD1",
49 "SPKVDD2",
50};
51
52/* codec private data */
53struct wm8962_priv {
Nicolin Chene75a52c2013-06-06 19:38:45 +0800[diff] [blame]54 struct wm8962_pdata pdata;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]55 struct regmap *regmap;
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]56 struct snd_soc_codec *codec;
57
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]58 int sysclk;
59 int sysclk_rate;
60
61 int bclk; /* Desired BCLK */
62 int lrclk;
63
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]64 struct completion fll_lock;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]65 int fll_src;
66 int fll_fref;
67 int fll_fout;
68
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]69 u16 dsp2_ena;
70
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]71 struct delayed_work mic_work;
72 struct snd_soc_jack *jack;
73
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]74 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
75 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
76
Fabio Estevamc3e84942013-11-20 15:37:41 -0200[diff] [blame]77#if IS_ENABLED(CONFIG_INPUT)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]78 struct input_dev *beep;
79 struct work_struct beep_work;
80 int beep_rate;
81#endif
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]82
83#ifdef CONFIG_GPIOLIB
84 struct gpio_chip gpio_chip;
85#endif
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]86
87 int irq;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]88};
89
90/* We can't use the same notifier block for more than one supply and
91 * there's no way I can see to get from a callback to the caller
92 * except container_of().
93 */
94#define WM8962_REGULATOR_EVENT(n) \
95static int wm8962_regulator_event_##n(struct notifier_block *nb, \
96 unsigned long event, void *data) \
97{ \
98 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
99 disable_nb[n]); \
100 if (event & REGULATOR_EVENT_DISABLE) { \
Mark Brown5539a102012-01-25 21:10:21 +0000[diff] [blame]101 regcache_mark_dirty(wm8962->regmap); \
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]102 } \
103 return 0; \
104}
105
106WM8962_REGULATOR_EVENT(0)
107WM8962_REGULATOR_EVENT(1)
108WM8962_REGULATOR_EVENT(2)
109WM8962_REGULATOR_EVENT(3)
110WM8962_REGULATOR_EVENT(4)
111WM8962_REGULATOR_EVENT(5)
112WM8962_REGULATOR_EVENT(6)
113WM8962_REGULATOR_EVENT(7)
114
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]115static struct reg_default wm8962_reg[] = {
116 { 0, 0x009F }, /* R0 - Left Input volume */
117 { 1, 0x049F }, /* R1 - Right Input volume */
118 { 2, 0x0000 }, /* R2 - HPOUTL volume */
119 { 3, 0x0000 }, /* R3 - HPOUTR volume */
Mark Brownba106ce2012-03-06 00:25:28 +0000[diff] [blame]120
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]121 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */
122 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */
123 { 7, 0x000A }, /* R7 - Audio Interface 0 */
Mark Brownba106ce2012-03-06 00:25:28 +0000[diff] [blame]124
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]125 { 9, 0x0300 }, /* R9 - Audio Interface 1 */
126 { 10, 0x00C0 }, /* R10 - Left DAC volume */
127 { 11, 0x00C0 }, /* R11 - Right DAC volume */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]128
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]129 { 14, 0x0040 }, /* R14 - Audio Interface 2 */
130 { 15, 0x6243 }, /* R15 - Software Reset */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]131
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]132 { 17, 0x007B }, /* R17 - ALC1 */
Mark Brownba106ce2012-03-06 00:25:28 +0000[diff] [blame]133
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]134 { 19, 0x1C32 }, /* R19 - ALC3 */
135 { 20, 0x3200 }, /* R20 - Noise Gate */
136 { 21, 0x00C0 }, /* R21 - Left ADC volume */
137 { 22, 0x00C0 }, /* R22 - Right ADC volume */
138 { 23, 0x0160 }, /* R23 - Additional control(1) */
139 { 24, 0x0000 }, /* R24 - Additional control(2) */
140 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
141 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
142 { 27, 0x0010 }, /* R27 - Additional Control (3) */
143 { 28, 0x0000 }, /* R28 - Anti-pop */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]144
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]145 { 30, 0x005E }, /* R30 - Clocking 3 */
146 { 31, 0x0000 }, /* R31 - Input mixer control (1) */
147 { 32, 0x0145 }, /* R32 - Left input mixer volume */
148 { 33, 0x0145 }, /* R33 - Right input mixer volume */
149 { 34, 0x0009 }, /* R34 - Input mixer control (2) */
150 { 35, 0x0003 }, /* R35 - Input bias control */
151 { 37, 0x0008 }, /* R37 - Left input PGA control */
152 { 38, 0x0008 }, /* R38 - Right input PGA control */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]153
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]154 { 40, 0x0000 }, /* R40 - SPKOUTL volume */
155 { 41, 0x0000 }, /* R41 - SPKOUTR volume */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]156
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]157 { 51, 0x0003 }, /* R51 - Class D Control 2 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]158
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]159 { 56, 0x0506 }, /* R56 - Clocking 4 */
160 { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */
161 { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]162
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]163 { 60, 0x0300 }, /* R60 - DC Servo 0 */
164 { 61, 0x0300 }, /* R61 - DC Servo 1 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]165
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]166 { 64, 0x0810 }, /* R64 - DC Servo 4 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]167
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]168 { 68, 0x001B }, /* R68 - Analogue PGA Bias */
169 { 69, 0x0000 }, /* R69 - Analogue HP 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]170
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]171 { 71, 0x01FB }, /* R71 - Analogue HP 2 */
172 { 72, 0x0000 }, /* R72 - Charge Pump 1 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]173
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]174 { 82, 0x0004 }, /* R82 - Charge Pump B */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]175
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]176 { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]177
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]178 { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]179
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]180 { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */
181 { 94, 0x0000 }, /* R94 - Control Interface */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]182
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]183 { 99, 0x0000 }, /* R99 - Mixer Enables */
184 { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */
185 { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */
186 { 102, 0x013F }, /* R102 - Headphone Mixer (3) */
187 { 103, 0x013F }, /* R103 - Headphone Mixer (4) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]188
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]189 { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */
190 { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */
191 { 107, 0x013F }, /* R107 - Speaker Mixer (3) */
192 { 108, 0x013F }, /* R108 - Speaker Mixer (4) */
193 { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */
194 { 110, 0x0002 }, /* R110 - Beep Generator (1) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]195
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]196 { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */
197 { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]198
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]199 { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]200
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]201 { 124, 0x0011 }, /* R124 - Analogue Clocking1 */
202 { 125, 0x004B }, /* R125 - Analogue Clocking2 */
203 { 126, 0x000D }, /* R126 - Analogue Clocking3 */
204 { 127, 0x0000 }, /* R127 - PLL Software Reset */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]205
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]206 { 131, 0x0000 }, /* R131 - PLL 4 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]207
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]208 { 136, 0x0067 }, /* R136 - PLL 9 */
209 { 137, 0x001C }, /* R137 - PLL 10 */
210 { 138, 0x0071 }, /* R138 - PLL 11 */
211 { 139, 0x00C7 }, /* R139 - PLL 12 */
212 { 140, 0x0067 }, /* R140 - PLL 13 */
213 { 141, 0x0048 }, /* R141 - PLL 14 */
214 { 142, 0x0022 }, /* R142 - PLL 15 */
215 { 143, 0x0097 }, /* R143 - PLL 16 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]216
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]217 { 155, 0x000C }, /* R155 - FLL Control (1) */
218 { 156, 0x0039 }, /* R156 - FLL Control (2) */
219 { 157, 0x0180 }, /* R157 - FLL Control (3) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]220
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]221 { 159, 0x0032 }, /* R159 - FLL Control (5) */
222 { 160, 0x0018 }, /* R160 - FLL Control (6) */
223 { 161, 0x007D }, /* R161 - FLL Control (7) */
224 { 162, 0x0008 }, /* R162 - FLL Control (8) */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]225
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]226 { 252, 0x0005 }, /* R252 - General test 1 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]227
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]228 { 256, 0x0000 }, /* R256 - DF1 */
229 { 257, 0x0000 }, /* R257 - DF2 */
230 { 258, 0x0000 }, /* R258 - DF3 */
231 { 259, 0x0000 }, /* R259 - DF4 */
232 { 260, 0x0000 }, /* R260 - DF5 */
233 { 261, 0x0000 }, /* R261 - DF6 */
234 { 262, 0x0000 }, /* R262 - DF7 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]235
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]236 { 264, 0x0000 }, /* R264 - LHPF1 */
237 { 265, 0x0000 }, /* R265 - LHPF2 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]238
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]239 { 268, 0x0000 }, /* R268 - THREED1 */
240 { 269, 0x0000 }, /* R269 - THREED2 */
241 { 270, 0x0000 }, /* R270 - THREED3 */
242 { 271, 0x0000 }, /* R271 - THREED4 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]243
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]244 { 276, 0x000C }, /* R276 - DRC 1 */
245 { 277, 0x0925 }, /* R277 - DRC 2 */
246 { 278, 0x0000 }, /* R278 - DRC 3 */
247 { 279, 0x0000 }, /* R279 - DRC 4 */
248 { 280, 0x0000 }, /* R280 - DRC 5 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]249
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]250 { 285, 0x0000 }, /* R285 - Tloopback */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]251
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]252 { 335, 0x0004 }, /* R335 - EQ1 */
253 { 336, 0x6318 }, /* R336 - EQ2 */
254 { 337, 0x6300 }, /* R337 - EQ3 */
255 { 338, 0x0FCA }, /* R338 - EQ4 */
256 { 339, 0x0400 }, /* R339 - EQ5 */
257 { 340, 0x00D8 }, /* R340 - EQ6 */
258 { 341, 0x1EB5 }, /* R341 - EQ7 */
259 { 342, 0xF145 }, /* R342 - EQ8 */
260 { 343, 0x0B75 }, /* R343 - EQ9 */
261 { 344, 0x01C5 }, /* R344 - EQ10 */
262 { 345, 0x1C58 }, /* R345 - EQ11 */
263 { 346, 0xF373 }, /* R346 - EQ12 */
264 { 347, 0x0A54 }, /* R347 - EQ13 */
265 { 348, 0x0558 }, /* R348 - EQ14 */
266 { 349, 0x168E }, /* R349 - EQ15 */
267 { 350, 0xF829 }, /* R350 - EQ16 */
268 { 351, 0x07AD }, /* R351 - EQ17 */
269 { 352, 0x1103 }, /* R352 - EQ18 */
270 { 353, 0x0564 }, /* R353 - EQ19 */
271 { 354, 0x0559 }, /* R354 - EQ20 */
272 { 355, 0x4000 }, /* R355 - EQ21 */
273 { 356, 0x6318 }, /* R356 - EQ22 */
274 { 357, 0x6300 }, /* R357 - EQ23 */
275 { 358, 0x0FCA }, /* R358 - EQ24 */
276 { 359, 0x0400 }, /* R359 - EQ25 */
277 { 360, 0x00D8 }, /* R360 - EQ26 */
278 { 361, 0x1EB5 }, /* R361 - EQ27 */
279 { 362, 0xF145 }, /* R362 - EQ28 */
280 { 363, 0x0B75 }, /* R363 - EQ29 */
281 { 364, 0x01C5 }, /* R364 - EQ30 */
282 { 365, 0x1C58 }, /* R365 - EQ31 */
283 { 366, 0xF373 }, /* R366 - EQ32 */
284 { 367, 0x0A54 }, /* R367 - EQ33 */
285 { 368, 0x0558 }, /* R368 - EQ34 */
286 { 369, 0x168E }, /* R369 - EQ35 */
287 { 370, 0xF829 }, /* R370 - EQ36 */
288 { 371, 0x07AD }, /* R371 - EQ37 */
289 { 372, 0x1103 }, /* R372 - EQ38 */
290 { 373, 0x0564 }, /* R373 - EQ39 */
291 { 374, 0x0559 }, /* R374 - EQ40 */
292 { 375, 0x4000 }, /* R375 - EQ41 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]293
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]294 { 513, 0x0000 }, /* R513 - GPIO 2 */
295 { 514, 0x0000 }, /* R514 - GPIO 3 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]296
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]297 { 516, 0x8100 }, /* R516 - GPIO 5 */
298 { 517, 0x8100 }, /* R517 - GPIO 6 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]299
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]300 { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */
301 { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]302
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]303 { 576, 0x0000 }, /* R576 - Interrupt Control */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]304
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]305 { 584, 0x002D }, /* R584 - IRQ Debounce */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]306
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]307 { 586, 0x0000 }, /* R586 - MICINT Source Pol */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]308
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]309 { 768, 0x1C00 }, /* R768 - DSP2 Power Management */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]310
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]311 { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]312
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]313 { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */
314 { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */
315 { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]316
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]317 { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */
318 { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]319
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]320 { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */
321 { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]322
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]323 { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */
324 { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]325
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]326 { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]327
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]328 { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */
329 { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */
330 { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
331 { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
332 { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */
333 { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]334
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]335 { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */
336 { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */
337 { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */
338 { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */
339 { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */
340 { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */
341 { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */
342 { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */
343 { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */
344 { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */
345 { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */
346 { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */
347 { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */
348 { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */
349 { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */
350 { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */
351 { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */
352 { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */
353 { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */
354 { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */
355 { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */
356 { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */
357 { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */
358 { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */
359 { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */
360 { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */
361 { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */
362 { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */
363 { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */
364 { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]365
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]366 { 17048, 0x0083 }, /* R17408 - HPF_C_1 */
367 { 17049, 0x98AD }, /* R17409 - HPF_C_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]368
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]369 { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */
370 { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */
371 { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */
372 { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */
373 { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */
374 { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */
375 { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */
376 { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */
377 { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */
378 { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */
379 { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */
380 { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */
381 { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */
382 { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */
383 { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */
384 { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */
385 { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */
386 { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */
387 { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */
388 { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */
389 { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */
390 { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */
391 { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */
392 { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */
393 { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */
394 { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */
395 { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */
396 { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */
397 { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */
398 { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */
399 { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */
400 { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */
401 { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */
402 { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */
403 { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */
404 { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */
405 { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */
406 { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */
407 { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */
408 { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */
409 { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */
410 { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */
411 { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */
412 { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */
413 { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */
414 { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */
415 { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */
416 { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */
417 { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */
418 { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */
419 { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */
420 { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */
421 { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */
422 { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */
423 { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */
424 { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */
425 { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */
426 { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */
427 { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */
428 { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */
429 { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */
430 { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */
431 { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */
432 { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]433
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]434 { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */
435 { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */
436 { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */
437 { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]438
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]439 { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */
440 { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */
441 { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */
442 { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */
443 { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */
444 { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */
445 { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */
446 { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */
447 { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */
448 { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */
449 { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */
450 { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */
451 { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */
452 { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */
453 { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */
454 { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */
455 { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */
456 { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */
457 { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */
458 { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */
459 { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */
460 { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */
461 { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */
462 { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */
463 { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */
464 { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */
465 { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */
466 { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */
467 { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */
468 { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */
469 { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */
470 { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */
471 { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */
472 { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */
473 { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */
474 { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */
475 { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */
476 { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */
477 { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */
478 { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */
479 { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */
480 { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */
481 { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */
482 { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */
483 { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */
484 { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */
485 { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */
486 { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */
487 { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */
488 { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */
489 { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */
490 { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */
491 { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */
492 { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */
493 { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */
494 { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */
495 { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */
496 { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */
497 { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */
498 { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */
499 { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */
500 { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */
501 { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */
502 { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]503
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]504 { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */
505 { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */
506 { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */
507 { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */
508 { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */
509 { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */
510 { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */
511 { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */
512 { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */
513 { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */
514 { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */
515 { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */
516 { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */
517 { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */
518 { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */
519 { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */
520 { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */
521 { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */
522 { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */
523 { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */
524 { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */
525 { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */
526 { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */
527 { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */
528 { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */
529 { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */
530 { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */
531 { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */
532 { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */
533 { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */
534 { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */
535 { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */
536 { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */
537 { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */
538 { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */
539 { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */
540 { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */
541 { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */
542 { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */
543 { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */
544 { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */
545 { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */
546 { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */
547 { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */
548 { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */
549 { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */
550 { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */
551 { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */
552 { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */
553 { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */
554 { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */
555 { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */
556 { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */
557 { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */
558 { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */
559 { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */
560 { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */
561 { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */
562 { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */
563 { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */
564 { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */
565 { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */
566 { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */
567 { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]568
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]569 { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */
570 { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */
571 { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */
572 { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]573
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]574 { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */
575 { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */
576 { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */
577 { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */
578 { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */
579 { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */
580 { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */
581 { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */
582 { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */
583 { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */
584 { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */
585 { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */
586 { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */
587 { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */
588 { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */
589 { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */
590 { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */
591 { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */
592 { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */
593 { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */
594 { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */
595 { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */
596 { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */
597 { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */
598 { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */
599 { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */
600 { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */
601 { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */
602 { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */
603 { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */
604 { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */
605 { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */
606 { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */
607 { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */
608 { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */
609 { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */
610 { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */
611 { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */
612 { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */
613 { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */
614 { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */
615 { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */
616 { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */
617 { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */
618 { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */
619 { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */
620 { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */
621 { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */
622 { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */
623 { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */
624 { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */
625 { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */
626 { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */
627 { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */
628 { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */
629 { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */
630 { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */
631 { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */
632 { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */
633 { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */
634 { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */
635 { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */
636 { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */
637 { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]638
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]639 { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */
640 { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */
641 { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */
642 { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */
643 { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */
644 { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */
645 { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */
646 { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */
647 { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */
648 { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */
649 { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */
650 { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */
651 { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */
652 { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */
653 { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */
654 { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */
655 { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */
656 { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */
657 { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */
658 { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */
659 { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */
660 { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */
661 { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */
662 { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */
663 { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */
664 { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */
665 { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */
666 { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */
667 { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */
668 { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */
669 { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */
670 { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */
671 { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */
672 { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */
673 { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */
674 { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */
675 { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */
676 { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */
677 { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */
678 { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */
679 { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */
680 { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */
681 { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */
682 { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */
683 { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */
684 { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */
685 { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */
686 { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */
687 { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */
688 { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */
689 { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */
690 { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */
691 { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */
692 { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */
693 { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */
694 { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */
695 { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */
696 { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */
697 { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */
698 { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */
699 { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */
700 { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */
701 { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */
702 { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */
703 { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */
704 { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */
705 { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */
706 { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */
707 { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */
708 { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */
709 { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */
710 { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */
711 { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */
712 { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */
713 { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */
714 { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */
715 { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */
716 { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */
717 { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */
718 { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */
719 { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */
720 { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */
721 { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */
722 { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */
723 { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */
724 { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */
725 { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */
726 { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */
727 { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */
728 { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */
729 { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */
730 { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */
731 { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */
732 { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */
733 { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */
734 { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */
735 { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */
736 { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */
737 { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */
738 { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */
739 { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */
740 { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */
741 { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */
742 { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */
743 { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */
744 { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */
745 { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */
746 { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */
747 { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */
748 { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */
749 { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */
750 { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */
751 { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */
752 { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */
753 { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */
754 { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */
755 { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */
756 { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */
757 { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */
758 { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */
759 { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */
760 { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */
761 { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */
762 { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */
763 { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */
764 { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */
765 { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */
766 { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */
767 { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */
768 { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */
769 { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */
770 { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */
771 { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */
772 { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */
773 { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */
774 { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */
775 { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */
776 { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */
777 { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */
778 { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */
779 { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */
780 { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */
781 { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */
782 { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */
783 { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */
784 { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */
785 { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */
786 { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */
Mark Brownf57f6c042010-10-07 17:41:04 -0700[diff] [blame]787};
788
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]789static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]790{
Mark Browncef6d1d2012-01-11 20:13:19 -0800[diff] [blame]791 switch (reg) {
792 case WM8962_CLOCKING1:
793 case WM8962_CLOCKING2:
794 case WM8962_SOFTWARE_RESET:
795 case WM8962_ALC2:
796 case WM8962_THERMAL_SHUTDOWN_STATUS:
797 case WM8962_ADDITIONAL_CONTROL_4:
798 case WM8962_CLASS_D_CONTROL_1:
799 case WM8962_DC_SERVO_6:
800 case WM8962_INTERRUPT_STATUS_1:
801 case WM8962_INTERRUPT_STATUS_2:
802 case WM8962_DSP2_EXECCONTROL:
803 return true;
804 default:
805 return false;
806 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]807}
808
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]809static bool wm8962_readable_register(struct device *dev, unsigned int reg)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]810{
Mark Browncef6d1d2012-01-11 20:13:19 -0800[diff] [blame]811 switch (reg) {
812 case WM8962_LEFT_INPUT_VOLUME:
813 case WM8962_RIGHT_INPUT_VOLUME:
814 case WM8962_HPOUTL_VOLUME:
815 case WM8962_HPOUTR_VOLUME:
816 case WM8962_CLOCKING1:
817 case WM8962_ADC_DAC_CONTROL_1:
818 case WM8962_ADC_DAC_CONTROL_2:
819 case WM8962_AUDIO_INTERFACE_0:
820 case WM8962_CLOCKING2:
821 case WM8962_AUDIO_INTERFACE_1:
822 case WM8962_LEFT_DAC_VOLUME:
823 case WM8962_RIGHT_DAC_VOLUME:
824 case WM8962_AUDIO_INTERFACE_2:
825 case WM8962_SOFTWARE_RESET:
826 case WM8962_ALC1:
827 case WM8962_ALC2:
828 case WM8962_ALC3:
829 case WM8962_NOISE_GATE:
830 case WM8962_LEFT_ADC_VOLUME:
831 case WM8962_RIGHT_ADC_VOLUME:
832 case WM8962_ADDITIONAL_CONTROL_1:
833 case WM8962_ADDITIONAL_CONTROL_2:
834 case WM8962_PWR_MGMT_1:
835 case WM8962_PWR_MGMT_2:
836 case WM8962_ADDITIONAL_CONTROL_3:
837 case WM8962_ANTI_POP:
838 case WM8962_CLOCKING_3:
839 case WM8962_INPUT_MIXER_CONTROL_1:
840 case WM8962_LEFT_INPUT_MIXER_VOLUME:
841 case WM8962_RIGHT_INPUT_MIXER_VOLUME:
842 case WM8962_INPUT_MIXER_CONTROL_2:
843 case WM8962_INPUT_BIAS_CONTROL:
844 case WM8962_LEFT_INPUT_PGA_CONTROL:
845 case WM8962_RIGHT_INPUT_PGA_CONTROL:
846 case WM8962_SPKOUTL_VOLUME:
847 case WM8962_SPKOUTR_VOLUME:
848 case WM8962_THERMAL_SHUTDOWN_STATUS:
849 case WM8962_ADDITIONAL_CONTROL_4:
850 case WM8962_CLASS_D_CONTROL_1:
851 case WM8962_CLASS_D_CONTROL_2:
852 case WM8962_CLOCKING_4:
853 case WM8962_DAC_DSP_MIXING_1:
854 case WM8962_DAC_DSP_MIXING_2:
855 case WM8962_DC_SERVO_0:
856 case WM8962_DC_SERVO_1:
857 case WM8962_DC_SERVO_4:
858 case WM8962_DC_SERVO_6:
859 case WM8962_ANALOGUE_PGA_BIAS:
860 case WM8962_ANALOGUE_HP_0:
861 case WM8962_ANALOGUE_HP_2:
862 case WM8962_CHARGE_PUMP_1:
863 case WM8962_CHARGE_PUMP_B:
864 case WM8962_WRITE_SEQUENCER_CONTROL_1:
865 case WM8962_WRITE_SEQUENCER_CONTROL_2:
866 case WM8962_WRITE_SEQUENCER_CONTROL_3:
867 case WM8962_CONTROL_INTERFACE:
868 case WM8962_MIXER_ENABLES:
869 case WM8962_HEADPHONE_MIXER_1:
870 case WM8962_HEADPHONE_MIXER_2:
871 case WM8962_HEADPHONE_MIXER_3:
872 case WM8962_HEADPHONE_MIXER_4:
873 case WM8962_SPEAKER_MIXER_1:
874 case WM8962_SPEAKER_MIXER_2:
875 case WM8962_SPEAKER_MIXER_3:
876 case WM8962_SPEAKER_MIXER_4:
877 case WM8962_SPEAKER_MIXER_5:
878 case WM8962_BEEP_GENERATOR_1:
879 case WM8962_OSCILLATOR_TRIM_3:
880 case WM8962_OSCILLATOR_TRIM_4:
881 case WM8962_OSCILLATOR_TRIM_7:
882 case WM8962_ANALOGUE_CLOCKING1:
883 case WM8962_ANALOGUE_CLOCKING2:
884 case WM8962_ANALOGUE_CLOCKING3:
885 case WM8962_PLL_SOFTWARE_RESET:
886 case WM8962_PLL2:
887 case WM8962_PLL_4:
888 case WM8962_PLL_9:
889 case WM8962_PLL_10:
890 case WM8962_PLL_11:
891 case WM8962_PLL_12:
892 case WM8962_PLL_13:
893 case WM8962_PLL_14:
894 case WM8962_PLL_15:
895 case WM8962_PLL_16:
896 case WM8962_FLL_CONTROL_1:
897 case WM8962_FLL_CONTROL_2:
898 case WM8962_FLL_CONTROL_3:
899 case WM8962_FLL_CONTROL_5:
900 case WM8962_FLL_CONTROL_6:
901 case WM8962_FLL_CONTROL_7:
902 case WM8962_FLL_CONTROL_8:
903 case WM8962_GENERAL_TEST_1:
904 case WM8962_DF1:
905 case WM8962_DF2:
906 case WM8962_DF3:
907 case WM8962_DF4:
908 case WM8962_DF5:
909 case WM8962_DF6:
910 case WM8962_DF7:
911 case WM8962_LHPF1:
912 case WM8962_LHPF2:
913 case WM8962_THREED1:
914 case WM8962_THREED2:
915 case WM8962_THREED3:
916 case WM8962_THREED4:
917 case WM8962_DRC_1:
918 case WM8962_DRC_2:
919 case WM8962_DRC_3:
920 case WM8962_DRC_4:
921 case WM8962_DRC_5:
922 case WM8962_TLOOPBACK:
923 case WM8962_EQ1:
924 case WM8962_EQ2:
925 case WM8962_EQ3:
926 case WM8962_EQ4:
927 case WM8962_EQ5:
928 case WM8962_EQ6:
929 case WM8962_EQ7:
930 case WM8962_EQ8:
931 case WM8962_EQ9:
932 case WM8962_EQ10:
933 case WM8962_EQ11:
934 case WM8962_EQ12:
935 case WM8962_EQ13:
936 case WM8962_EQ14:
937 case WM8962_EQ15:
938 case WM8962_EQ16:
939 case WM8962_EQ17:
940 case WM8962_EQ18:
941 case WM8962_EQ19:
942 case WM8962_EQ20:
943 case WM8962_EQ21:
944 case WM8962_EQ22:
945 case WM8962_EQ23:
946 case WM8962_EQ24:
947 case WM8962_EQ25:
948 case WM8962_EQ26:
949 case WM8962_EQ27:
950 case WM8962_EQ28:
951 case WM8962_EQ29:
952 case WM8962_EQ30:
953 case WM8962_EQ31:
954 case WM8962_EQ32:
955 case WM8962_EQ33:
956 case WM8962_EQ34:
957 case WM8962_EQ35:
958 case WM8962_EQ36:
959 case WM8962_EQ37:
960 case WM8962_EQ38:
961 case WM8962_EQ39:
962 case WM8962_EQ40:
963 case WM8962_EQ41:
964 case WM8962_GPIO_BASE:
965 case WM8962_GPIO_2:
966 case WM8962_GPIO_3:
967 case WM8962_GPIO_5:
968 case WM8962_GPIO_6:
969 case WM8962_INTERRUPT_STATUS_1:
970 case WM8962_INTERRUPT_STATUS_2:
971 case WM8962_INTERRUPT_STATUS_1_MASK:
972 case WM8962_INTERRUPT_STATUS_2_MASK:
973 case WM8962_INTERRUPT_CONTROL:
974 case WM8962_IRQ_DEBOUNCE:
975 case WM8962_MICINT_SOURCE_POL:
976 case WM8962_DSP2_POWER_MANAGEMENT:
977 case WM8962_DSP2_EXECCONTROL:
978 case WM8962_DSP2_INSTRUCTION_RAM_0:
979 case WM8962_DSP2_ADDRESS_RAM_2:
980 case WM8962_DSP2_ADDRESS_RAM_1:
981 case WM8962_DSP2_ADDRESS_RAM_0:
982 case WM8962_DSP2_DATA1_RAM_1:
983 case WM8962_DSP2_DATA1_RAM_0:
984 case WM8962_DSP2_DATA2_RAM_1:
985 case WM8962_DSP2_DATA2_RAM_0:
986 case WM8962_DSP2_DATA3_RAM_1:
987 case WM8962_DSP2_DATA3_RAM_0:
988 case WM8962_DSP2_COEFF_RAM_0:
989 case WM8962_RETUNEADC_SHARED_COEFF_1:
990 case WM8962_RETUNEADC_SHARED_COEFF_0:
991 case WM8962_RETUNEDAC_SHARED_COEFF_1:
992 case WM8962_RETUNEDAC_SHARED_COEFF_0:
993 case WM8962_SOUNDSTAGE_ENABLES_1:
994 case WM8962_SOUNDSTAGE_ENABLES_0:
995 case WM8962_HDBASS_AI_1:
996 case WM8962_HDBASS_AI_0:
997 case WM8962_HDBASS_AR_1:
998 case WM8962_HDBASS_AR_0:
999 case WM8962_HDBASS_B_1:
1000 case WM8962_HDBASS_B_0:
1001 case WM8962_HDBASS_K_1:
1002 case WM8962_HDBASS_K_0:
1003 case WM8962_HDBASS_N1_1:
1004 case WM8962_HDBASS_N1_0:
1005 case WM8962_HDBASS_N2_1:
1006 case WM8962_HDBASS_N2_0:
1007 case WM8962_HDBASS_N3_1:
1008 case WM8962_HDBASS_N3_0:
1009 case WM8962_HDBASS_N4_1:
1010 case WM8962_HDBASS_N4_0:
1011 case WM8962_HDBASS_N5_1:
1012 case WM8962_HDBASS_N5_0:
1013 case WM8962_HDBASS_X1_1:
1014 case WM8962_HDBASS_X1_0:
1015 case WM8962_HDBASS_X2_1:
1016 case WM8962_HDBASS_X2_0:
1017 case WM8962_HDBASS_X3_1:
1018 case WM8962_HDBASS_X3_0:
1019 case WM8962_HDBASS_ATK_1:
1020 case WM8962_HDBASS_ATK_0:
1021 case WM8962_HDBASS_DCY_1:
1022 case WM8962_HDBASS_DCY_0:
1023 case WM8962_HDBASS_PG_1:
1024 case WM8962_HDBASS_PG_0:
1025 case WM8962_HPF_C_1:
1026 case WM8962_HPF_C_0:
1027 case WM8962_ADCL_RETUNE_C1_1:
1028 case WM8962_ADCL_RETUNE_C1_0:
1029 case WM8962_ADCL_RETUNE_C2_1:
1030 case WM8962_ADCL_RETUNE_C2_0:
1031 case WM8962_ADCL_RETUNE_C3_1:
1032 case WM8962_ADCL_RETUNE_C3_0:
1033 case WM8962_ADCL_RETUNE_C4_1:
1034 case WM8962_ADCL_RETUNE_C4_0:
1035 case WM8962_ADCL_RETUNE_C5_1:
1036 case WM8962_ADCL_RETUNE_C5_0:
1037 case WM8962_ADCL_RETUNE_C6_1:
1038 case WM8962_ADCL_RETUNE_C6_0:
1039 case WM8962_ADCL_RETUNE_C7_1:
1040 case WM8962_ADCL_RETUNE_C7_0:
1041 case WM8962_ADCL_RETUNE_C8_1:
1042 case WM8962_ADCL_RETUNE_C8_0:
1043 case WM8962_ADCL_RETUNE_C9_1:
1044 case WM8962_ADCL_RETUNE_C9_0:
1045 case WM8962_ADCL_RETUNE_C10_1:
1046 case WM8962_ADCL_RETUNE_C10_0:
1047 case WM8962_ADCL_RETUNE_C11_1:
1048 case WM8962_ADCL_RETUNE_C11_0:
1049 case WM8962_ADCL_RETUNE_C12_1:
1050 case WM8962_ADCL_RETUNE_C12_0:
1051 case WM8962_ADCL_RETUNE_C13_1:
1052 case WM8962_ADCL_RETUNE_C13_0:
1053 case WM8962_ADCL_RETUNE_C14_1:
1054 case WM8962_ADCL_RETUNE_C14_0:
1055 case WM8962_ADCL_RETUNE_C15_1:
1056 case WM8962_ADCL_RETUNE_C15_0:
1057 case WM8962_ADCL_RETUNE_C16_1:
1058 case WM8962_ADCL_RETUNE_C16_0:
1059 case WM8962_ADCL_RETUNE_C17_1:
1060 case WM8962_ADCL_RETUNE_C17_0:
1061 case WM8962_ADCL_RETUNE_C18_1:
1062 case WM8962_ADCL_RETUNE_C18_0:
1063 case WM8962_ADCL_RETUNE_C19_1:
1064 case WM8962_ADCL_RETUNE_C19_0:
1065 case WM8962_ADCL_RETUNE_C20_1:
1066 case WM8962_ADCL_RETUNE_C20_0:
1067 case WM8962_ADCL_RETUNE_C21_1:
1068 case WM8962_ADCL_RETUNE_C21_0:
1069 case WM8962_ADCL_RETUNE_C22_1:
1070 case WM8962_ADCL_RETUNE_C22_0:
1071 case WM8962_ADCL_RETUNE_C23_1:
1072 case WM8962_ADCL_RETUNE_C23_0:
1073 case WM8962_ADCL_RETUNE_C24_1:
1074 case WM8962_ADCL_RETUNE_C24_0:
1075 case WM8962_ADCL_RETUNE_C25_1:
1076 case WM8962_ADCL_RETUNE_C25_0:
1077 case WM8962_ADCL_RETUNE_C26_1:
1078 case WM8962_ADCL_RETUNE_C26_0:
1079 case WM8962_ADCL_RETUNE_C27_1:
1080 case WM8962_ADCL_RETUNE_C27_0:
1081 case WM8962_ADCL_RETUNE_C28_1:
1082 case WM8962_ADCL_RETUNE_C28_0:
1083 case WM8962_ADCL_RETUNE_C29_1:
1084 case WM8962_ADCL_RETUNE_C29_0:
1085 case WM8962_ADCL_RETUNE_C30_1:
1086 case WM8962_ADCL_RETUNE_C30_0:
1087 case WM8962_ADCL_RETUNE_C31_1:
1088 case WM8962_ADCL_RETUNE_C31_0:
1089 case WM8962_ADCL_RETUNE_C32_1:
1090 case WM8962_ADCL_RETUNE_C32_0:
1091 case WM8962_RETUNEADC_PG2_1:
1092 case WM8962_RETUNEADC_PG2_0:
1093 case WM8962_RETUNEADC_PG_1:
1094 case WM8962_RETUNEADC_PG_0:
1095 case WM8962_ADCR_RETUNE_C1_1:
1096 case WM8962_ADCR_RETUNE_C1_0:
1097 case WM8962_ADCR_RETUNE_C2_1:
1098 case WM8962_ADCR_RETUNE_C2_0:
1099 case WM8962_ADCR_RETUNE_C3_1:
1100 case WM8962_ADCR_RETUNE_C3_0:
1101 case WM8962_ADCR_RETUNE_C4_1:
1102 case WM8962_ADCR_RETUNE_C4_0:
1103 case WM8962_ADCR_RETUNE_C5_1:
1104 case WM8962_ADCR_RETUNE_C5_0:
1105 case WM8962_ADCR_RETUNE_C6_1:
1106 case WM8962_ADCR_RETUNE_C6_0:
1107 case WM8962_ADCR_RETUNE_C7_1:
1108 case WM8962_ADCR_RETUNE_C7_0:
1109 case WM8962_ADCR_RETUNE_C8_1:
1110 case WM8962_ADCR_RETUNE_C8_0:
1111 case WM8962_ADCR_RETUNE_C9_1:
1112 case WM8962_ADCR_RETUNE_C9_0:
1113 case WM8962_ADCR_RETUNE_C10_1:
1114 case WM8962_ADCR_RETUNE_C10_0:
1115 case WM8962_ADCR_RETUNE_C11_1:
1116 case WM8962_ADCR_RETUNE_C11_0:
1117 case WM8962_ADCR_RETUNE_C12_1:
1118 case WM8962_ADCR_RETUNE_C12_0:
1119 case WM8962_ADCR_RETUNE_C13_1:
1120 case WM8962_ADCR_RETUNE_C13_0:
1121 case WM8962_ADCR_RETUNE_C14_1:
1122 case WM8962_ADCR_RETUNE_C14_0:
1123 case WM8962_ADCR_RETUNE_C15_1:
1124 case WM8962_ADCR_RETUNE_C15_0:
1125 case WM8962_ADCR_RETUNE_C16_1:
1126 case WM8962_ADCR_RETUNE_C16_0:
1127 case WM8962_ADCR_RETUNE_C17_1:
1128 case WM8962_ADCR_RETUNE_C17_0:
1129 case WM8962_ADCR_RETUNE_C18_1:
1130 case WM8962_ADCR_RETUNE_C18_0:
1131 case WM8962_ADCR_RETUNE_C19_1:
1132 case WM8962_ADCR_RETUNE_C19_0:
1133 case WM8962_ADCR_RETUNE_C20_1:
1134 case WM8962_ADCR_RETUNE_C20_0:
1135 case WM8962_ADCR_RETUNE_C21_1:
1136 case WM8962_ADCR_RETUNE_C21_0:
1137 case WM8962_ADCR_RETUNE_C22_1:
1138 case WM8962_ADCR_RETUNE_C22_0:
1139 case WM8962_ADCR_RETUNE_C23_1:
1140 case WM8962_ADCR_RETUNE_C23_0:
1141 case WM8962_ADCR_RETUNE_C24_1:
1142 case WM8962_ADCR_RETUNE_C24_0:
1143 case WM8962_ADCR_RETUNE_C25_1:
1144 case WM8962_ADCR_RETUNE_C25_0:
1145 case WM8962_ADCR_RETUNE_C26_1:
1146 case WM8962_ADCR_RETUNE_C26_0:
1147 case WM8962_ADCR_RETUNE_C27_1:
1148 case WM8962_ADCR_RETUNE_C27_0:
1149 case WM8962_ADCR_RETUNE_C28_1:
1150 case WM8962_ADCR_RETUNE_C28_0:
1151 case WM8962_ADCR_RETUNE_C29_1:
1152 case WM8962_ADCR_RETUNE_C29_0:
1153 case WM8962_ADCR_RETUNE_C30_1:
1154 case WM8962_ADCR_RETUNE_C30_0:
1155 case WM8962_ADCR_RETUNE_C31_1:
1156 case WM8962_ADCR_RETUNE_C31_0:
1157 case WM8962_ADCR_RETUNE_C32_1:
1158 case WM8962_ADCR_RETUNE_C32_0:
1159 case WM8962_DACL_RETUNE_C1_1:
1160 case WM8962_DACL_RETUNE_C1_0:
1161 case WM8962_DACL_RETUNE_C2_1:
1162 case WM8962_DACL_RETUNE_C2_0:
1163 case WM8962_DACL_RETUNE_C3_1:
1164 case WM8962_DACL_RETUNE_C3_0:
1165 case WM8962_DACL_RETUNE_C4_1:
1166 case WM8962_DACL_RETUNE_C4_0:
1167 case WM8962_DACL_RETUNE_C5_1:
1168 case WM8962_DACL_RETUNE_C5_0:
1169 case WM8962_DACL_RETUNE_C6_1:
1170 case WM8962_DACL_RETUNE_C6_0:
1171 case WM8962_DACL_RETUNE_C7_1:
1172 case WM8962_DACL_RETUNE_C7_0:
1173 case WM8962_DACL_RETUNE_C8_1:
1174 case WM8962_DACL_RETUNE_C8_0:
1175 case WM8962_DACL_RETUNE_C9_1:
1176 case WM8962_DACL_RETUNE_C9_0:
1177 case WM8962_DACL_RETUNE_C10_1:
1178 case WM8962_DACL_RETUNE_C10_0:
1179 case WM8962_DACL_RETUNE_C11_1:
1180 case WM8962_DACL_RETUNE_C11_0:
1181 case WM8962_DACL_RETUNE_C12_1:
1182 case WM8962_DACL_RETUNE_C12_0:
1183 case WM8962_DACL_RETUNE_C13_1:
1184 case WM8962_DACL_RETUNE_C13_0:
1185 case WM8962_DACL_RETUNE_C14_1:
1186 case WM8962_DACL_RETUNE_C14_0:
1187 case WM8962_DACL_RETUNE_C15_1:
1188 case WM8962_DACL_RETUNE_C15_0:
1189 case WM8962_DACL_RETUNE_C16_1:
1190 case WM8962_DACL_RETUNE_C16_0:
1191 case WM8962_DACL_RETUNE_C17_1:
1192 case WM8962_DACL_RETUNE_C17_0:
1193 case WM8962_DACL_RETUNE_C18_1:
1194 case WM8962_DACL_RETUNE_C18_0:
1195 case WM8962_DACL_RETUNE_C19_1:
1196 case WM8962_DACL_RETUNE_C19_0:
1197 case WM8962_DACL_RETUNE_C20_1:
1198 case WM8962_DACL_RETUNE_C20_0:
1199 case WM8962_DACL_RETUNE_C21_1:
1200 case WM8962_DACL_RETUNE_C21_0:
1201 case WM8962_DACL_RETUNE_C22_1:
1202 case WM8962_DACL_RETUNE_C22_0:
1203 case WM8962_DACL_RETUNE_C23_1:
1204 case WM8962_DACL_RETUNE_C23_0:
1205 case WM8962_DACL_RETUNE_C24_1:
1206 case WM8962_DACL_RETUNE_C24_0:
1207 case WM8962_DACL_RETUNE_C25_1:
1208 case WM8962_DACL_RETUNE_C25_0:
1209 case WM8962_DACL_RETUNE_C26_1:
1210 case WM8962_DACL_RETUNE_C26_0:
1211 case WM8962_DACL_RETUNE_C27_1:
1212 case WM8962_DACL_RETUNE_C27_0:
1213 case WM8962_DACL_RETUNE_C28_1:
1214 case WM8962_DACL_RETUNE_C28_0:
1215 case WM8962_DACL_RETUNE_C29_1:
1216 case WM8962_DACL_RETUNE_C29_0:
1217 case WM8962_DACL_RETUNE_C30_1:
1218 case WM8962_DACL_RETUNE_C30_0:
1219 case WM8962_DACL_RETUNE_C31_1:
1220 case WM8962_DACL_RETUNE_C31_0:
1221 case WM8962_DACL_RETUNE_C32_1:
1222 case WM8962_DACL_RETUNE_C32_0:
1223 case WM8962_RETUNEDAC_PG2_1:
1224 case WM8962_RETUNEDAC_PG2_0:
1225 case WM8962_RETUNEDAC_PG_1:
1226 case WM8962_RETUNEDAC_PG_0:
1227 case WM8962_DACR_RETUNE_C1_1:
1228 case WM8962_DACR_RETUNE_C1_0:
1229 case WM8962_DACR_RETUNE_C2_1:
1230 case WM8962_DACR_RETUNE_C2_0:
1231 case WM8962_DACR_RETUNE_C3_1:
1232 case WM8962_DACR_RETUNE_C3_0:
1233 case WM8962_DACR_RETUNE_C4_1:
1234 case WM8962_DACR_RETUNE_C4_0:
1235 case WM8962_DACR_RETUNE_C5_1:
1236 case WM8962_DACR_RETUNE_C5_0:
1237 case WM8962_DACR_RETUNE_C6_1:
1238 case WM8962_DACR_RETUNE_C6_0:
1239 case WM8962_DACR_RETUNE_C7_1:
1240 case WM8962_DACR_RETUNE_C7_0:
1241 case WM8962_DACR_RETUNE_C8_1:
1242 case WM8962_DACR_RETUNE_C8_0:
1243 case WM8962_DACR_RETUNE_C9_1:
1244 case WM8962_DACR_RETUNE_C9_0:
1245 case WM8962_DACR_RETUNE_C10_1:
1246 case WM8962_DACR_RETUNE_C10_0:
1247 case WM8962_DACR_RETUNE_C11_1:
1248 case WM8962_DACR_RETUNE_C11_0:
1249 case WM8962_DACR_RETUNE_C12_1:
1250 case WM8962_DACR_RETUNE_C12_0:
1251 case WM8962_DACR_RETUNE_C13_1:
1252 case WM8962_DACR_RETUNE_C13_0:
1253 case WM8962_DACR_RETUNE_C14_1:
1254 case WM8962_DACR_RETUNE_C14_0:
1255 case WM8962_DACR_RETUNE_C15_1:
1256 case WM8962_DACR_RETUNE_C15_0:
1257 case WM8962_DACR_RETUNE_C16_1:
1258 case WM8962_DACR_RETUNE_C16_0:
1259 case WM8962_DACR_RETUNE_C17_1:
1260 case WM8962_DACR_RETUNE_C17_0:
1261 case WM8962_DACR_RETUNE_C18_1:
1262 case WM8962_DACR_RETUNE_C18_0:
1263 case WM8962_DACR_RETUNE_C19_1:
1264 case WM8962_DACR_RETUNE_C19_0:
1265 case WM8962_DACR_RETUNE_C20_1:
1266 case WM8962_DACR_RETUNE_C20_0:
1267 case WM8962_DACR_RETUNE_C21_1:
1268 case WM8962_DACR_RETUNE_C21_0:
1269 case WM8962_DACR_RETUNE_C22_1:
1270 case WM8962_DACR_RETUNE_C22_0:
1271 case WM8962_DACR_RETUNE_C23_1:
1272 case WM8962_DACR_RETUNE_C23_0:
1273 case WM8962_DACR_RETUNE_C24_1:
1274 case WM8962_DACR_RETUNE_C24_0:
1275 case WM8962_DACR_RETUNE_C25_1:
1276 case WM8962_DACR_RETUNE_C25_0:
1277 case WM8962_DACR_RETUNE_C26_1:
1278 case WM8962_DACR_RETUNE_C26_0:
1279 case WM8962_DACR_RETUNE_C27_1:
1280 case WM8962_DACR_RETUNE_C27_0:
1281 case WM8962_DACR_RETUNE_C28_1:
1282 case WM8962_DACR_RETUNE_C28_0:
1283 case WM8962_DACR_RETUNE_C29_1:
1284 case WM8962_DACR_RETUNE_C29_0:
1285 case WM8962_DACR_RETUNE_C30_1:
1286 case WM8962_DACR_RETUNE_C30_0:
1287 case WM8962_DACR_RETUNE_C31_1:
1288 case WM8962_DACR_RETUNE_C31_0:
1289 case WM8962_DACR_RETUNE_C32_1:
1290 case WM8962_DACR_RETUNE_C32_0:
1291 case WM8962_VSS_XHD2_1:
1292 case WM8962_VSS_XHD2_0:
1293 case WM8962_VSS_XHD3_1:
1294 case WM8962_VSS_XHD3_0:
1295 case WM8962_VSS_XHN1_1:
1296 case WM8962_VSS_XHN1_0:
1297 case WM8962_VSS_XHN2_1:
1298 case WM8962_VSS_XHN2_0:
1299 case WM8962_VSS_XHN3_1:
1300 case WM8962_VSS_XHN3_0:
1301 case WM8962_VSS_XLA_1:
1302 case WM8962_VSS_XLA_0:
1303 case WM8962_VSS_XLB_1:
1304 case WM8962_VSS_XLB_0:
1305 case WM8962_VSS_XLG_1:
1306 case WM8962_VSS_XLG_0:
1307 case WM8962_VSS_PG2_1:
1308 case WM8962_VSS_PG2_0:
1309 case WM8962_VSS_PG_1:
1310 case WM8962_VSS_PG_0:
1311 case WM8962_VSS_XTD1_1:
1312 case WM8962_VSS_XTD1_0:
1313 case WM8962_VSS_XTD2_1:
1314 case WM8962_VSS_XTD2_0:
1315 case WM8962_VSS_XTD3_1:
1316 case WM8962_VSS_XTD3_0:
1317 case WM8962_VSS_XTD4_1:
1318 case WM8962_VSS_XTD4_0:
1319 case WM8962_VSS_XTD5_1:
1320 case WM8962_VSS_XTD5_0:
1321 case WM8962_VSS_XTD6_1:
1322 case WM8962_VSS_XTD6_0:
1323 case WM8962_VSS_XTD7_1:
1324 case WM8962_VSS_XTD7_0:
1325 case WM8962_VSS_XTD8_1:
1326 case WM8962_VSS_XTD8_0:
1327 case WM8962_VSS_XTD9_1:
1328 case WM8962_VSS_XTD9_0:
1329 case WM8962_VSS_XTD10_1:
1330 case WM8962_VSS_XTD10_0:
1331 case WM8962_VSS_XTD11_1:
1332 case WM8962_VSS_XTD11_0:
1333 case WM8962_VSS_XTD12_1:
1334 case WM8962_VSS_XTD12_0:
1335 case WM8962_VSS_XTD13_1:
1336 case WM8962_VSS_XTD13_0:
1337 case WM8962_VSS_XTD14_1:
1338 case WM8962_VSS_XTD14_0:
1339 case WM8962_VSS_XTD15_1:
1340 case WM8962_VSS_XTD15_0:
1341 case WM8962_VSS_XTD16_1:
1342 case WM8962_VSS_XTD16_0:
1343 case WM8962_VSS_XTD17_1:
1344 case WM8962_VSS_XTD17_0:
1345 case WM8962_VSS_XTD18_1:
1346 case WM8962_VSS_XTD18_0:
1347 case WM8962_VSS_XTD19_1:
1348 case WM8962_VSS_XTD19_0:
1349 case WM8962_VSS_XTD20_1:
1350 case WM8962_VSS_XTD20_0:
1351 case WM8962_VSS_XTD21_1:
1352 case WM8962_VSS_XTD21_0:
1353 case WM8962_VSS_XTD22_1:
1354 case WM8962_VSS_XTD22_0:
1355 case WM8962_VSS_XTD23_1:
1356 case WM8962_VSS_XTD23_0:
1357 case WM8962_VSS_XTD24_1:
1358 case WM8962_VSS_XTD24_0:
1359 case WM8962_VSS_XTD25_1:
1360 case WM8962_VSS_XTD25_0:
1361 case WM8962_VSS_XTD26_1:
1362 case WM8962_VSS_XTD26_0:
1363 case WM8962_VSS_XTD27_1:
1364 case WM8962_VSS_XTD27_0:
1365 case WM8962_VSS_XTD28_1:
1366 case WM8962_VSS_XTD28_0:
1367 case WM8962_VSS_XTD29_1:
1368 case WM8962_VSS_XTD29_0:
1369 case WM8962_VSS_XTD30_1:
1370 case WM8962_VSS_XTD30_0:
1371 case WM8962_VSS_XTD31_1:
1372 case WM8962_VSS_XTD31_0:
1373 case WM8962_VSS_XTD32_1:
1374 case WM8962_VSS_XTD32_0:
1375 case WM8962_VSS_XTS1_1:
1376 case WM8962_VSS_XTS1_0:
1377 case WM8962_VSS_XTS2_1:
1378 case WM8962_VSS_XTS2_0:
1379 case WM8962_VSS_XTS3_1:
1380 case WM8962_VSS_XTS3_0:
1381 case WM8962_VSS_XTS4_1:
1382 case WM8962_VSS_XTS4_0:
1383 case WM8962_VSS_XTS5_1:
1384 case WM8962_VSS_XTS5_0:
1385 case WM8962_VSS_XTS6_1:
1386 case WM8962_VSS_XTS6_0:
1387 case WM8962_VSS_XTS7_1:
1388 case WM8962_VSS_XTS7_0:
1389 case WM8962_VSS_XTS8_1:
1390 case WM8962_VSS_XTS8_0:
1391 case WM8962_VSS_XTS9_1:
1392 case WM8962_VSS_XTS9_0:
1393 case WM8962_VSS_XTS10_1:
1394 case WM8962_VSS_XTS10_0:
1395 case WM8962_VSS_XTS11_1:
1396 case WM8962_VSS_XTS11_0:
1397 case WM8962_VSS_XTS12_1:
1398 case WM8962_VSS_XTS12_0:
1399 case WM8962_VSS_XTS13_1:
1400 case WM8962_VSS_XTS13_0:
1401 case WM8962_VSS_XTS14_1:
1402 case WM8962_VSS_XTS14_0:
1403 case WM8962_VSS_XTS15_1:
1404 case WM8962_VSS_XTS15_0:
1405 case WM8962_VSS_XTS16_1:
1406 case WM8962_VSS_XTS16_0:
1407 case WM8962_VSS_XTS17_1:
1408 case WM8962_VSS_XTS17_0:
1409 case WM8962_VSS_XTS18_1:
1410 case WM8962_VSS_XTS18_0:
1411 case WM8962_VSS_XTS19_1:
1412 case WM8962_VSS_XTS19_0:
1413 case WM8962_VSS_XTS20_1:
1414 case WM8962_VSS_XTS20_0:
1415 case WM8962_VSS_XTS21_1:
1416 case WM8962_VSS_XTS21_0:
1417 case WM8962_VSS_XTS22_1:
1418 case WM8962_VSS_XTS22_0:
1419 case WM8962_VSS_XTS23_1:
1420 case WM8962_VSS_XTS23_0:
1421 case WM8962_VSS_XTS24_1:
1422 case WM8962_VSS_XTS24_0:
1423 case WM8962_VSS_XTS25_1:
1424 case WM8962_VSS_XTS25_0:
1425 case WM8962_VSS_XTS26_1:
1426 case WM8962_VSS_XTS26_0:
1427 case WM8962_VSS_XTS27_1:
1428 case WM8962_VSS_XTS27_0:
1429 case WM8962_VSS_XTS28_1:
1430 case WM8962_VSS_XTS28_0:
1431 case WM8962_VSS_XTS29_1:
1432 case WM8962_VSS_XTS29_0:
1433 case WM8962_VSS_XTS30_1:
1434 case WM8962_VSS_XTS30_0:
1435 case WM8962_VSS_XTS31_1:
1436 case WM8962_VSS_XTS31_0:
1437 case WM8962_VSS_XTS32_1:
1438 case WM8962_VSS_XTS32_0:
1439 return true;
1440 default:
1441 return false;
1442 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1443}
1444
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]1445static int wm8962_reset(struct wm8962_priv *wm8962)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1446{
Mark Brown4f4488a2011-11-01 13:36:10 +0000[diff] [blame]1447 int ret;
1448
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]1449 ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
Mark Brown4f4488a2011-11-01 13:36:10 +0000[diff] [blame]1450 if (ret != 0)
1451 return ret;
1452
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]1453 return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1454}
1455
1456static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1457static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1458static const unsigned int mixinpga_tlv[] = {
Clemens Ladisch43e9dc72011-11-20 15:13:27 +0100[diff] [blame]1459 TLV_DB_RANGE_HEAD(5),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1460 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1461 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1462 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1463 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1464 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
1465};
1466static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1467static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1468static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1469static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1470static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1471static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1472static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1473static const unsigned int classd_tlv[] = {
Clemens Ladisch43e9dc72011-11-20 15:13:27 +0100[diff] [blame]1474 TLV_DB_RANGE_HEAD(2),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1475 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1476 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
1477};
Mark Brown8f63aaa882011-06-07 23:14:37 +0100[diff] [blame]1478static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1479
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1480static int wm8962_dsp2_write_config(struct snd_soc_codec *codec)
1481{
Lars-Peter Clausend7f31d32014-02-22 18:32:05 +0100[diff] [blame]1482 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1483
1484 return regcache_sync_region(wm8962->regmap,
Mark Brown26b427a2012-02-23 20:19:47 +0000[diff] [blame]1485 WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1486}
1487
1488static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val)
1489{
1490 u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME);
1491 u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME);
1492 u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1);
1493
1494 /* Mute the ADCs and DACs */
1495 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0);
1496 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1497 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1498 WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1499
1500 snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val);
1501
1502 /* Restore the ADCs and DACs */
1503 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl);
1504 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr);
1505 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1506 WM8962_DAC_MUTE, dac);
1507
1508 return 0;
1509}
1510
1511static int wm8962_dsp2_start(struct snd_soc_codec *codec)
1512{
1513 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1514
1515 wm8962_dsp2_write_config(codec);
1516
1517 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1518
1519 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1520
1521 return 0;
1522}
1523
1524static int wm8962_dsp2_stop(struct snd_soc_codec *codec)
1525{
1526 wm8962_dsp2_set_enable(codec, 0);
1527
1528 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1529
1530 return 0;
1531}
1532
1533#define WM8962_DSP2_ENABLE(xname, xshift) \
1534{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1535 .info = wm8962_dsp2_ena_info, \
1536 .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1537 .private_value = xshift }
1538
1539static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1540 struct snd_ctl_elem_info *uinfo)
1541{
1542 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1543
1544 uinfo->count = 1;
1545 uinfo->value.integer.min = 0;
1546 uinfo->value.integer.max = 1;
1547
1548 return 0;
1549}
1550
1551static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1552 struct snd_ctl_elem_value *ucontrol)
1553{
1554 int shift = kcontrol->private_value;
1555 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1556 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1557
1558 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1559
1560 return 0;
1561}
1562
1563static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1564 struct snd_ctl_elem_value *ucontrol)
1565{
1566 int shift = kcontrol->private_value;
1567 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1568 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1569 int old = wm8962->dsp2_ena;
1570 int ret = 0;
1571 int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) &
1572 WM8962_DSP2_ENA;
1573
1574 mutex_lock(&codec->mutex);
1575
1576 if (ucontrol->value.integer.value[0])
1577 wm8962->dsp2_ena |= 1 << shift;
1578 else
1579 wm8962->dsp2_ena &= ~(1 << shift);
1580
1581 if (wm8962->dsp2_ena == old)
1582 goto out;
1583
1584 ret = 1;
1585
1586 if (dsp2_running) {
1587 if (wm8962->dsp2_ena)
1588 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1589 else
1590 wm8962_dsp2_stop(codec);
1591 }
1592
1593out:
1594 mutex_unlock(&codec->mutex);
1595
1596 return ret;
1597}
1598
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1599/* The VU bits for the headphones are in a different register to the mute
1600 * bits and only take effect on the PGA if it is actually powered.
1601 */
1602static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1603 struct snd_ctl_elem_value *ucontrol)
1604{
1605 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1606 int ret;
1607
1608 /* Apply the update (if any) */
1609 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1610 if (ret == 0)
1611 return 0;
1612
1613 /* If the left PGA is enabled hit that VU bit... */
Nicolin Chen2e7ee152013-06-14 12:34:50 +0800[diff] [blame]1614 ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1615 if (ret & WM8962_HPOUTL_PGA_ENA) {
1616 snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
1617 snd_soc_read(codec, WM8962_HPOUTL_VOLUME));
1618 return 1;
1619 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1620
1621 /* ...otherwise the right. The VU is stereo. */
Nicolin Chen2e7ee152013-06-14 12:34:50 +0800[diff] [blame]1622 if (ret & WM8962_HPOUTR_PGA_ENA)
1623 snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
1624 snd_soc_read(codec, WM8962_HPOUTR_VOLUME));
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1625
Nicolin Chen2e7ee152013-06-14 12:34:50 +0800[diff] [blame]1626 return 1;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1627}
1628
1629/* The VU bits for the speakers are in a different register to the mute
1630 * bits and only take effect on the PGA if it is actually powered.
1631 */
1632static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1633 struct snd_ctl_elem_value *ucontrol)
1634{
1635 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1636 int ret;
1637
1638 /* Apply the update (if any) */
1639 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1640 if (ret == 0)
1641 return 0;
1642
1643 /* If the left PGA is enabled hit that VU bit... */
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1644 ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1645 if (ret & WM8962_SPKOUTL_PGA_ENA) {
1646 snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
1647 snd_soc_read(codec, WM8962_SPKOUTL_VOLUME));
1648 return 1;
1649 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1650
1651 /* ...otherwise the right. The VU is stereo. */
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1652 if (ret & WM8962_SPKOUTR_PGA_ENA)
1653 snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
1654 snd_soc_read(codec, WM8962_SPKOUTR_VOLUME));
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1655
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1656 return 1;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1657}
1658
Mark Brown6be449e2011-04-26 16:04:37 +0100[diff] [blame]1659static const char *cap_hpf_mode_text[] = {
1660 "Hi-fi", "Application"
1661};
1662
Takashi Iwaida6ebf82014-02-18 10:43:07 +0100[diff] [blame]1663static SOC_ENUM_SINGLE_DECL(cap_hpf_mode,
1664 WM8962_ADC_DAC_CONTROL_2, 10, cap_hpf_mode_text);
Mark Brown6be449e2011-04-26 16:04:37 +0100[diff] [blame]1665
Mark Brown1ab63da2011-08-21 10:54:38 +0100[diff] [blame]1666
1667static const char *cap_lhpf_mode_text[] = {
1668 "LPF", "HPF"
1669};
1670
Takashi Iwaida6ebf82014-02-18 10:43:07 +0100[diff] [blame]1671static SOC_ENUM_SINGLE_DECL(cap_lhpf_mode,
1672 WM8962_LHPF1, 1, cap_lhpf_mode_text);
Mark Brown1ab63da2011-08-21 10:54:38 +0100[diff] [blame]1673
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1674static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1675SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1676
1677SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1678 mixin_tlv),
1679SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1680 mixinpga_tlv),
1681SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1682 mixin_tlv),
1683
1684SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1685 mixin_tlv),
1686SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1687 mixinpga_tlv),
1688SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1689 mixin_tlv),
1690
1691SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1692 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1693SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1694 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1695SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1696 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1697SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1698 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
Mark Brown6be449e2011-04-26 16:04:37 +0100[diff] [blame]1699SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1700SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1701SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
Mark Brown1ab63da2011-08-21 10:54:38 +0100[diff] [blame]1702SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1703SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1704
1705SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1706 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1707
1708SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1709 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1710SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
Mark Brown5f52ee42012-01-11 16:31:00 -0800[diff] [blame]1711SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1712SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1713
1714SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1715 5, 1, 0),
1716
1717SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1718
1719SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1720 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1721SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1722 snd_soc_get_volsw, wm8962_put_hp_sw),
1723SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1724 7, 1, 0),
1725SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1726 hp_tlv),
1727
1728SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1729 WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1730
1731SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1732 3, 7, 0, bypass_tlv),
1733SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1734 0, 7, 0, bypass_tlv),
1735SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1736 7, 1, 1, inmix_tlv),
1737SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1738 6, 1, 1, inmix_tlv),
1739
1740SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1741 3, 7, 0, bypass_tlv),
1742SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1743 0, 7, 0, bypass_tlv),
1744SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1745 7, 1, 1, inmix_tlv),
1746SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1747 6, 1, 1, inmix_tlv),
1748
1749SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1750 classd_tlv),
Mark Brown8f63aaa882011-06-07 23:14:37 +0100[diff] [blame]1751
1752SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1753SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1754 WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1755SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1756 WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1757SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1758 WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1759SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1760 WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1761SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1762 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
Richard Fitzgeraldae2ff9f2013-11-01 10:02:58 +0000[diff] [blame]1763SND_SOC_BYTES("EQL Coefficients", WM8962_EQ4, 18),
1764SND_SOC_BYTES("EQR Coefficients", WM8962_EQ24, 18),
1765
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1766
Mark Brown69e5a392012-02-21 23:21:17 +0000[diff] [blame]1767SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
1768SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
1769
Mark Brownacf31d42012-02-21 23:24:46 +0000[diff] [blame]1770SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
1771SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
1772
Mark Brownfd0ca452012-02-21 23:25:05 +0000[diff] [blame]1773SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
1774SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
1775
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1776WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
Mark Brown5462fcc2012-02-21 23:33:26 +0000[diff] [blame]1777SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1778WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1779WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
Mark Brown93a86be2012-03-06 00:29:37 +0000[diff] [blame]1780SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1781WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
Mark Brown5462fcc2012-02-21 23:33:26 +0000[diff] [blame]1782SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
Richard Fitzgeralddea0c742013-11-01 10:02:10 +0000[diff] [blame]1783
1784SOC_DOUBLE("ALC Switch", WM8962_ALC1, WM8962_ALCL_ENA_SHIFT,
1785 WM8962_ALCR_ENA_SHIFT, 1, 0),
1786SND_SOC_BYTES_MASK("ALC Coefficients", WM8962_ALC1, 4,
1787 WM8962_ALCL_ENA_MASK | WM8962_ALCR_ENA_MASK),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1788};
1789
1790static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1791SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1792SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1793 snd_soc_get_volsw, wm8962_put_spk_sw),
1794SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1795
1796SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1797SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1798 3, 7, 0, bypass_tlv),
1799SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1800 0, 7, 0, bypass_tlv),
1801SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1802 7, 1, 1, inmix_tlv),
1803SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1804 6, 1, 1, inmix_tlv),
1805SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1806 7, 1, 0, inmix_tlv),
1807SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1808 6, 1, 0, inmix_tlv),
1809};
1810
1811static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1812SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1813 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1814SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1815 snd_soc_get_volsw, wm8962_put_spk_sw),
1816SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1817 7, 1, 0),
1818
1819SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1820 WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1821
1822SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1823 3, 7, 0, bypass_tlv),
1824SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1825 0, 7, 0, bypass_tlv),
1826SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1827 7, 1, 1, inmix_tlv),
1828SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1829 6, 1, 1, inmix_tlv),
1830SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1831 7, 1, 0, inmix_tlv),
1832SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1833 6, 1, 0, inmix_tlv),
1834
1835SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1836 3, 7, 0, bypass_tlv),
1837SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1838 0, 7, 0, bypass_tlv),
1839SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1840 7, 1, 1, inmix_tlv),
1841SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1842 6, 1, 1, inmix_tlv),
1843SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1844 5, 1, 0, inmix_tlv),
1845SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1846 4, 1, 0, inmix_tlv),
1847};
1848
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1849static int cp_event(struct snd_soc_dapm_widget *w,
1850 struct snd_kcontrol *kcontrol, int event)
1851{
1852 switch (event) {
1853 case SND_SOC_DAPM_POST_PMU:
1854 msleep(5);
1855 break;
1856
1857 default:
Takashi Iwai69134362013-11-06 11:07:16 +0100[diff] [blame]1858 WARN(1, "Invalid event %d\n", event);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1859 return -EINVAL;
1860 }
1861
1862 return 0;
1863}
1864
1865static int hp_event(struct snd_soc_dapm_widget *w,
1866 struct snd_kcontrol *kcontrol, int event)
1867{
1868 struct snd_soc_codec *codec = w->codec;
1869 int timeout;
1870 int reg;
1871 int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1872 WM8962_DCS_STARTUP_DONE_HP1R);
1873
1874 switch (event) {
1875 case SND_SOC_DAPM_POST_PMU:
1876 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1877 WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1878 WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1879 udelay(20);
1880
1881 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1882 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1883 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1884
1885 /* Start the DC servo */
1886 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1887 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1888 WM8962_HP1L_DCS_STARTUP |
1889 WM8962_HP1R_DCS_STARTUP,
1890 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1891 WM8962_HP1L_DCS_STARTUP |
1892 WM8962_HP1R_DCS_STARTUP);
1893
1894 /* Wait for it to complete, should be well under 100ms */
1895 timeout = 0;
1896 do {
1897 msleep(1);
1898 reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
1899 if (reg < 0) {
1900 dev_err(codec->dev,
1901 "Failed to read DCS status: %d\n",
1902 reg);
1903 continue;
1904 }
1905 dev_dbg(codec->dev, "DCS status: %x\n", reg);
1906 } while (++timeout < 200 && (reg & expected) != expected);
1907
1908 if ((reg & expected) != expected)
1909 dev_err(codec->dev, "DC servo timed out\n");
1910 else
1911 dev_dbg(codec->dev, "DC servo complete after %dms\n",
1912 timeout);
1913
1914 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1915 WM8962_HP1L_ENA_OUTP |
1916 WM8962_HP1R_ENA_OUTP,
1917 WM8962_HP1L_ENA_OUTP |
1918 WM8962_HP1R_ENA_OUTP);
1919 udelay(20);
1920
1921 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1922 WM8962_HP1L_RMV_SHORT |
1923 WM8962_HP1R_RMV_SHORT,
1924 WM8962_HP1L_RMV_SHORT |
1925 WM8962_HP1R_RMV_SHORT);
1926 break;
1927
1928 case SND_SOC_DAPM_PRE_PMD:
1929 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1930 WM8962_HP1L_RMV_SHORT |
1931 WM8962_HP1R_RMV_SHORT, 0);
1932
1933 udelay(20);
1934
1935 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1936 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1937 WM8962_HP1L_DCS_STARTUP |
1938 WM8962_HP1R_DCS_STARTUP,
1939 0);
1940
1941 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1942 WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1943 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1944 WM8962_HP1L_ENA_OUTP |
1945 WM8962_HP1R_ENA_OUTP, 0);
1946
1947 break;
1948
1949 default:
Takashi Iwai69134362013-11-06 11:07:16 +0100[diff] [blame]1950 WARN(1, "Invalid event %d\n", event);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1951 return -EINVAL;
1952
1953 }
1954
1955 return 0;
1956}
1957
1958/* VU bits for the output PGAs only take effect while the PGA is powered */
1959static int out_pga_event(struct snd_soc_dapm_widget *w,
1960 struct snd_kcontrol *kcontrol, int event)
1961{
1962 struct snd_soc_codec *codec = w->codec;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1963 int reg;
1964
1965 switch (w->shift) {
1966 case WM8962_HPOUTR_PGA_ENA_SHIFT:
1967 reg = WM8962_HPOUTR_VOLUME;
1968 break;
1969 case WM8962_HPOUTL_PGA_ENA_SHIFT:
1970 reg = WM8962_HPOUTL_VOLUME;
1971 break;
1972 case WM8962_SPKOUTR_PGA_ENA_SHIFT:
1973 reg = WM8962_SPKOUTR_VOLUME;
1974 break;
1975 case WM8962_SPKOUTL_PGA_ENA_SHIFT:
1976 reg = WM8962_SPKOUTL_VOLUME;
1977 break;
1978 default:
Takashi Iwai69134362013-11-06 11:07:16 +0100[diff] [blame]1979 WARN(1, "Invalid shift %d\n", w->shift);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1980 return -EINVAL;
1981 }
1982
1983 switch (event) {
1984 case SND_SOC_DAPM_POST_PMU:
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1985 return snd_soc_write(codec, reg, snd_soc_read(codec, reg));
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1986 default:
Takashi Iwai69134362013-11-06 11:07:16 +0100[diff] [blame]1987 WARN(1, "Invalid event %d\n", event);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1988 return -EINVAL;
1989 }
1990}
1991
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1992static int dsp2_event(struct snd_soc_dapm_widget *w,
1993 struct snd_kcontrol *kcontrol, int event)
1994{
1995 struct snd_soc_codec *codec = w->codec;
1996 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1997
1998 switch (event) {
1999 case SND_SOC_DAPM_POST_PMU:
2000 if (wm8962->dsp2_ena)
2001 wm8962_dsp2_start(codec);
2002 break;
2003
2004 case SND_SOC_DAPM_PRE_PMD:
2005 if (wm8962->dsp2_ena)
2006 wm8962_dsp2_stop(codec);
2007 break;
2008
2009 default:
Takashi Iwai69134362013-11-06 11:07:16 +0100[diff] [blame]2010 WARN(1, "Invalid event %d\n", event);
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2011 return -EINVAL;
2012 }
2013
2014 return 0;
2015}
2016
Mark Brown31794bc2012-02-13 22:00:47 -0800[diff] [blame]2017static const char *st_text[] = { "None", "Left", "Right" };
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2018
Takashi Iwaida6ebf82014-02-18 10:43:07 +0100[diff] [blame]2019static SOC_ENUM_SINGLE_DECL(str_enum,
2020 WM8962_DAC_DSP_MIXING_1, 2, st_text);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2021
2022static const struct snd_kcontrol_new str_mux =
2023 SOC_DAPM_ENUM("Right Sidetone", str_enum);
2024
Takashi Iwaida6ebf82014-02-18 10:43:07 +0100[diff] [blame]2025static SOC_ENUM_SINGLE_DECL(stl_enum,
2026 WM8962_DAC_DSP_MIXING_2, 2, st_text);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2027
2028static const struct snd_kcontrol_new stl_mux =
2029 SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2030
2031static const char *outmux_text[] = { "DAC", "Mixer" };
2032
Takashi Iwaida6ebf82014-02-18 10:43:07 +0100[diff] [blame]2033static SOC_ENUM_SINGLE_DECL(spkoutr_enum,
2034 WM8962_SPEAKER_MIXER_2, 7, outmux_text);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2035
2036static const struct snd_kcontrol_new spkoutr_mux =
2037 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2038
Takashi Iwaida6ebf82014-02-18 10:43:07 +0100[diff] [blame]2039static SOC_ENUM_SINGLE_DECL(spkoutl_enum,
2040 WM8962_SPEAKER_MIXER_1, 7, outmux_text);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2041
2042static const struct snd_kcontrol_new spkoutl_mux =
2043 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2044
Takashi Iwaida6ebf82014-02-18 10:43:07 +0100[diff] [blame]2045static SOC_ENUM_SINGLE_DECL(hpoutr_enum,
2046 WM8962_HEADPHONE_MIXER_2, 7, outmux_text);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2047
2048static const struct snd_kcontrol_new hpoutr_mux =
2049 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2050
Takashi Iwaida6ebf82014-02-18 10:43:07 +0100[diff] [blame]2051static SOC_ENUM_SINGLE_DECL(hpoutl_enum,
2052 WM8962_HEADPHONE_MIXER_1, 7, outmux_text);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2053
2054static const struct snd_kcontrol_new hpoutl_mux =
2055 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2056
2057static const struct snd_kcontrol_new inpgal[] = {
2058SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2059SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2060SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2061SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2062};
2063
2064static const struct snd_kcontrol_new inpgar[] = {
2065SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2066SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2067SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2068SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2069};
2070
2071static const struct snd_kcontrol_new mixinl[] = {
2072SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2073SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2074SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2075};
2076
2077static const struct snd_kcontrol_new mixinr[] = {
2078SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2079SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2080SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2081};
2082
2083static const struct snd_kcontrol_new hpmixl[] = {
2084SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2085SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2086SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2087SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2088SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2089SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2090};
2091
2092static const struct snd_kcontrol_new hpmixr[] = {
2093SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2094SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2095SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2096SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2097SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2098SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2099};
2100
2101static const struct snd_kcontrol_new spkmixl[] = {
2102SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2103SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2104SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2105SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2106SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2107SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2108};
2109
2110static const struct snd_kcontrol_new spkmixr[] = {
2111SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2112SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2113SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2114SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2115SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2116SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2117};
2118
2119static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2120SND_SOC_DAPM_INPUT("IN1L"),
2121SND_SOC_DAPM_INPUT("IN1R"),
2122SND_SOC_DAPM_INPUT("IN2L"),
2123SND_SOC_DAPM_INPUT("IN2R"),
2124SND_SOC_DAPM_INPUT("IN3L"),
2125SND_SOC_DAPM_INPUT("IN3R"),
2126SND_SOC_DAPM_INPUT("IN4L"),
2127SND_SOC_DAPM_INPUT("IN4R"),
Mark Brown36c6b542011-11-27 16:24:18 +0000[diff] [blame]2128SND_SOC_DAPM_SIGGEN("Beep"),
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]2129SND_SOC_DAPM_INPUT("DMICDAT"),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2130
Mark Brown086d7f82011-09-23 16:22:48 +0100[diff] [blame]2131SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
Mark Browna4f28c02010-09-29 13:24:35 -0700[diff] [blame]2132
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2133SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
Mark Browna968d9d2012-01-27 19:54:03 +0000[diff] [blame]2134SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2135SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2136 SND_SOC_DAPM_POST_PMU),
2137SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2138SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2139 WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2140 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2141SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0),
2142SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2143
2144SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2145 inpgal, ARRAY_SIZE(inpgal)),
2146SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2147 inpgar, ARRAY_SIZE(inpgar)),
2148SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2149 mixinl, ARRAY_SIZE(mixinl)),
2150SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2151 mixinr, ARRAY_SIZE(mixinr)),
2152
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2153SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]2154
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2155SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2156SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2157
2158SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2159SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2160
2161SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2162SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2163
2164SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2165SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2166
2167SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2168 hpmixl, ARRAY_SIZE(hpmixl)),
2169SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2170 hpmixr, ARRAY_SIZE(hpmixr)),
2171
2172SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2173 out_pga_event, SND_SOC_DAPM_POST_PMU),
2174SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2175 out_pga_event, SND_SOC_DAPM_POST_PMU),
2176
2177SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2178 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2179
2180SND_SOC_DAPM_OUTPUT("HPOUTL"),
2181SND_SOC_DAPM_OUTPUT("HPOUTR"),
2182};
2183
2184static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2185SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2186 spkmixl, ARRAY_SIZE(spkmixl)),
2187SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2188 out_pga_event, SND_SOC_DAPM_POST_PMU),
2189SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2190SND_SOC_DAPM_OUTPUT("SPKOUT"),
2191};
2192
2193static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2194SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2195 spkmixl, ARRAY_SIZE(spkmixl)),
2196SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2197 spkmixr, ARRAY_SIZE(spkmixr)),
2198
2199SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2200 out_pga_event, SND_SOC_DAPM_POST_PMU),
2201SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2202 out_pga_event, SND_SOC_DAPM_POST_PMU),
2203
2204SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2205SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2206
2207SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2208SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2209};
2210
2211static const struct snd_soc_dapm_route wm8962_intercon[] = {
2212 { "INPGAL", "IN1L Switch", "IN1L" },
2213 { "INPGAL", "IN2L Switch", "IN2L" },
2214 { "INPGAL", "IN3L Switch", "IN3L" },
2215 { "INPGAL", "IN4L Switch", "IN4L" },
2216
2217 { "INPGAR", "IN1R Switch", "IN1R" },
2218 { "INPGAR", "IN2R Switch", "IN2R" },
2219 { "INPGAR", "IN3R Switch", "IN3R" },
2220 { "INPGAR", "IN4R Switch", "IN4R" },
2221
2222 { "MIXINL", "IN2L Switch", "IN2L" },
2223 { "MIXINL", "IN3L Switch", "IN3L" },
2224 { "MIXINL", "PGA Switch", "INPGAL" },
2225
2226 { "MIXINR", "IN2R Switch", "IN2R" },
2227 { "MIXINR", "IN3R Switch", "IN3R" },
2228 { "MIXINR", "PGA Switch", "INPGAR" },
2229
Mark Brown821f4202010-09-21 17:53:38 +0100[diff] [blame]2230 { "MICBIAS", NULL, "SYSCLK" },
2231
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2232 { "DMIC_ENA", NULL, "DMICDAT" },
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]2233
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2234 { "ADCL", NULL, "SYSCLK" },
2235 { "ADCL", NULL, "TOCLK" },
2236 { "ADCL", NULL, "MIXINL" },
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2237 { "ADCL", NULL, "DMIC_ENA" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2238 { "ADCL", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2239
2240 { "ADCR", NULL, "SYSCLK" },
2241 { "ADCR", NULL, "TOCLK" },
2242 { "ADCR", NULL, "MIXINR" },
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2243 { "ADCR", NULL, "DMIC_ENA" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2244 { "ADCR", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2245
2246 { "STL", "Left", "ADCL" },
2247 { "STL", "Right", "ADCR" },
Mark Brown1355ab12012-03-01 16:40:51 +0000[diff] [blame]2248 { "STL", NULL, "Class G" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2249
2250 { "STR", "Left", "ADCL" },
2251 { "STR", "Right", "ADCR" },
Mark Brown1355ab12012-03-01 16:40:51 +0000[diff] [blame]2252 { "STR", NULL, "Class G" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2253
2254 { "DACL", NULL, "SYSCLK" },
2255 { "DACL", NULL, "TOCLK" },
2256 { "DACL", NULL, "Beep" },
2257 { "DACL", NULL, "STL" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2258 { "DACL", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2259
2260 { "DACR", NULL, "SYSCLK" },
2261 { "DACR", NULL, "TOCLK" },
2262 { "DACR", NULL, "Beep" },
2263 { "DACR", NULL, "STR" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2264 { "DACR", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2265
2266 { "HPMIXL", "IN4L Switch", "IN4L" },
2267 { "HPMIXL", "IN4R Switch", "IN4R" },
2268 { "HPMIXL", "DACL Switch", "DACL" },
2269 { "HPMIXL", "DACR Switch", "DACR" },
2270 { "HPMIXL", "MIXINL Switch", "MIXINL" },
2271 { "HPMIXL", "MIXINR Switch", "MIXINR" },
2272
2273 { "HPMIXR", "IN4L Switch", "IN4L" },
2274 { "HPMIXR", "IN4R Switch", "IN4R" },
2275 { "HPMIXR", "DACL Switch", "DACL" },
2276 { "HPMIXR", "DACR Switch", "DACR" },
2277 { "HPMIXR", "MIXINL Switch", "MIXINL" },
2278 { "HPMIXR", "MIXINR Switch", "MIXINR" },
2279
2280 { "Left Bypass", NULL, "HPMIXL" },
2281 { "Left Bypass", NULL, "Class G" },
2282
2283 { "Right Bypass", NULL, "HPMIXR" },
2284 { "Right Bypass", NULL, "Class G" },
2285
2286 { "HPOUTL PGA", "Mixer", "Left Bypass" },
2287 { "HPOUTL PGA", "DAC", "DACL" },
2288
2289 { "HPOUTR PGA", "Mixer", "Right Bypass" },
2290 { "HPOUTR PGA", "DAC", "DACR" },
2291
2292 { "HPOUT", NULL, "HPOUTL PGA" },
2293 { "HPOUT", NULL, "HPOUTR PGA" },
2294 { "HPOUT", NULL, "Charge Pump" },
2295 { "HPOUT", NULL, "SYSCLK" },
2296 { "HPOUT", NULL, "TOCLK" },
2297
2298 { "HPOUTL", NULL, "HPOUT" },
2299 { "HPOUTR", NULL, "HPOUT" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2300
2301 { "HPOUTL", NULL, "TEMP_HP" },
2302 { "HPOUTR", NULL, "TEMP_HP" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2303};
2304
2305static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2306 { "Speaker Mixer", "IN4L Switch", "IN4L" },
2307 { "Speaker Mixer", "IN4R Switch", "IN4R" },
2308 { "Speaker Mixer", "DACL Switch", "DACL" },
2309 { "Speaker Mixer", "DACR Switch", "DACR" },
2310 { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2311 { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2312
2313 { "Speaker PGA", "Mixer", "Speaker Mixer" },
2314 { "Speaker PGA", "DAC", "DACL" },
2315
2316 { "Speaker Output", NULL, "Speaker PGA" },
2317 { "Speaker Output", NULL, "SYSCLK" },
2318 { "Speaker Output", NULL, "TOCLK" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2319 { "Speaker Output", NULL, "TEMP_SPK" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2320
2321 { "SPKOUT", NULL, "Speaker Output" },
2322};
2323
2324static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2325 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2326 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2327 { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2328 { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2329 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2330 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2331
2332 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2333 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2334 { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2335 { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2336 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2337 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2338
2339 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2340 { "SPKOUTL PGA", "DAC", "DACL" },
2341
2342 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2343 { "SPKOUTR PGA", "DAC", "DACR" },
2344
2345 { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2346 { "SPKOUTL Output", NULL, "SYSCLK" },
2347 { "SPKOUTL Output", NULL, "TOCLK" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2348 { "SPKOUTL Output", NULL, "TEMP_SPK" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2349
2350 { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2351 { "SPKOUTR Output", NULL, "SYSCLK" },
2352 { "SPKOUTR Output", NULL, "TOCLK" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2353 { "SPKOUTR Output", NULL, "TEMP_SPK" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2354
2355 { "SPKOUTL", NULL, "SPKOUTL Output" },
2356 { "SPKOUTR", NULL, "SPKOUTR Output" },
2357};
2358
2359static int wm8962_add_widgets(struct snd_soc_codec *codec)
2360{
Nicolin Chene75a52c2013-06-06 19:38:45 +0800[diff] [blame]2361 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2362 struct wm8962_pdata *pdata = &wm8962->pdata;
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2363 struct snd_soc_dapm_context *dapm = &codec->dapm;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2364
Liam Girdwood022658b2012-02-03 17:43:09 +0000[diff] [blame]2365 snd_soc_add_codec_controls(codec, wm8962_snd_controls,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2366 ARRAY_SIZE(wm8962_snd_controls));
Nicolin Chene75a52c2013-06-06 19:38:45 +0800[diff] [blame]2367 if (pdata->spk_mono)
Liam Girdwood022658b2012-02-03 17:43:09 +0000[diff] [blame]2368 snd_soc_add_codec_controls(codec, wm8962_spk_mono_controls,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2369 ARRAY_SIZE(wm8962_spk_mono_controls));
2370 else
Liam Girdwood022658b2012-02-03 17:43:09 +0000[diff] [blame]2371 snd_soc_add_codec_controls(codec, wm8962_spk_stereo_controls,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2372 ARRAY_SIZE(wm8962_spk_stereo_controls));
2373
2374
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2375 snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2376 ARRAY_SIZE(wm8962_dapm_widgets));
Nicolin Chene75a52c2013-06-06 19:38:45 +0800[diff] [blame]2377 if (pdata->spk_mono)
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2378 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2379 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2380 else
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2381 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2382 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2383
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2384 snd_soc_dapm_add_routes(dapm, wm8962_intercon,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2385 ARRAY_SIZE(wm8962_intercon));
Nicolin Chene75a52c2013-06-06 19:38:45 +0800[diff] [blame]2386 if (pdata->spk_mono)
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2387 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2388 ARRAY_SIZE(wm8962_spk_mono_intercon));
2389 else
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2390 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2391 ARRAY_SIZE(wm8962_spk_stereo_intercon));
2392
2393
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2394 snd_soc_dapm_disable_pin(dapm, "Beep");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2395
2396 return 0;
2397}
2398
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2399/* -1 for reserved values */
2400static const int bclk_divs[] = {
2401 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2402};
2403
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2404static const int sysclk_rates[] = {
Mark Brown07fabd12012-02-16 00:19:47 -0800[diff] [blame]2405 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2406};
2407
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2408static void wm8962_configure_bclk(struct snd_soc_codec *codec)
2409{
2410 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2411 int dspclk, i;
2412 int clocking2 = 0;
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2413 int clocking4 = 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2414 int aif2 = 0;
2415
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2416 if (!wm8962->sysclk_rate) {
2417 dev_dbg(codec->dev, "No SYSCLK configured\n");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2418 return;
2419 }
2420
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2421 if (!wm8962->bclk || !wm8962->lrclk) {
2422 dev_dbg(codec->dev, "No audio clocks configured\n");
2423 return;
2424 }
2425
2426 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2427 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2428 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2429 break;
2430 }
2431 }
2432
2433 if (i == ARRAY_SIZE(sysclk_rates)) {
2434 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
2435 wm8962->sysclk_rate / wm8962->lrclk);
2436 return;
2437 }
2438
Mark Browneeba1f82012-02-16 00:19:30 -0800[diff] [blame]2439 dev_dbg(codec->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
2440
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2441 snd_soc_update_bits(codec, WM8962_CLOCKING_4,
2442 WM8962_SYSCLK_RATE_MASK, clocking4);
2443
Nicolin Chen75704ec2013-12-04 17:22:16 +0800[diff] [blame]2444 /* DSPCLK_DIV can be only generated correctly after enabling SYSCLK.
2445 * So we here provisionally enable it and then disable it afterward
2446 * if current bias_level hasn't reached SND_SOC_BIAS_ON.
2447 */
2448 if (codec->dapm.bias_level != SND_SOC_BIAS_ON)
2449 snd_soc_update_bits(codec, WM8962_CLOCKING2,
2450 WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);
2451
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2452 dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
Nicolin Chen75704ec2013-12-04 17:22:16 +0800[diff] [blame]2453
2454 if (codec->dapm.bias_level != SND_SOC_BIAS_ON)
2455 snd_soc_update_bits(codec, WM8962_CLOCKING2,
2456 WM8962_SYSCLK_ENA_MASK, 0);
2457
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2458 if (dspclk < 0) {
2459 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
2460 return;
2461 }
2462
2463 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2464 switch (dspclk) {
2465 case 0:
2466 dspclk = wm8962->sysclk_rate;
2467 break;
2468 case 1:
2469 dspclk = wm8962->sysclk_rate / 2;
2470 break;
2471 case 2:
2472 dspclk = wm8962->sysclk_rate / 4;
2473 break;
2474 default:
2475 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
2476 dspclk = wm8962->sysclk;
2477 }
2478
2479 dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2480
2481 /* We're expecting an exact match */
2482 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2483 if (bclk_divs[i] < 0)
2484 continue;
2485
2486 if (dspclk / bclk_divs[i] == wm8962->bclk) {
2487 dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
2488 bclk_divs[i], wm8962->bclk);
2489 clocking2 |= i;
2490 break;
2491 }
2492 }
2493 if (i == ARRAY_SIZE(bclk_divs)) {
2494 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
2495 dspclk / wm8962->bclk);
2496 return;
2497 }
2498
2499 aif2 |= wm8962->bclk / wm8962->lrclk;
2500 dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
2501 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2502
2503 snd_soc_update_bits(codec, WM8962_CLOCKING2,
2504 WM8962_BCLK_DIV_MASK, clocking2);
2505 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
2506 WM8962_AIF_RATE_MASK, aif2);
2507}
2508
2509static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2510 enum snd_soc_bias_level level)
2511{
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2512 if (level == codec->dapm.bias_level)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2513 return 0;
2514
2515 switch (level) {
2516 case SND_SOC_BIAS_ON:
2517 break;
2518
2519 case SND_SOC_BIAS_PREPARE:
2520 /* VMID 2*50k */
2521 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2522 WM8962_VMID_SEL_MASK, 0x80);
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2523
2524 wm8962_configure_bclk(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2525 break;
2526
2527 case SND_SOC_BIAS_STANDBY:
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2528 /* VMID 2*250k */
2529 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2530 WM8962_VMID_SEL_MASK, 0x100);
Mark Brown9d40e552012-07-30 18:24:19 +0100[diff] [blame]2531
2532 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
2533 msleep(100);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2534 break;
2535
2536 case SND_SOC_BIAS_OFF:
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2537 break;
2538 }
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]2539
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2540 codec->dapm.bias_level = level;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2541 return 0;
2542}
2543
2544static const struct {
2545 int rate;
2546 int reg;
2547} sr_vals[] = {
2548 { 48000, 0 },
2549 { 44100, 0 },
2550 { 32000, 1 },
2551 { 22050, 2 },
2552 { 24000, 2 },
2553 { 16000, 3 },
2554 { 11025, 4 },
2555 { 12000, 4 },
2556 { 8000, 5 },
2557 { 88200, 6 },
2558 { 96000, 6 },
2559};
2560
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2561static int wm8962_hw_params(struct snd_pcm_substream *substream,
2562 struct snd_pcm_hw_params *params,
2563 struct snd_soc_dai *dai)
2564{
Mark Browne6968a12012-04-04 15:58:16 +0100[diff] [blame]2565 struct snd_soc_codec *codec = dai->codec;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2566 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2567 int i;
2568 int aif0 = 0;
2569 int adctl3 = 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2570
2571 wm8962->bclk = snd_soc_params_to_bclk(params);
Mark Brown4c6c0b52012-02-08 19:02:24 +0000[diff] [blame]2572 if (params_channels(params) == 1)
2573 wm8962->bclk *= 2;
2574
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2575 wm8962->lrclk = params_rate(params);
2576
2577 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2578 if (sr_vals[i].rate == wm8962->lrclk) {
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2579 adctl3 |= sr_vals[i].reg;
2580 break;
2581 }
2582 }
2583 if (i == ARRAY_SIZE(sr_vals)) {
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2584 dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2585 return -EINVAL;
2586 }
2587
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2588 if (wm8962->lrclk % 8000 == 0)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2589 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2590
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2591 switch (params_format(params)) {
2592 case SNDRV_PCM_FORMAT_S16_LE:
2593 break;
2594 case SNDRV_PCM_FORMAT_S20_3LE:
Susan Gao2b6712b2012-01-30 13:57:04 -0800[diff] [blame]2595 aif0 |= 0x4;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2596 break;
2597 case SNDRV_PCM_FORMAT_S24_LE:
Susan Gao2b6712b2012-01-30 13:57:04 -0800[diff] [blame]2598 aif0 |= 0x8;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2599 break;
2600 case SNDRV_PCM_FORMAT_S32_LE:
Susan Gao2b6712b2012-01-30 13:57:04 -0800[diff] [blame]2601 aif0 |= 0xc;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2602 break;
2603 default:
2604 return -EINVAL;
2605 }
2606
2607 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2608 WM8962_WL_MASK, aif0);
2609 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
2610 WM8962_SAMPLE_RATE_INT_MODE |
2611 WM8962_SAMPLE_RATE_MASK, adctl3);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2612
Mark Brown081413f2012-07-02 18:19:58 +0100[diff] [blame]2613 dev_dbg(codec->dev, "hw_params set BCLK %dHz LRCLK %dHz\n",
2614 wm8962->bclk, wm8962->lrclk);
2615
Mark Brown19935022012-02-16 00:46:44 -0800[diff] [blame]2616 if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
2617 wm8962_configure_bclk(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2618
2619 return 0;
2620}
2621
2622static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2623 unsigned int freq, int dir)
2624{
2625 struct snd_soc_codec *codec = dai->codec;
2626 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2627 int src;
2628
2629 switch (clk_id) {
2630 case WM8962_SYSCLK_MCLK:
2631 wm8962->sysclk = WM8962_SYSCLK_MCLK;
2632 src = 0;
2633 break;
2634 case WM8962_SYSCLK_FLL:
2635 wm8962->sysclk = WM8962_SYSCLK_FLL;
2636 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2637 break;
2638 default:
2639 return -EINVAL;
2640 }
2641
2642 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2643 src);
2644
2645 wm8962->sysclk_rate = freq;
2646
2647 return 0;
2648}
2649
2650static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2651{
2652 struct snd_soc_codec *codec = dai->codec;
2653 int aif0 = 0;
2654
2655 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2656 case SND_SOC_DAIFMT_DSP_B:
Susan Gaofbc7c622011-09-29 11:08:18 +0100[diff] [blame]2657 aif0 |= WM8962_LRCLK_INV | 3;
2658 case SND_SOC_DAIFMT_DSP_A:
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2659 aif0 |= 3;
2660
2661 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2662 case SND_SOC_DAIFMT_NB_NF:
2663 case SND_SOC_DAIFMT_IB_NF:
2664 break;
2665 default:
2666 return -EINVAL;
2667 }
2668 break;
2669
2670 case SND_SOC_DAIFMT_RIGHT_J:
2671 break;
2672 case SND_SOC_DAIFMT_LEFT_J:
2673 aif0 |= 1;
2674 break;
2675 case SND_SOC_DAIFMT_I2S:
2676 aif0 |= 2;
2677 break;
2678 default:
2679 return -EINVAL;
2680 }
2681
2682 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2683 case SND_SOC_DAIFMT_NB_NF:
2684 break;
2685 case SND_SOC_DAIFMT_IB_NF:
2686 aif0 |= WM8962_BCLK_INV;
2687 break;
2688 case SND_SOC_DAIFMT_NB_IF:
2689 aif0 |= WM8962_LRCLK_INV;
2690 break;
2691 case SND_SOC_DAIFMT_IB_IF:
2692 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2693 break;
2694 default:
2695 return -EINVAL;
2696 }
2697
2698 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2699 case SND_SOC_DAIFMT_CBM_CFM:
2700 aif0 |= WM8962_MSTR;
2701 break;
2702 case SND_SOC_DAIFMT_CBS_CFS:
2703 break;
2704 default:
2705 return -EINVAL;
2706 }
2707
2708 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2709 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2710 WM8962_LRCLK_INV, aif0);
2711
2712 return 0;
2713}
2714
2715struct _fll_div {
2716 u16 fll_fratio;
2717 u16 fll_outdiv;
2718 u16 fll_refclk_div;
2719 u16 n;
2720 u16 theta;
2721 u16 lambda;
2722};
2723
2724/* The size in bits of the FLL divide multiplied by 10
2725 * to allow rounding later */
2726#define FIXED_FLL_SIZE ((1 << 16) * 10)
2727
2728static struct {
2729 unsigned int min;
2730 unsigned int max;
2731 u16 fll_fratio;
2732 int ratio;
2733} fll_fratios[] = {
2734 { 0, 64000, 4, 16 },
2735 { 64000, 128000, 3, 8 },
2736 { 128000, 256000, 2, 4 },
2737 { 256000, 1000000, 1, 2 },
2738 { 1000000, 13500000, 0, 1 },
2739};
2740
2741static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2742 unsigned int Fout)
2743{
2744 unsigned int target;
2745 unsigned int div;
2746 unsigned int fratio, gcd_fll;
2747 int i;
2748
2749 /* Fref must be <=13.5MHz */
2750 div = 1;
2751 fll_div->fll_refclk_div = 0;
2752 while ((Fref / div) > 13500000) {
2753 div *= 2;
2754 fll_div->fll_refclk_div++;
2755
2756 if (div > 4) {
2757 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2758 Fref);
2759 return -EINVAL;
2760 }
2761 }
2762
2763 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2764
2765 /* Apply the division for our remaining calculations */
2766 Fref /= div;
2767
2768 /* Fvco should be 90-100MHz; don't check the upper bound */
2769 div = 2;
2770 while (Fout * div < 90000000) {
2771 div++;
2772 if (div > 64) {
2773 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2774 Fout);
2775 return -EINVAL;
2776 }
2777 }
2778 target = Fout * div;
2779 fll_div->fll_outdiv = div - 1;
2780
2781 pr_debug("FLL Fvco=%dHz\n", target);
2782
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]2783 /* Find an appropriate FLL_FRATIO and factor it out of the target */
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2784 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2785 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2786 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2787 fratio = fll_fratios[i].ratio;
2788 break;
2789 }
2790 }
2791 if (i == ARRAY_SIZE(fll_fratios)) {
2792 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2793 return -EINVAL;
2794 }
2795
2796 fll_div->n = target / (fratio * Fref);
2797
2798 if (target % Fref == 0) {
2799 fll_div->theta = 0;
2800 fll_div->lambda = 0;
2801 } else {
2802 gcd_fll = gcd(target, fratio * Fref);
2803
2804 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2805 / gcd_fll;
2806 fll_div->lambda = (fratio * Fref) / gcd_fll;
2807 }
2808
2809 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2810 fll_div->n, fll_div->theta, fll_div->lambda);
2811 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2812 fll_div->fll_fratio, fll_div->fll_outdiv,
2813 fll_div->fll_refclk_div);
2814
2815 return 0;
2816}
2817
Mark Brown92a43522011-04-25 18:44:01 +0100[diff] [blame]2818static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2819 unsigned int Fref, unsigned int Fout)
2820{
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2821 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2822 struct _fll_div fll_div;
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]2823 unsigned long timeout;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2824 int ret;
Mark Browna968d9d2012-01-27 19:54:03 +0000[diff] [blame]2825 int fll1 = 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2826
2827 /* Any change? */
2828 if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2829 Fout == wm8962->fll_fout)
2830 return 0;
2831
2832 if (Fout == 0) {
2833 dev_dbg(codec->dev, "FLL disabled\n");
2834
2835 wm8962->fll_fref = 0;
2836 wm8962->fll_fout = 0;
2837
2838 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2839 WM8962_FLL_ENA, 0);
2840
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]2841 pm_runtime_put(codec->dev);
2842
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2843 return 0;
2844 }
2845
2846 ret = fll_factors(&fll_div, Fref, Fout);
2847 if (ret != 0)
2848 return ret;
2849
Mark Browna968d9d2012-01-27 19:54:03 +0000[diff] [blame]2850 /* Parameters good, disable so we can reprogram */
2851 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2852
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2853 switch (fll_id) {
2854 case WM8962_FLL_MCLK:
2855 case WM8962_FLL_BCLK:
2856 case WM8962_FLL_OSC:
2857 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2858 break;
2859 case WM8962_FLL_INT:
2860 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2861 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2862 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
2863 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2864 break;
2865 default:
2866 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2867 return -EINVAL;
2868 }
2869
2870 if (fll_div.theta || fll_div.lambda)
2871 fll1 |= WM8962_FLL_FRAC;
2872
2873 /* Stop the FLL while we reconfigure */
2874 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2875
2876 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
2877 WM8962_FLL_OUTDIV_MASK |
2878 WM8962_FLL_REFCLK_DIV_MASK,
2879 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2880 (fll_div.fll_refclk_div));
2881
2882 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
2883 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2884
2885 snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
2886 snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
2887 snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
2888
Mark Brown9d7433b2014-01-30 20:32:06 +0000[diff] [blame]2889 reinit_completion(&wm8962->fll_lock);
Mark Brown4df0cb22011-08-21 17:18:52 +0100[diff] [blame]2890
Mark Browndf6ab652014-01-30 19:59:31 +0000[diff] [blame]2891 ret = pm_runtime_get_sync(codec->dev);
2892 if (ret < 0) {
2893 dev_err(codec->dev, "Failed to resume device: %d\n", ret);
2894 return ret;
2895 }
Mark Brown2a761cd2011-11-01 15:19:23 +0000[diff] [blame]2896
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2897 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2898 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
Mark Browna968d9d2012-01-27 19:54:03 +0000[diff] [blame]2899 WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2900
2901 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2902
Mark Brown346f1d42012-12-12 11:28:01 +0900[diff] [blame]2903 /* This should be a massive overestimate but go even
2904 * higher if we'll error out
2905 */
2906 if (wm8962->irq)
2907 timeout = msecs_to_jiffies(5);
2908 else
2909 timeout = msecs_to_jiffies(1);
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]2910
Mark Brown346f1d42012-12-12 11:28:01 +0900[diff] [blame]2911 timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2912 timeout);
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]2913
Mark Brown346f1d42012-12-12 11:28:01 +0900[diff] [blame]2914 if (timeout == 0 && wm8962->irq) {
2915 dev_err(codec->dev, "FLL lock timed out");
Mark Brownd6f95e52014-01-30 20:04:34 +0000[diff] [blame]2916 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2917 WM8962_FLL_ENA, 0);
2918 pm_runtime_put(codec->dev);
2919 return -ETIMEDOUT;
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]2920 }
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]2921
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2922 wm8962->fll_fref = Fref;
2923 wm8962->fll_fout = Fout;
2924 wm8962->fll_src = source;
2925
Mark Brownd6f95e52014-01-30 20:04:34 +0000[diff] [blame]2926 return 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2927}
2928
2929static int wm8962_mute(struct snd_soc_dai *dai, int mute)
2930{
2931 struct snd_soc_codec *codec = dai->codec;
2932 int val;
2933
2934 if (mute)
2935 val = WM8962_DAC_MUTE;
2936 else
2937 val = 0;
2938
2939 return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
2940 WM8962_DAC_MUTE, val);
2941}
2942
2943#define WM8962_RATES SNDRV_PCM_RATE_8000_96000
2944
2945#define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2946 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2947
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100[diff] [blame]2948static const struct snd_soc_dai_ops wm8962_dai_ops = {
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2949 .hw_params = wm8962_hw_params,
2950 .set_sysclk = wm8962_set_dai_sysclk,
2951 .set_fmt = wm8962_set_dai_fmt,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2952 .digital_mute = wm8962_mute,
2953};
2954
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]2955static struct snd_soc_dai_driver wm8962_dai = {
2956 .name = "wm8962",
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2957 .playback = {
2958 .stream_name = "Playback",
Mark Brown4c6c0b52012-02-08 19:02:24 +0000[diff] [blame]2959 .channels_min = 1,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2960 .channels_max = 2,
2961 .rates = WM8962_RATES,
2962 .formats = WM8962_FORMATS,
2963 },
2964 .capture = {
2965 .stream_name = "Capture",
Mark Brown4c6c0b52012-02-08 19:02:24 +0000[diff] [blame]2966 .channels_min = 1,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2967 .channels_max = 2,
2968 .rates = WM8962_RATES,
2969 .formats = WM8962_FORMATS,
2970 },
2971 .ops = &wm8962_dai_ops,
2972 .symmetric_rates = 1,
2973};
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2974
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]2975static void wm8962_mic_work(struct work_struct *work)
2976{
2977 struct wm8962_priv *wm8962 = container_of(work,
2978 struct wm8962_priv,
2979 mic_work.work);
2980 struct snd_soc_codec *codec = wm8962->codec;
2981 int status = 0;
2982 int irq_pol = 0;
2983 int reg;
2984
2985 reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
2986
2987 if (reg & WM8962_MICDET_STS) {
2988 status |= SND_JACK_MICROPHONE;
2989 irq_pol |= WM8962_MICD_IRQ_POL;
2990 }
2991
2992 if (reg & WM8962_MICSHORT_STS) {
2993 status |= SND_JACK_BTN_0;
2994 irq_pol |= WM8962_MICSCD_IRQ_POL;
2995 }
2996
2997 snd_soc_jack_report(wm8962->jack, status,
2998 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
2999
3000 snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
3001 WM8962_MICSCD_IRQ_POL |
3002 WM8962_MICD_IRQ_POL, irq_pol);
3003}
3004
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3005static irqreturn_t wm8962_irq(int irq, void *data)
3006{
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3007 struct device *dev = data;
3008 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3009 unsigned int mask;
3010 unsigned int active;
3011 int reg, ret;
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3012
Mark Brown7e9614e2014-01-30 19:55:45 +0000[diff] [blame]3013 ret = pm_runtime_get_sync(dev);
3014 if (ret < 0) {
3015 dev_err(dev, "Failed to resume: %d\n", ret);
3016 return IRQ_NONE;
3017 }
3018
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3019 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
3020 &mask);
3021 if (ret != 0) {
Mark Brown7e9614e2014-01-30 19:55:45 +0000[diff] [blame]3022 pm_runtime_put(dev);
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3023 dev_err(dev, "Failed to read interrupt mask: %d\n",
3024 ret);
3025 return IRQ_NONE;
3026 }
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3027
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3028 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
3029 if (ret != 0) {
Mark Brown7e9614e2014-01-30 19:55:45 +0000[diff] [blame]3030 pm_runtime_put(dev);
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3031 dev_err(dev, "Failed to read interrupt: %d\n", ret);
3032 return IRQ_NONE;
3033 }
3034
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3035 active &= ~mask;
3036
Mark Brown7e9614e2014-01-30 19:55:45 +0000[diff] [blame]3037 if (!active) {
3038 pm_runtime_put(dev);
Mark Browne6ef5872011-08-21 11:47:14 +0100[diff] [blame]3039 return IRQ_NONE;
Mark Brown7e9614e2014-01-30 19:55:45 +0000[diff] [blame]3040 }
Mark Browne6ef5872011-08-21 11:47:14 +0100[diff] [blame]3041
Mark Brown3198b9e2011-07-20 13:50:10 +0100[diff] [blame]3042 /* Acknowledge the interrupts */
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3043 ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
3044 if (ret != 0)
3045 dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
Mark Brown3198b9e2011-07-20 13:50:10 +0100[diff] [blame]3046
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]3047 if (active & WM8962_FLL_LOCK_EINT) {
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3048 dev_dbg(dev, "FLL locked\n");
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]3049 complete(&wm8962->fll_lock);
3050 }
3051
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3052 if (active & WM8962_FIFOS_ERR_EINT)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3053 dev_err(dev, "FIFO error\n");
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3054
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3055 if (active & WM8962_TEMP_SHUT_EINT) {
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3056 dev_crit(dev, "Thermal shutdown\n");
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3057
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3058 ret = regmap_read(wm8962->regmap,
3059 WM8962_THERMAL_SHUTDOWN_STATUS, &reg);
3060 if (ret != 0) {
3061 dev_warn(dev, "Failed to read thermal status: %d\n",
3062 ret);
3063 reg = 0;
3064 }
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3065
3066 if (reg & WM8962_TEMP_ERR_HP)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3067 dev_crit(dev, "Headphone thermal error\n");
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3068 if (reg & WM8962_TEMP_WARN_HP)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3069 dev_crit(dev, "Headphone thermal warning\n");
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3070 if (reg & WM8962_TEMP_ERR_SPK)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3071 dev_crit(dev, "Speaker thermal error\n");
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3072 if (reg & WM8962_TEMP_WARN_SPK)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3073 dev_crit(dev, "Speaker thermal warning\n");
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3074 }
3075
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3076 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3077 dev_dbg(dev, "Microphone event detected\n");
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3078
Mark Brown6dc47e92010-12-28 02:14:25 +0000[diff] [blame]3079#ifndef CONFIG_SND_SOC_WM8962_MODULE
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3080 trace_snd_soc_jack_irq(dev_name(dev));
Mark Brown1435b942010-12-23 01:56:20 +0000[diff] [blame]3081#endif
Mark Brown2bbb5d62010-12-05 12:50:12 +0000[diff] [blame]3082
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3083 pm_wakeup_event(dev, 300);
Mark Brown11e16eb2010-11-03 14:45:07 -0400[diff] [blame]3084
Mark Brownda72c962013-07-18 22:46:46 +0100[diff] [blame]3085 queue_delayed_work(system_power_efficient_wq,
3086 &wm8962->mic_work,
3087 msecs_to_jiffies(250));
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3088 }
3089
Mark Brown7e9614e2014-01-30 19:55:45 +0000[diff] [blame]3090 pm_runtime_put(dev);
3091
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3092 return IRQ_HANDLED;
3093}
3094
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3095/**
3096 * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3097 *
3098 * @codec: WM8962 codec
3099 * @jack: jack to report detection events on
3100 *
3101 * Enable microphone detection via IRQ on the WM8962. If GPIOs are
3102 * being used to bring out signals to the processor then only platform
3103 * data configuration is needed for WM8962 and processor GPIOs should
3104 * be configured using snd_soc_jack_add_gpios() instead.
3105 *
3106 * If no jack is supplied detection will be disabled.
3107 */
3108int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
3109{
3110 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Charles Keepaxf1a3b8d2014-02-18 15:22:18 +0000[diff] [blame]3111 struct snd_soc_dapm_context *dapm = &codec->dapm;
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3112 int irq_mask, enable;
3113
3114 wm8962->jack = jack;
3115 if (jack) {
3116 irq_mask = 0;
3117 enable = WM8962_MICDET_ENA;
3118 } else {
3119 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3120 enable = 0;
3121 }
3122
3123 snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
3124 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3125 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3126 WM8962_MICDET_ENA, enable);
3127
3128 /* Send an initial empty report */
3129 snd_soc_jack_report(wm8962->jack, 0,
3130 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3131
Charles Keepaxf1a3b8d2014-02-18 15:22:18 +0000[diff] [blame]3132 snd_soc_dapm_mutex_lock(dapm);
3133
Mark Browna5ef9882011-11-01 16:00:15 +0000[diff] [blame]3134 if (jack) {
Charles Keepaxf1a3b8d2014-02-18 15:22:18 +0000[diff] [blame]3135 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
3136 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
Mark Brown00ae3b82011-11-01 16:02:01 +0000[diff] [blame]3137 } else {
Charles Keepaxf1a3b8d2014-02-18 15:22:18 +0000[diff] [blame]3138 snd_soc_dapm_disable_pin_unlocked(dapm, "SYSCLK");
3139 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
Mark Browna5ef9882011-11-01 16:00:15 +0000[diff] [blame]3140 }
Mark Browndb0e5542011-11-01 15:59:03 +0000[diff] [blame]3141
Charles Keepaxf1a3b8d2014-02-18 15:22:18 +0000[diff] [blame]3142 snd_soc_dapm_mutex_unlock(dapm);
3143
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3144 return 0;
3145}
3146EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3147
Fabio Estevamc3e84942013-11-20 15:37:41 -0200[diff] [blame]3148#if IS_ENABLED(CONFIG_INPUT)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3149static int beep_rates[] = {
3150 500, 1000, 2000, 4000,
3151};
3152
3153static void wm8962_beep_work(struct work_struct *work)
3154{
3155 struct wm8962_priv *wm8962 =
3156 container_of(work, struct wm8962_priv, beep_work);
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3157 struct snd_soc_codec *codec = wm8962->codec;
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3158 struct snd_soc_dapm_context *dapm = &codec->dapm;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3159 int i;
3160 int reg = 0;
3161 int best = 0;
3162
3163 if (wm8962->beep_rate) {
3164 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3165 if (abs(wm8962->beep_rate - beep_rates[i]) <
3166 abs(wm8962->beep_rate - beep_rates[best]))
3167 best = i;
3168 }
3169
3170 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
3171 beep_rates[best], wm8962->beep_rate);
3172
3173 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3174
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3175 snd_soc_dapm_enable_pin(dapm, "Beep");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3176 } else {
3177 dev_dbg(codec->dev, "Disabling beep\n");
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3178 snd_soc_dapm_disable_pin(dapm, "Beep");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3179 }
3180
3181 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
3182 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3183
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3184 snd_soc_dapm_sync(dapm);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3185}
3186
3187/* For usability define a way of injecting beep events for the device -
3188 * many systems will not have a keyboard.
3189 */
3190static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3191 unsigned int code, int hz)
3192{
3193 struct snd_soc_codec *codec = input_get_drvdata(dev);
3194 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3195
3196 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
3197
3198 switch (code) {
3199 case SND_BELL:
3200 if (hz)
3201 hz = 1000;
3202 case SND_TONE:
3203 break;
3204 default:
3205 return -1;
3206 }
3207
3208 /* Kick the beep from a workqueue */
3209 wm8962->beep_rate = hz;
3210 schedule_work(&wm8962->beep_work);
3211 return 0;
3212}
3213
3214static ssize_t wm8962_beep_set(struct device *dev,
3215 struct device_attribute *attr,
3216 const char *buf, size_t count)
3217{
3218 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3219 long int time;
Mark Brown74a557e2010-11-03 09:37:06 -0400[diff] [blame]3220 int ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3221
Jingoo Hanb785a492013-07-19 16:24:59 +0900[diff] [blame]3222 ret = kstrtol(buf, 10, &time);
Mark Brown74a557e2010-11-03 09:37:06 -0400[diff] [blame]3223 if (ret != 0)
3224 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3225
3226 input_event(wm8962->beep, EV_SND, SND_TONE, time);
3227
3228 return count;
3229}
3230
3231static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
3232
3233static void wm8962_init_beep(struct snd_soc_codec *codec)
3234{
3235 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3236 int ret;
3237
Mark Browna2ce6472012-12-20 13:09:59 +0000[diff] [blame]3238 wm8962->beep = devm_input_allocate_device(codec->dev);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3239 if (!wm8962->beep) {
3240 dev_err(codec->dev, "Failed to allocate beep device\n");
3241 return;
3242 }
3243
3244 INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3245 wm8962->beep_rate = 0;
3246
3247 wm8962->beep->name = "WM8962 Beep Generator";
3248 wm8962->beep->phys = dev_name(codec->dev);
3249 wm8962->beep->id.bustype = BUS_I2C;
3250
3251 wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3252 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3253 wm8962->beep->event = wm8962_beep_event;
3254 wm8962->beep->dev.parent = codec->dev;
3255 input_set_drvdata(wm8962->beep, codec);
3256
3257 ret = input_register_device(wm8962->beep);
3258 if (ret != 0) {
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3259 wm8962->beep = NULL;
3260 dev_err(codec->dev, "Failed to register beep device\n");
3261 }
3262
3263 ret = device_create_file(codec->dev, &dev_attr_beep);
3264 if (ret != 0) {
3265 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
3266 ret);
3267 }
3268}
3269
3270static void wm8962_free_beep(struct snd_soc_codec *codec)
3271{
3272 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3273
3274 device_remove_file(codec->dev, &dev_attr_beep);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3275 cancel_work_sync(&wm8962->beep_work);
3276 wm8962->beep = NULL;
3277
3278 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3279}
3280#else
3281static void wm8962_init_beep(struct snd_soc_codec *codec)
3282{
3283}
3284
3285static void wm8962_free_beep(struct snd_soc_codec *codec)
3286{
3287}
3288#endif
3289
Mark Brown78b78f52013-10-17 15:04:21 +0100[diff] [blame]3290static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio)
Mark Brown8ca2aa92010-10-01 17:46:37 -0700[diff] [blame]3291{
3292 int mask = 0;
3293 int val = 0;
3294
3295 /* Some of the GPIOs are behind MFP configuration and need to
3296 * be put into GPIO mode. */
3297 switch (gpio) {
3298 case 2:
3299 mask = WM8962_CLKOUT2_SEL_MASK;
3300 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3301 break;
3302 case 3:
3303 mask = WM8962_CLKOUT3_SEL_MASK;
3304 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3305 break;
3306 default:
3307 break;
3308 }
3309
3310 if (mask)
Mark Brown78b78f52013-10-17 15:04:21 +0100[diff] [blame]3311 regmap_update_bits(wm8962->regmap, WM8962_ANALOGUE_CLOCKING1,
3312 mask, val);
Mark Brown8ca2aa92010-10-01 17:46:37 -0700[diff] [blame]3313}
3314
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3315#ifdef CONFIG_GPIOLIB
3316static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
3317{
3318 return container_of(chip, struct wm8962_priv, gpio_chip);
3319}
3320
3321static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3322{
3323 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3324
3325 /* The WM8962 GPIOs aren't linearly numbered. For simplicity
3326 * we export linear numbers and error out if the unsupported
3327 * ones are requsted.
3328 */
3329 switch (offset + 1) {
3330 case 2:
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3331 case 3:
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3332 case 5:
3333 case 6:
3334 break;
3335 default:
3336 return -EINVAL;
3337 }
3338
Mark Brown78b78f52013-10-17 15:04:21 +0100[diff] [blame]3339 wm8962_set_gpio_mode(wm8962, offset + 1);
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3340
3341 return 0;
3342}
3343
3344static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3345{
3346 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3347 struct snd_soc_codec *codec = wm8962->codec;
3348
3349 snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
Mark Brownd71bb812011-01-31 13:41:03 +0000[diff] [blame]3350 WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3351}
3352
3353static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3354 unsigned offset, int value)
3355{
3356 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3357 struct snd_soc_codec *codec = wm8962->codec;
Axel Linfe75fe02011-12-30 23:38:03 +0800[diff] [blame]3358 int ret, val;
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3359
3360 /* Force function 1 (logic output) */
3361 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3362
Axel Linfe75fe02011-12-30 23:38:03 +0800[diff] [blame]3363 ret = snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3364 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3365 if (ret < 0)
3366 return ret;
3367
3368 return 0;
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3369}
3370
3371static struct gpio_chip wm8962_template_chip = {
3372 .label = "wm8962",
3373 .owner = THIS_MODULE,
3374 .request = wm8962_gpio_request,
3375 .direction_output = wm8962_gpio_direction_out,
3376 .set = wm8962_gpio_set,
3377 .can_sleep = 1,
3378};
3379
3380static void wm8962_init_gpio(struct snd_soc_codec *codec)
3381{
3382 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Nicolin Chene75a52c2013-06-06 19:38:45 +0800[diff] [blame]3383 struct wm8962_pdata *pdata = &wm8962->pdata;
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3384 int ret;
3385
3386 wm8962->gpio_chip = wm8962_template_chip;
3387 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3388 wm8962->gpio_chip.dev = codec->dev;
3389
Nicolin Chene75a52c2013-06-06 19:38:45 +0800[diff] [blame]3390 if (pdata->gpio_base)
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3391 wm8962->gpio_chip.base = pdata->gpio_base;
3392 else
3393 wm8962->gpio_chip.base = -1;
3394
3395 ret = gpiochip_add(&wm8962->gpio_chip);
3396 if (ret != 0)
3397 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
3398}
3399
3400static void wm8962_free_gpio(struct snd_soc_codec *codec)
3401{
3402 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3403 int ret;
3404
3405 ret = gpiochip_remove(&wm8962->gpio_chip);
3406 if (ret != 0)
3407 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
3408}
3409#else
3410static void wm8962_init_gpio(struct snd_soc_codec *codec)
3411{
3412}
3413
3414static void wm8962_free_gpio(struct snd_soc_codec *codec)
3415{
3416}
3417#endif
3418
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3419static int wm8962_probe(struct snd_soc_codec *codec)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3420{
3421 int ret;
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3422 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brownca504102013-10-17 14:56:13 +0100[diff] [blame]3423 int i;
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]3424 bool dmicclk, dmicdat;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3425
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3426 wm8962->codec = codec;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3427
3428 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3429 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3430 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3431 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3432 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3433 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3434 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3435 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3436
3437 /* This should really be moved into the regulator core */
3438 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3439 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
3440 &wm8962->disable_nb[i]);
3441 if (ret != 0) {
3442 dev_err(codec->dev,
3443 "Failed to register regulator notifier: %d\n",
3444 ret);
3445 }
3446 }
3447
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3448 wm8962_add_widgets(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3449
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]3450 /* Save boards having to disable DMIC when not in use */
3451 dmicclk = false;
3452 dmicdat = false;
3453 for (i = 0; i < WM8962_MAX_GPIO; i++) {
3454 switch (snd_soc_read(codec, WM8962_GPIO_BASE + i)
3455 & WM8962_GP2_FN_MASK) {
3456 case WM8962_GPIO_FN_DMICCLK:
3457 dmicclk = true;
3458 break;
3459 case WM8962_GPIO_FN_DMICDAT:
3460 dmicdat = true;
3461 break;
3462 default:
3463 break;
3464 }
3465 }
3466 if (!dmicclk || !dmicdat) {
3467 dev_dbg(codec->dev, "DMIC not in use, disabling\n");
3468 snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT");
3469 }
3470 if (dmicclk != dmicdat)
3471 dev_warn(codec->dev, "DMIC GPIOs partially configured\n");
3472
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3473 wm8962_init_beep(codec);
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3474 wm8962_init_gpio(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3475
3476 return 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3477}
3478
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3479static int wm8962_remove(struct snd_soc_codec *codec)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3480{
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3481 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3482 int i;
3483
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3484 cancel_delayed_work_sync(&wm8962->mic_work);
3485
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3486 wm8962_free_gpio(codec);
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3487 wm8962_free_beep(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3488 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3489 regulator_unregister_notifier(wm8962->supplies[i].consumer,
3490 &wm8962->disable_nb[i]);
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3491
3492 return 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3493}
3494
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3495static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
3496 .probe = wm8962_probe,
3497 .remove = wm8962_remove,
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3498 .set_bias_level = wm8962_set_bias_level,
Mark Brown92a43522011-04-25 18:44:01 +0100[diff] [blame]3499 .set_pll = wm8962_set_fll,
Mark Brown2693efd2012-01-27 19:36:45 +0000[diff] [blame]3500 .idle_bias_off = true,
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3501};
3502
Mark Brown182c51c2012-01-24 21:07:55 +0000[diff] [blame]3503/* Improve power consumption for IN4 DC measurement mode */
3504static const struct reg_default wm8962_dc_measure[] = {
3505 { 0xfd, 0x1 },
3506 { 0xcc, 0x40 },
3507 { 0xfd, 0 },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3508};
3509
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3510static const struct regmap_config wm8962_regmap = {
3511 .reg_bits = 16,
3512 .val_bits = 16,
3513
3514 .max_register = WM8962_MAX_REGISTER,
3515 .reg_defaults = wm8962_reg,
3516 .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3517 .volatile_reg = wm8962_volatile_register,
3518 .readable_reg = wm8962_readable_register,
3519 .cache_type = REGCACHE_RBTREE,
3520};
3521
Nicolin Chend74e9e72013-06-07 11:23:27 +0800[diff] [blame]3522static int wm8962_set_pdata_from_of(struct i2c_client *i2c,
3523 struct wm8962_pdata *pdata)
3524{
3525 const struct device_node *np = i2c->dev.of_node;
3526 u32 val32;
3527 int i;
3528
3529 if (of_property_read_bool(np, "spk-mono"))
3530 pdata->spk_mono = true;
3531
3532 if (of_property_read_u32(np, "mic-cfg", &val32) >= 0)
3533 pdata->mic_cfg = val32;
3534
3535 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init,
3536 ARRAY_SIZE(pdata->gpio_init)) >= 0)
3537 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) {
3538 /*
3539 * The range of GPIO register value is [0x0, 0xffff]
3540 * While the default value of each register is 0x0
3541 * Any other value will be regarded as default value
3542 */
3543 if (pdata->gpio_init[i] > 0xffff)
3544 pdata->gpio_init[i] = 0x0;
3545 }
3546
3547 return 0;
3548}
3549
Bill Pemberton7a79e942012-12-07 09:26:37 -0500[diff] [blame]3550static int wm8962_i2c_probe(struct i2c_client *i2c,
3551 const struct i2c_device_id *id)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3552{
Mark Brown182c51c2012-01-24 21:07:55 +0000[diff] [blame]3553 struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3554 struct wm8962_priv *wm8962;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3555 unsigned int reg;
Mark Brownca504102013-10-17 14:56:13 +0100[diff] [blame]3556 int ret, i, irq_pol, trigger;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3557
Mark Brownbe086aa2011-11-27 19:56:52 +0000[diff] [blame]3558 wm8962 = devm_kzalloc(&i2c->dev, sizeof(struct wm8962_priv),
3559 GFP_KERNEL);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3560 if (wm8962 == NULL)
3561 return -ENOMEM;
3562
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3563 i2c_set_clientdata(i2c, wm8962);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3564
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3565 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3566 init_completion(&wm8962->fll_lock);
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3567 wm8962->irq = i2c->irq;
3568
Nicolin Chene75a52c2013-06-06 19:38:45 +0800[diff] [blame]3569 /* If platform data was supplied, update the default data in priv */
Nicolin Chend74e9e72013-06-07 11:23:27 +0800[diff] [blame]3570 if (pdata) {
Nicolin Chene75a52c2013-06-06 19:38:45 +0800[diff] [blame]3571 memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata));
Nicolin Chend74e9e72013-06-07 11:23:27 +0800[diff] [blame]3572 } else if (i2c->dev.of_node) {
3573 ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata);
3574 if (ret != 0)
3575 return ret;
3576 }
Nicolin Chene75a52c2013-06-06 19:38:45 +0800[diff] [blame]3577
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3578 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3579 wm8962->supplies[i].supply = wm8962_supply_names[i];
3580
Sachin Kamat92437cb2012-11-26 17:19:35 +0530[diff] [blame]3581 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3582 wm8962->supplies);
3583 if (ret != 0) {
3584 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
Mark Brownbe086aa2011-11-27 19:56:52 +0000[diff] [blame]3585 goto err;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3586 }
3587
3588 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3589 wm8962->supplies);
3590 if (ret != 0) {
3591 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
Sachin Kamat92437cb2012-11-26 17:19:35 +0530[diff] [blame]3592 return ret;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3593 }
3594
Sachin Kamatb439c6d2012-11-26 17:19:44 +0530[diff] [blame]3595 wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap);
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3596 if (IS_ERR(wm8962->regmap)) {
3597 ret = PTR_ERR(wm8962->regmap);
3598 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3599 goto err_enable;
3600 }
3601
3602 /*
3603 * We haven't marked the chip revision as volatile due to
3604 * sharing a register with the right input volume; explicitly
3605 * bypass the cache to read it.
3606 */
3607 regcache_cache_bypass(wm8962->regmap, true);
3608
3609 ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, &reg);
3610 if (ret < 0) {
3611 dev_err(&i2c->dev, "Failed to read ID register\n");
Sachin Kamatb439c6d2012-11-26 17:19:44 +0530[diff] [blame]3612 goto err_enable;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3613 }
3614 if (reg != 0x6243) {
3615 dev_err(&i2c->dev,
Axel Lin905b4192012-02-16 10:33:45 +0800[diff] [blame]3616 "Device is not a WM8962, ID %x != 0x6243\n", reg);
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3617 ret = -EINVAL;
Sachin Kamatb439c6d2012-11-26 17:19:44 +0530[diff] [blame]3618 goto err_enable;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3619 }
3620
3621 ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, &reg);
3622 if (ret < 0) {
3623 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3624 ret);
Sachin Kamatb439c6d2012-11-26 17:19:44 +0530[diff] [blame]3625 goto err_enable;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3626 }
3627
3628 dev_info(&i2c->dev, "customer id %x revision %c\n",
3629 (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3630 ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3631 + 'A');
3632
3633 regcache_cache_bypass(wm8962->regmap, false);
3634
3635 ret = wm8962_reset(wm8962);
3636 if (ret < 0) {
3637 dev_err(&i2c->dev, "Failed to issue reset\n");
Sachin Kamatb439c6d2012-11-26 17:19:44 +0530[diff] [blame]3638 goto err_enable;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3639 }
3640
Mark Brown78b78f52013-10-17 15:04:21 +0100[diff] [blame]3641 /* SYSCLK defaults to on; make sure it is off so we can safely
3642 * write to registers if the device is declocked.
3643 */
3644 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3645 WM8962_SYSCLK_ENA, 0);
3646
3647 /* Ensure we have soft control over all registers */
3648 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3649 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3650
3651 /* Ensure that the oscillator and PLLs are disabled */
3652 regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3653 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3654 0);
3655
3656 /* Apply static configuration for GPIOs */
Nicolin Chenb5ef3f22013-10-29 17:06:27 +0800[diff] [blame]3657 for (i = 0; i < ARRAY_SIZE(wm8962->pdata.gpio_init); i++)
3658 if (wm8962->pdata.gpio_init[i]) {
Mark Brown78b78f52013-10-17 15:04:21 +0100[diff] [blame]3659 wm8962_set_gpio_mode(wm8962, i + 1);
3660 regmap_write(wm8962->regmap, 0x200 + i,
Nicolin Chenb5ef3f22013-10-29 17:06:27 +0800[diff] [blame]3661 wm8962->pdata.gpio_init[i] & 0xffff);
Mark Brown78b78f52013-10-17 15:04:21 +0100[diff] [blame]3662 }
3663
3664
3665 /* Put the speakers into mono mode? */
Nicolin Chenb5ef3f22013-10-29 17:06:27 +0800[diff] [blame]3666 if (wm8962->pdata.spk_mono)
Mark Brown78b78f52013-10-17 15:04:21 +0100[diff] [blame]3667 regmap_update_bits(wm8962->regmap, WM8962_CLASS_D_CONTROL_2,
3668 WM8962_SPK_MONO_MASK, WM8962_SPK_MONO);
3669
3670 /* Micbias setup, detection enable and detection
3671 * threasholds. */
Nicolin Chenb5ef3f22013-10-29 17:06:27 +0800[diff] [blame]3672 if (wm8962->pdata.mic_cfg)
Mark Brown78b78f52013-10-17 15:04:21 +0100[diff] [blame]3673 regmap_update_bits(wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4,
3674 WM8962_MICDET_ENA |
3675 WM8962_MICDET_THR_MASK |
3676 WM8962_MICSHORT_THR_MASK |
3677 WM8962_MICBIAS_LVL,
Nicolin Chenb5ef3f22013-10-29 17:06:27 +0800[diff] [blame]3678 wm8962->pdata.mic_cfg);
Mark Brown78b78f52013-10-17 15:04:21 +0100[diff] [blame]3679
3680 /* Latch volume update bits */
3681 regmap_update_bits(wm8962->regmap, WM8962_LEFT_INPUT_VOLUME,
3682 WM8962_IN_VU, WM8962_IN_VU);
3683 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME,
3684 WM8962_IN_VU, WM8962_IN_VU);
3685 regmap_update_bits(wm8962->regmap, WM8962_LEFT_ADC_VOLUME,
3686 WM8962_ADC_VU, WM8962_ADC_VU);
3687 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_ADC_VOLUME,
3688 WM8962_ADC_VU, WM8962_ADC_VU);
3689 regmap_update_bits(wm8962->regmap, WM8962_LEFT_DAC_VOLUME,
3690 WM8962_DAC_VU, WM8962_DAC_VU);
3691 regmap_update_bits(wm8962->regmap, WM8962_RIGHT_DAC_VOLUME,
3692 WM8962_DAC_VU, WM8962_DAC_VU);
3693 regmap_update_bits(wm8962->regmap, WM8962_SPKOUTL_VOLUME,
3694 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3695 regmap_update_bits(wm8962->regmap, WM8962_SPKOUTR_VOLUME,
3696 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3697 regmap_update_bits(wm8962->regmap, WM8962_HPOUTL_VOLUME,
3698 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3699 regmap_update_bits(wm8962->regmap, WM8962_HPOUTR_VOLUME,
3700 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3701
3702 /* Stereo control for EQ */
3703 regmap_update_bits(wm8962->regmap, WM8962_EQ1,
3704 WM8962_EQ_SHARED_COEFF, 0);
3705
3706 /* Don't debouce interrupts so we don't need SYSCLK */
3707 regmap_update_bits(wm8962->regmap, WM8962_IRQ_DEBOUNCE,
3708 WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3709 WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3710 0);
3711
Nicolin Chene75a52c2013-06-06 19:38:45 +0800[diff] [blame]3712 if (wm8962->pdata.in4_dc_measure) {
Mark Brown182c51c2012-01-24 21:07:55 +0000[diff] [blame]3713 ret = regmap_register_patch(wm8962->regmap,
3714 wm8962_dc_measure,
3715 ARRAY_SIZE(wm8962_dc_measure));
3716 if (ret != 0)
3717 dev_err(&i2c->dev,
3718 "Failed to configure for DC mesurement: %d\n",
3719 ret);
3720 }
3721
Mark Brownca504102013-10-17 14:56:13 +0100[diff] [blame]3722 if (wm8962->irq) {
Nicolin Chenb5ef3f22013-10-29 17:06:27 +0800[diff] [blame]3723 if (wm8962->pdata.irq_active_low) {
Mark Brownca504102013-10-17 14:56:13 +0100[diff] [blame]3724 trigger = IRQF_TRIGGER_LOW;
3725 irq_pol = WM8962_IRQ_POL;
3726 } else {
3727 trigger = IRQF_TRIGGER_HIGH;
3728 irq_pol = 0;
3729 }
3730
3731 regmap_update_bits(wm8962->regmap, WM8962_INTERRUPT_CONTROL,
3732 WM8962_IRQ_POL, irq_pol);
3733
3734 ret = devm_request_threaded_irq(&i2c->dev, wm8962->irq, NULL,
3735 wm8962_irq,
3736 trigger | IRQF_ONESHOT,
3737 "wm8962", &i2c->dev);
3738 if (ret != 0) {
3739 dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
3740 wm8962->irq, ret);
3741 wm8962->irq = 0;
3742 /* Non-fatal */
3743 } else {
3744 /* Enable some IRQs by default */
3745 regmap_update_bits(wm8962->regmap,
3746 WM8962_INTERRUPT_STATUS_2_MASK,
3747 WM8962_FLL_LOCK_EINT |
3748 WM8962_TEMP_SHUT_EINT |
3749 WM8962_FIFOS_ERR_EINT, 0);
3750 }
3751 }
3752
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]3753 pm_runtime_enable(&i2c->dev);
3754 pm_request_idle(&i2c->dev);
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3755
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3756 ret = snd_soc_register_codec(&i2c->dev,
3757 &soc_codec_dev_wm8962, &wm8962_dai, 1);
3758 if (ret < 0)
Sachin Kamatb439c6d2012-11-26 17:19:44 +0530[diff] [blame]3759 goto err_enable;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3760
Nicolin Chen50bfcf2d2013-11-14 11:59:21 +0800[diff] [blame]3761 regcache_cache_only(wm8962->regmap, true);
3762
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3763 /* The drivers should power up as needed */
3764 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3765
3766 return 0;
3767
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3768err_enable:
3769 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
Mark Brownbe086aa2011-11-27 19:56:52 +0000[diff] [blame]3770err:
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3771 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3772}
3773
Bill Pemberton7a79e942012-12-07 09:26:37 -0500[diff] [blame]3774static int wm8962_i2c_remove(struct i2c_client *client)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3775{
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3776 snd_soc_unregister_codec(&client->dev);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3777 return 0;
3778}
3779
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]3780#ifdef CONFIG_PM_RUNTIME
3781static int wm8962_runtime_resume(struct device *dev)
3782{
3783 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3784 int ret;
3785
3786 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3787 wm8962->supplies);
3788 if (ret != 0) {
3789 dev_err(dev,
3790 "Failed to enable supplies: %d\n", ret);
3791 return ret;
3792 }
3793
3794 regcache_cache_only(wm8962->regmap, false);
Mark Browne4dd7672012-07-11 19:03:48 +0100[diff] [blame]3795
3796 wm8962_reset(wm8962);
3797
Mark Brown9c24b162013-06-07 16:19:58 +0100[diff] [blame]3798 /* SYSCLK defaults to on; make sure it is off so we can safely
3799 * write to registers if the device is declocked.
3800 */
3801 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3802 WM8962_SYSCLK_ENA, 0);
3803
3804 /* Ensure we have soft control over all registers */
3805 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3806 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3807
3808 /* Ensure that the oscillator and PLLs are disabled */
3809 regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3810 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3811 0);
3812
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]3813 regcache_sync(wm8962->regmap);
3814
Nicolin Chenf5055f92013-06-14 19:49:06 +0800[diff] [blame]3815 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3816 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
3817 WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
3818
3819 /* Bias enable at 2*5k (fast start-up) */
3820 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3821 WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK,
3822 WM8962_BIAS_ENA | 0x180);
3823
3824 msleep(5);
3825
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]3826 return 0;
3827}
3828
3829static int wm8962_runtime_suspend(struct device *dev)
3830{
3831 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3832
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]3833 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3834 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
3835
3836 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3837 WM8962_STARTUP_BIAS_ENA |
3838 WM8962_VMID_BUF_ENA, 0);
3839
3840 regcache_cache_only(wm8962->regmap, true);
3841
3842 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
3843 wm8962->supplies);
3844
3845 return 0;
3846}
3847#endif
3848
3849static struct dev_pm_ops wm8962_pm = {
3850 SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
3851};
3852
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3853static const struct i2c_device_id wm8962_i2c_id[] = {
3854 { "wm8962", 0 },
3855 { }
3856};
3857MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3858
Fabio Estevam5ce56832012-12-12 23:28:04 -0200[diff] [blame]3859static const struct of_device_id wm8962_of_match[] = {
3860 { .compatible = "wlf,wm8962", },
3861 { }
3862};
3863MODULE_DEVICE_TABLE(of, wm8962_of_match);
3864
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3865static struct i2c_driver wm8962_i2c_driver = {
3866 .driver = {
Mark Brownea738ba2010-09-20 20:36:19 +0100[diff] [blame]3867 .name = "wm8962",
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3868 .owner = THIS_MODULE,
Fabio Estevam5ce56832012-12-12 23:28:04 -0200[diff] [blame]3869 .of_match_table = wm8962_of_match,
Mark Brownd23031a2012-02-01 12:48:59 +0000[diff] [blame]3870 .pm = &wm8962_pm,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3871 },
3872 .probe = wm8962_i2c_probe,
Bill Pemberton7a79e942012-12-07 09:26:37 -0500[diff] [blame]3873 .remove = wm8962_i2c_remove,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3874 .id_table = wm8962_i2c_id,
3875};
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3876
Mark Brown9d50a762012-02-16 22:43:39 -0800[diff] [blame]3877module_i2c_driver(wm8962_i2c_driver);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3878
3879MODULE_DESCRIPTION("ASoC WM8962 driver");
3880MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3881MODULE_LICENSE("GPL");