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Juha Yrjola4bbbc1a2006-06-26 16:16:16 -07001/*
2 * General-Purpose Memory Controller for OMAP2
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H
13
Paul Walmsleyfd1dc872008-10-06 15:49:17 +030014/* Maximum Number of Chip Selects */
15#define GPMC_CS_NUM 8
16
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070017#define GPMC_CS_CONFIG1 0x00
18#define GPMC_CS_CONFIG2 0x04
19#define GPMC_CS_CONFIG3 0x08
20#define GPMC_CS_CONFIG4 0x0c
21#define GPMC_CS_CONFIG5 0x10
22#define GPMC_CS_CONFIG6 0x14
23#define GPMC_CS_CONFIG7 0x18
24#define GPMC_CS_NAND_COMMAND 0x1c
25#define GPMC_CS_NAND_ADDRESS 0x20
26#define GPMC_CS_NAND_DATA 0x24
27
Tony Lindgren646e3ed2008-10-06 15:49:36 +030028#define GPMC_CONFIG 0x50
29#define GPMC_STATUS 0x54
Vimal Singhc2798e92010-02-15 10:03:33 -080030#define GPMC_CS0_BASE 0x60
31#define GPMC_CS_SIZE 0x30
Tony Lindgren646e3ed2008-10-06 15:49:36 +030032
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070033#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
David Brownell1c22cc12006-12-06 17:13:55 -080034#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070035#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
36#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
David Brownell1c22cc12006-12-06 17:13:55 -080037#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070038#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
39#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
40#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
41#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
42#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
43#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
44#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
45#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
46#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
47#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
48#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
49#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
Vimal Singh8fe8acb2009-12-11 16:16:35 -080050#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2)
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070051#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
52#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
53#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
54#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
55#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
56#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
Rajendra Nayaka2d3e7b2008-09-26 17:47:33 +053057#define GPMC_CONFIG7_CSVALID (1 << 6)
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070058
59/*
60 * Note that all values in this struct are in nanoseconds, while
61 * the register values are in gpmc_fck cycles.
62 */
63struct gpmc_timings {
64 /* Minimum clock period for synchronous mode */
65 u16 sync_clk;
66
67 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
68 u16 cs_on; /* Assertion time */
69 u16 cs_rd_off; /* Read deassertion time */
70 u16 cs_wr_off; /* Write deassertion time */
71
72 /* ADV signal timings corresponding to GPMC_CONFIG3 */
73 u16 adv_on; /* Assertion time */
74 u16 adv_rd_off; /* Read deassertion time */
75 u16 adv_wr_off; /* Write deassertion time */
76
77 /* WE signals timings corresponding to GPMC_CONFIG4 */
78 u16 we_on; /* WE assertion time */
79 u16 we_off; /* WE deassertion time */
80
81 /* OE signals timings corresponding to GPMC_CONFIG4 */
82 u16 oe_on; /* OE assertion time */
83 u16 oe_off; /* OE deassertion time */
84
85 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
86 u16 page_burst_access; /* Multiple access word delay */
87 u16 access; /* Start-cycle to first data valid delay */
88 u16 rd_cycle; /* Total read cycle time */
89 u16 wr_cycle; /* Total write cycle time */
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030090
91 /* The following are only on OMAP3430 */
92 u16 wr_access; /* WRACCESSTIME */
93 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -070094};
95
96extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
Paul Walmsleyfd1dc872008-10-06 15:49:17 +030097extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
Kai Svahn23300592007-01-26 12:29:40 -080098extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
99extern unsigned long gpmc_get_fclk_period(void);
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -0700100
101extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
102extern u32 gpmc_cs_read_reg(int cs, int idx);
103extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
104extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
Imre Deakf37e4582006-09-25 12:41:33 +0300105extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
106extern void gpmc_cs_free(int cs);
Tony Lindgren39b8e692006-12-12 23:02:43 -0800107extern int gpmc_cs_set_reserved(int cs, int reserved);
Tony Lindgrenf4e4c322006-12-07 13:57:38 -0800108extern int gpmc_cs_reserved(int cs);
vimal singh59e9c5a2009-07-13 16:26:24 +0530109extern int gpmc_prefetch_enable(int cs, int dma_mode,
110 unsigned int u32_count, int is_write);
111extern void gpmc_prefetch_reset(void);
112extern int gpmc_prefetch_status(void);
Rajendra Nayaka2d3e7b2008-09-26 17:47:33 +0530113extern void omap3_gpmc_save_context(void);
114extern void omap3_gpmc_restore_context(void);
Felipe Balbi2586ef02010-02-15 10:03:33 -0800115extern void gpmc_init(void);
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -0700116
117#endif