blob: db1ef585606325420bd42e4096f2215ecd37cc91 [file] [log] [blame]
Thomas Petazzonic7841472013-07-30 17:44:50 +02001/*
2 * Device Tree file for Marvell RD-AXPWiFiAP.
3 *
4 * Note: this board is shipped with a new generation boot loader that
5 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
6 * is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be
7 * used.
8 *
9 * Copyright (C) 2013 Marvell
10 *
11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18/dts-v1/;
Thomas Petazzoni29e74f82014-02-11 18:07:12 +010019#include <dt-bindings/gpio/gpio.h>
Ezequiel Garciad10ff4d2013-08-06 14:09:42 -030020#include "armada-xp-mv78230.dtsi"
Thomas Petazzonic7841472013-07-30 17:44:50 +020021
22/ {
23 model = "Marvell RD-AXPWiFiAP";
24 compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25
26 chosen {
27 bootargs = "console=ttyS0,115200 earlyprintk";
28 };
29
30 memory {
31 device_type = "memory";
32 reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
33 };
34
35 soc {
Ezequiel Garciad10ff4d2013-08-06 14:09:42 -030036 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
37 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
38
39 pcie-controller {
40 status = "okay";
41
42 /* First mini-PCIe port */
43 pcie@1,0 {
44 /* Port 0, Lane 0 */
45 status = "okay";
46 };
47
48 /* Second mini-PCIe port */
49 pcie@2,0 {
50 /* Port 0, Lane 1 */
51 status = "okay";
52 };
53
54 /* Renesas uPD720202 USB 3.0 controller */
55 pcie@3,0 {
56 /* Port 0, Lane 3 */
57 status = "okay";
58 };
59 };
Thomas Petazzonic7841472013-07-30 17:44:50 +020060
61 internal-regs {
62 pinctrl {
63 pinctrl-0 = <&pmx_phy_int>;
64 pinctrl-names = "default";
65
66 pmx_ge0: pmx-ge0 {
67 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
68 "mpp4", "mpp5", "mpp6", "mpp7",
69 "mpp8", "mpp9", "mpp10", "mpp11";
70 marvell,function = "ge0";
71 };
72
73 pmx_ge1: pmx-ge1 {
74 marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
75 "mpp16", "mpp17", "mpp18", "mpp19",
76 "mpp20", "mpp21", "mpp22", "mpp23";
77 marvell,function = "ge1";
78 };
79
80 pmx_keys: pmx-keys {
81 marvell,pins = "mpp33";
82 marvell,function = "gpio";
83 };
84
85 pmx_spi: pmx-spi {
86 marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
87 marvell,function = "spi";
88 };
89
90 pmx_phy_int: pmx-phy-int {
91 marvell,pins = "mpp32";
92 marvell,function = "gpio";
93 };
94 };
95
96 serial@12000 {
97 clock-frequency = <250000000>;
98 status = "okay";
99 };
100
101 serial@12100 {
102 clock-frequency = <250000000>;
103 status = "okay";
104 };
105
106 sata@a0000 {
107 nr-ports = <1>;
108 status = "okay";
109 };
110
111 mdio {
112 phy0: ethernet-phy@0 {
113 reg = <0>;
114 };
115
116 phy1: ethernet-phy@1 {
117 reg = <1>;
118 };
119 };
120
121 ethernet@70000 {
122 pinctrl-0 = <&pmx_ge0>;
123 pinctrl-names = "default";
124 status = "okay";
125 phy = <&phy0>;
126 phy-mode = "rgmii-id";
127 };
128 ethernet@74000 {
129 pinctrl-0 = <&pmx_ge1>;
130 pinctrl-names = "default";
131 status = "okay";
132 phy = <&phy1>;
133 phy-mode = "rgmii-id";
134 };
135
136 spi0: spi@10600 {
137 status = "okay";
138 pinctrl-0 = <&pmx_spi>;
139 pinctrl-names = "default";
140
141 spi-flash@0 {
142 #address-cells = <1>;
143 #size-cells = <1>;
144 compatible = "n25q128a13";
145 reg = <0>; /* Chip select 0 */
146 spi-max-frequency = <108000000>;
147 };
148 };
Thomas Petazzonic7841472013-07-30 17:44:50 +0200149 };
150 };
151
152 gpio_keys {
153 compatible = "gpio-keys";
154 #address-cells = <1>;
155 #size-cells = <0>;
156 pinctrl-0 = <&pmx_keys>;
157 pinctrl-names = "default";
158
159 button@1 {
160 label = "Factory Reset Button";
161 linux,code = <141>; /* KEY_SETUP */
Thomas Petazzoni29e74f82014-02-11 18:07:12 +0100162 gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
Thomas Petazzonic7841472013-07-30 17:44:50 +0200163 };
164 };
165};