Sergei Shtylyov | b356e97 | 2014-02-18 03:12:43 +0300 | [diff] [blame] | 1 | * Renesas Electronics SH EtherMAC |
| 2 | |
| 3 | This file provides information on what the device node for the SH EtherMAC |
| 4 | interface contains. |
| 5 | |
| 6 | Required properties: |
| 7 | - compatible: "renesas,gether-r8a7740" if the device is a part of R8A7740 SoC. |
| 8 | "renesas,ether-r8a7778" if the device is a part of R8A7778 SoC. |
| 9 | "renesas,ether-r8a7779" if the device is a part of R8A7779 SoC. |
| 10 | "renesas,ether-r8a7790" if the device is a part of R8A7790 SoC. |
| 11 | "renesas,ether-r8a7791" if the device is a part of R8A7791 SoC. |
Hisashi Nakamura | 9488e1e | 2014-11-13 15:59:07 +0900 | [diff] [blame] | 12 | "renesas,ether-r8a7793" if the device is a part of R8A7793 SoC. |
Hisashi Nakamura | 0f76b9d | 2014-08-01 17:03:00 +0200 | [diff] [blame] | 13 | "renesas,ether-r8a7794" if the device is a part of R8A7794 SoC. |
Sergei Shtylyov | b356e97 | 2014-02-18 03:12:43 +0300 | [diff] [blame] | 14 | "renesas,ether-r7s72100" if the device is a part of R7S72100 SoC. |
| 15 | - reg: offset and length of (1) the E-DMAC/feLic register block (required), |
| 16 | (2) the TSU register block (optional). |
| 17 | - interrupts: interrupt specifier for the sole interrupt. |
| 18 | - phy-mode: see ethernet.txt file in the same directory. |
| 19 | - phy-handle: see ethernet.txt file in the same directory. |
| 20 | - #address-cells: number of address cells for the MDIO bus, must be equal to 1. |
| 21 | - #size-cells: number of size cells on the MDIO bus, must be equal to 0. |
| 22 | - clocks: clock phandle and specifier pair. |
| 23 | - pinctrl-0: phandle, referring to a default pin configuration node. |
| 24 | |
| 25 | Optional properties: |
| 26 | - interrupt-parent: the phandle for the interrupt controller that services |
| 27 | interrupts for this device. |
| 28 | - pinctrl-names: pin configuration state name ("default"). |
| 29 | - renesas,no-ether-link: boolean, specify when a board does not provide a proper |
| 30 | Ether LINK signal. |
| 31 | - renesas,ether-link-active-low: boolean, specify when the Ether LINK signal is |
| 32 | active-low instead of normal active-high. |
| 33 | |
| 34 | Example (Lager board): |
| 35 | |
| 36 | ethernet@ee700000 { |
| 37 | compatible = "renesas,ether-r8a7790"; |
| 38 | reg = <0 0xee700000 0 0x400>; |
| 39 | interrupt-parent = <&gic>; |
| 40 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; |
| 41 | clocks = <&mstp8_clks R8A7790_CLK_ETHER>; |
| 42 | phy-mode = "rmii"; |
| 43 | phy-handle = <&phy1>; |
| 44 | pinctrl-0 = <ðer_pins>; |
| 45 | pinctrl-names = "default"; |
| 46 | renesas,ether-link-active-low; |
| 47 | #address-cells = <1>; |
| 48 | #size-cells = <0>; |
| 49 | |
| 50 | phy1: ethernet-phy@1 { |
| 51 | reg = <1>; |
| 52 | interrupt-parent = <&irqc0>; |
| 53 | interrupts = <0 IRQ_TYPE_LEVEL_LOW>; |
| 54 | pinctrl-0 = <&phy1_pins>; |
| 55 | pinctrl-names = "default"; |
| 56 | }; |
| 57 | }; |