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gerrit-public.fairphone.software / kernel / msm-4.19 / 2cb98d010fdc7a545856baf32bce096fa431d250 / . / drivers / pci / pcie / Kconfig
blob: ac53edbc9613cc3a89ecdaf1c88241d0fe824279 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1#
2# PCI Express Port Bus Configuration
3#
4config PCIEPORTBUS
Ezequiel Garciad47af0b2013-07-04 17:45:20 -0300[diff] [blame]5 bool "PCI Express Port Bus support"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6 depends on PCI
7 help
8 This automatically enables PCI Express Port Bus support. Users can
9 choose Native Hot-Plug support, Advanced Error Reporting support,
10 Power Management Event support and Virtual Channel support to run
11 on PCI Express Ports (Root or Switch).
12
13#
14# Include service Kconfig here
15#
16config HOTPLUG_PCI_PCIE
Bjorn Helgaasc10cc482013-07-23 10:55:56 -0600[diff] [blame]17 bool "PCI Express Hotplug driver"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]18 depends on HOTPLUG_PCI && PCIEPORTBUS
19 help
20 Say Y here if you have a motherboard that supports PCI Express Native
21 Hotplug
22
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]23 When in doubt, say N.
24
Zhang, Yanmin6c2b3742006-07-31 15:21:33 +0800[diff] [blame]25source "drivers/pci/pcie/aer/Kconfig"
Shaohua Li7d715a62008-02-25 09:46:41 +0800[diff] [blame]26
27#
28# PCI Express ASPM
29#
30config PCIEASPM
David Rientjes6a108a12011-01-20 14:44:16 -0800[diff] [blame]31 bool "PCI Express ASPM control" if EXPERT
Matthew Garrettea5f9fc2010-06-22 17:03:03 -0400[diff] [blame]32 depends on PCI && PCIEPORTBUS
33 default y
Shaohua Li7d715a62008-02-25 09:46:41 +0800[diff] [blame]34 help
Matthew Garrettea5f9fc2010-06-22 17:03:03 -0400[diff] [blame]35 This enables OS control over PCI Express ASPM (Active State
36 Power Management) and Clock Power Management. ASPM supports
37 state L0/L0s/L1.
Shaohua Li7d715a62008-02-25 09:46:41 +0800[diff] [blame]38
P. Christeasd56641c2011-12-06 20:48:35 +0200[diff] [blame]39 ASPM is initially set up by the firmware. With this option enabled,
Matthew Garrettea5f9fc2010-06-22 17:03:03 -0400[diff] [blame]40 Linux can modify this state in order to disable ASPM on known-bad
41 hardware or configurations and enable it when known-safe.
42
43 ASPM can be disabled or enabled at runtime via
44 /sys/module/pcie_aspm/parameters/policy
45
46 When in doubt, say Y.
Andreas Zieglercc731762016-03-15 12:28:32 +0100[diff] [blame]47
Shaohua Li7d715a62008-02-25 09:46:41 +0800[diff] [blame]48config PCIEASPM_DEBUG
49 bool "Debug PCI Express ASPM"
50 depends on PCIEASPM
51 default n
52 help
53 This enables PCI Express ASPM debug support. It will add per-device
54 interface to control ASPM.
Rafael J. Wysockic7f48652010-02-17 23:39:08 +0100[diff] [blame]55
Matthew Garrettad71c962012-02-03 10:18:13 -0500[diff] [blame]56choice
57 prompt "Default ASPM policy"
58 default PCIEASPM_DEFAULT
59 depends on PCIEASPM
60
61config PCIEASPM_DEFAULT
Andreas Zieglercc731762016-03-15 12:28:32 +0100[diff] [blame]62 bool "BIOS default"
Matthew Garrettad71c962012-02-03 10:18:13 -0500[diff] [blame]63 depends on PCIEASPM
64 help
65 Use the BIOS defaults for PCI Express ASPM.
66
67config PCIEASPM_POWERSAVE
Andreas Zieglercc731762016-03-15 12:28:32 +0100[diff] [blame]68 bool "Powersave"
Matthew Garrettad71c962012-02-03 10:18:13 -0500[diff] [blame]69 depends on PCIEASPM
70 help
71 Enable PCI Express ASPM L0s and L1 where possible, even if the
72 BIOS did not.
73
Rajat Jainb2103cc2017-01-02 22:34:11 -0800[diff] [blame]74config PCIEASPM_POWER_SUPERSAVE
75 bool "Power Supersave"
76 depends on PCIEASPM
77 help
78 Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
79 possible. This would result in higher power savings while staying in L1
80 where the components support it.
81
Matthew Garrettad71c962012-02-03 10:18:13 -0500[diff] [blame]82config PCIEASPM_PERFORMANCE
Andreas Zieglercc731762016-03-15 12:28:32 +0100[diff] [blame]83 bool "Performance"
Matthew Garrettad71c962012-02-03 10:18:13 -0500[diff] [blame]84 depends on PCIEASPM
85 help
86 Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
87endchoice
88
Rafael J. Wysockic7f48652010-02-17 23:39:08 +0100[diff] [blame]89config PCIE_PME
90 def_bool y
Rafael J. Wysockifbb988b2014-11-27 23:16:57 +0100[diff] [blame]91 depends on PCIEPORTBUS && PM
Keith Busch26e51572016-04-28 16:24:48 -0600[diff] [blame]92
93config PCIE_DPC
Keith Buscha4959d82016-07-06 10:06:01 -0600[diff] [blame]94 bool "PCIe Downstream Port Containment support"
Keith Busch26e51572016-04-28 16:24:48 -0600[diff] [blame]95 depends on PCIEPORTBUS
96 default n
97 help
98 This enables PCI Express Downstream Port Containment (DPC)
99 driver support. DPC events from Root and Downstream ports
100 will be handled by the DPC driver. If your system doesn't
101 have this capability or you do not want to use this feature,
102 it is safe to answer N.
Jonathan Yong9bb04a02016-06-11 14:13:38 -0500[diff] [blame]103
104config PCIE_PTM
105 bool "PCIe Precision Time Measurement support"
106 default n
107 depends on PCIEPORTBUS
108 help
109 This enables PCI Express Precision Time Measurement (PTM)
110 support.
111
112 This is only useful if you have devices that support PTM, but it
113 is safe to enable even if you don't.