blob: 77b64bd64df36aab2dd805a5dd2e056003c3c6e7 [file] [log] [blame]
Flora Fu6df8dd52015-02-22 13:15:29 +01001/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Flora Fu, MediaTek
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/interrupt.h>
16#include <linux/module.h>
17#include <linux/of_device.h>
18#include <linux/of_irq.h>
19#include <linux/regmap.h>
20#include <linux/mfd/core.h>
21#include <linux/mfd/mt6397/core.h>
John Crispin44760cf2016-01-27 12:47:38 +010022#include <linux/mfd/mt6323/core.h>
Flora Fu6df8dd52015-02-22 13:15:29 +010023#include <linux/mfd/mt6397/registers.h>
John Crispin44760cf2016-01-27 12:47:38 +010024#include <linux/mfd/mt6323/registers.h>
Flora Fu6df8dd52015-02-22 13:15:29 +010025
Eddie Huanga5d7ea02015-05-06 15:23:40 +080026#define MT6397_RTC_BASE 0xe000
27#define MT6397_RTC_SIZE 0x3e
28
John Crispin44760cf2016-01-27 12:47:38 +010029#define MT6323_CID_CODE 0x23
John Crispin1d2c25e2016-01-27 12:47:37 +010030#define MT6391_CID_CODE 0x91
31#define MT6397_CID_CODE 0x97
32
Eddie Huanga5d7ea02015-05-06 15:23:40 +080033static const struct resource mt6397_rtc_resources[] = {
34 {
35 .start = MT6397_RTC_BASE,
36 .end = MT6397_RTC_BASE + MT6397_RTC_SIZE,
37 .flags = IORESOURCE_MEM,
38 },
39 {
40 .start = MT6397_IRQ_RTC,
41 .end = MT6397_IRQ_RTC,
42 .flags = IORESOURCE_IRQ,
43 },
44};
45
Chen Zhong55d1d152017-10-25 21:16:04 +080046static const struct resource mt6323_keys_resources[] = {
47 DEFINE_RES_IRQ(MT6323_IRQ_STATUS_PWRKEY),
48 DEFINE_RES_IRQ(MT6323_IRQ_STATUS_FCHRKEY),
49};
50
51static const struct resource mt6397_keys_resources[] = {
52 DEFINE_RES_IRQ(MT6397_IRQ_PWRKEY),
53 DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY),
54};
55
John Crispin44760cf2016-01-27 12:47:38 +010056static const struct mfd_cell mt6323_devs[] = {
57 {
58 .name = "mt6323-regulator",
59 .of_compatible = "mediatek,mt6323-regulator"
Sean Wang040fc9b2017-03-20 14:47:27 +080060 }, {
Sean Wang1cb8af82017-01-23 11:54:45 +080061 .name = "mt6323-led",
62 .of_compatible = "mediatek,mt6323-led"
Chen Zhong55d1d152017-10-25 21:16:04 +080063 }, {
64 .name = "mtk-pmic-keys",
65 .num_resources = ARRAY_SIZE(mt6323_keys_resources),
66 .resources = mt6323_keys_resources,
67 .of_compatible = "mediatek,mt6323-keys"
Sean Wang1cb8af82017-01-23 11:54:45 +080068 },
John Crispin44760cf2016-01-27 12:47:38 +010069};
70
Flora Fu6df8dd52015-02-22 13:15:29 +010071static const struct mfd_cell mt6397_devs[] = {
72 {
73 .name = "mt6397-rtc",
Eddie Huanga5d7ea02015-05-06 15:23:40 +080074 .num_resources = ARRAY_SIZE(mt6397_rtc_resources),
75 .resources = mt6397_rtc_resources,
Flora Fu6df8dd52015-02-22 13:15:29 +010076 .of_compatible = "mediatek,mt6397-rtc",
77 }, {
78 .name = "mt6397-regulator",
79 .of_compatible = "mediatek,mt6397-regulator",
80 }, {
81 .name = "mt6397-codec",
82 .of_compatible = "mediatek,mt6397-codec",
83 }, {
84 .name = "mt6397-clk",
85 .of_compatible = "mediatek,mt6397-clk",
Hongzhou Yangcf550782015-05-27 02:10:35 -070086 }, {
87 .name = "mt6397-pinctrl",
88 .of_compatible = "mediatek,mt6397-pinctrl",
Chen Zhong55d1d152017-10-25 21:16:04 +080089 }, {
90 .name = "mtk-pmic-keys",
91 .num_resources = ARRAY_SIZE(mt6397_keys_resources),
92 .resources = mt6397_keys_resources,
93 .of_compatible = "mediatek,mt6397-keys"
94 }
Flora Fu6df8dd52015-02-22 13:15:29 +010095};
96
97static void mt6397_irq_lock(struct irq_data *data)
98{
Jiang Liu1e84aa42015-07-13 20:44:56 +000099 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
Flora Fu6df8dd52015-02-22 13:15:29 +0100100
101 mutex_lock(&mt6397->irqlock);
102}
103
104static void mt6397_irq_sync_unlock(struct irq_data *data)
105{
Jiang Liu1e84aa42015-07-13 20:44:56 +0000106 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
Flora Fu6df8dd52015-02-22 13:15:29 +0100107
John Crispinfeec4792016-01-27 12:47:36 +0100108 regmap_write(mt6397->regmap, mt6397->int_con[0],
109 mt6397->irq_masks_cur[0]);
110 regmap_write(mt6397->regmap, mt6397->int_con[1],
111 mt6397->irq_masks_cur[1]);
Flora Fu6df8dd52015-02-22 13:15:29 +0100112
113 mutex_unlock(&mt6397->irqlock);
114}
115
116static void mt6397_irq_disable(struct irq_data *data)
117{
Jiang Liu1e84aa42015-07-13 20:44:56 +0000118 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
Flora Fu6df8dd52015-02-22 13:15:29 +0100119 int shift = data->hwirq & 0xf;
120 int reg = data->hwirq >> 4;
121
122 mt6397->irq_masks_cur[reg] &= ~BIT(shift);
123}
124
125static void mt6397_irq_enable(struct irq_data *data)
126{
Jiang Liu1e84aa42015-07-13 20:44:56 +0000127 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
Flora Fu6df8dd52015-02-22 13:15:29 +0100128 int shift = data->hwirq & 0xf;
129 int reg = data->hwirq >> 4;
130
131 mt6397->irq_masks_cur[reg] |= BIT(shift);
132}
133
Henry Chenf3151ab2015-08-10 21:10:45 +0800134#ifdef CONFIG_PM_SLEEP
135static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
136{
137 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
138 int shift = irq_data->hwirq & 0xf;
139 int reg = irq_data->hwirq >> 4;
140
141 if (on)
142 mt6397->wake_mask[reg] |= BIT(shift);
143 else
144 mt6397->wake_mask[reg] &= ~BIT(shift);
145
146 return 0;
147}
148#else
149#define mt6397_irq_set_wake NULL
150#endif
151
Flora Fu6df8dd52015-02-22 13:15:29 +0100152static struct irq_chip mt6397_irq_chip = {
153 .name = "mt6397-irq",
154 .irq_bus_lock = mt6397_irq_lock,
155 .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
156 .irq_enable = mt6397_irq_enable,
157 .irq_disable = mt6397_irq_disable,
Henry Chenf3151ab2015-08-10 21:10:45 +0800158 .irq_set_wake = mt6397_irq_set_wake,
Flora Fu6df8dd52015-02-22 13:15:29 +0100159};
160
161static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
162 int irqbase)
163{
164 unsigned int status;
165 int i, irq, ret;
166
167 ret = regmap_read(mt6397->regmap, reg, &status);
168 if (ret) {
169 dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
170 return;
171 }
172
173 for (i = 0; i < 16; i++) {
174 if (status & BIT(i)) {
175 irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
176 if (irq)
177 handle_nested_irq(irq);
178 }
179 }
180
181 regmap_write(mt6397->regmap, reg, status);
182}
183
184static irqreturn_t mt6397_irq_thread(int irq, void *data)
185{
186 struct mt6397_chip *mt6397 = data;
187
John Crispinfeec4792016-01-27 12:47:36 +0100188 mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
189 mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
Flora Fu6df8dd52015-02-22 13:15:29 +0100190
191 return IRQ_HANDLED;
192}
193
194static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
195 irq_hw_number_t hw)
196{
197 struct mt6397_chip *mt6397 = d->host_data;
198
199 irq_set_chip_data(irq, mt6397);
200 irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
201 irq_set_nested_thread(irq, 1);
Flora Fu6df8dd52015-02-22 13:15:29 +0100202 irq_set_noprobe(irq);
Flora Fu6df8dd52015-02-22 13:15:29 +0100203
204 return 0;
205}
206
Krzysztof Kozlowski7ce7b262015-04-27 21:54:13 +0900207static const struct irq_domain_ops mt6397_irq_domain_ops = {
Flora Fu6df8dd52015-02-22 13:15:29 +0100208 .map = mt6397_irq_domain_map,
209};
210
211static int mt6397_irq_init(struct mt6397_chip *mt6397)
212{
213 int ret;
214
215 mutex_init(&mt6397->irqlock);
216
217 /* Mask all interrupt sources */
John Crispinfeec4792016-01-27 12:47:36 +0100218 regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
219 regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);
Flora Fu6df8dd52015-02-22 13:15:29 +0100220
221 mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
222 MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
223 if (!mt6397->irq_domain) {
224 dev_err(mt6397->dev, "could not create irq domain\n");
225 return -ENOMEM;
226 }
227
228 ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
229 mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
230 if (ret) {
231 dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
232 mt6397->irq, ret);
233 return ret;
234 }
235
236 return 0;
237}
238
Henry Chenf3151ab2015-08-10 21:10:45 +0800239#ifdef CONFIG_PM_SLEEP
240static int mt6397_irq_suspend(struct device *dev)
241{
242 struct mt6397_chip *chip = dev_get_drvdata(dev);
243
John Crispinfeec4792016-01-27 12:47:36 +0100244 regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
245 regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);
Henry Chenf3151ab2015-08-10 21:10:45 +0800246
247 enable_irq_wake(chip->irq);
248
249 return 0;
250}
251
252static int mt6397_irq_resume(struct device *dev)
253{
254 struct mt6397_chip *chip = dev_get_drvdata(dev);
255
John Crispinfeec4792016-01-27 12:47:36 +0100256 regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
257 regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);
Henry Chenf3151ab2015-08-10 21:10:45 +0800258
259 disable_irq_wake(chip->irq);
260
261 return 0;
262}
263#endif
264
265static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
266 mt6397_irq_resume);
267
Flora Fu6df8dd52015-02-22 13:15:29 +0100268static int mt6397_probe(struct platform_device *pdev)
269{
270 int ret;
John Crispin1d2c25e2016-01-27 12:47:37 +0100271 unsigned int id;
272 struct mt6397_chip *pmic;
Flora Fu6df8dd52015-02-22 13:15:29 +0100273
John Crispin1d2c25e2016-01-27 12:47:37 +0100274 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
275 if (!pmic)
Flora Fu6df8dd52015-02-22 13:15:29 +0100276 return -ENOMEM;
277
John Crispin1d2c25e2016-01-27 12:47:37 +0100278 pmic->dev = &pdev->dev;
John Crispinfeec4792016-01-27 12:47:36 +0100279
Flora Fu6df8dd52015-02-22 13:15:29 +0100280 /*
281 * mt6397 MFD is child device of soc pmic wrapper.
282 * Regmap is set from its parent.
283 */
John Crispin1d2c25e2016-01-27 12:47:37 +0100284 pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
285 if (!pmic->regmap)
Flora Fu6df8dd52015-02-22 13:15:29 +0100286 return -ENODEV;
287
John Crispin1d2c25e2016-01-27 12:47:37 +0100288 platform_set_drvdata(pdev, pmic);
Flora Fu6df8dd52015-02-22 13:15:29 +0100289
John Crispin1d2c25e2016-01-27 12:47:37 +0100290 ret = regmap_read(pmic->regmap, MT6397_CID, &id);
291 if (ret) {
292 dev_err(pmic->dev, "Failed to read chip id: %d\n", ret);
Henry Chen1387ff52016-04-15 16:30:29 +0800293 return ret;
John Crispin1d2c25e2016-01-27 12:47:37 +0100294 }
295
Henry Chen1387ff52016-04-15 16:30:29 +0800296 pmic->irq = platform_get_irq(pdev, 0);
297 if (pmic->irq <= 0)
298 return pmic->irq;
299
John Crispin1d2c25e2016-01-27 12:47:37 +0100300 switch (id & 0xff) {
John Crispin44760cf2016-01-27 12:47:38 +0100301 case MT6323_CID_CODE:
302 pmic->int_con[0] = MT6323_INT_CON0;
303 pmic->int_con[1] = MT6323_INT_CON1;
304 pmic->int_status[0] = MT6323_INT_STATUS0;
305 pmic->int_status[1] = MT6323_INT_STATUS1;
Henry Chen1387ff52016-04-15 16:30:29 +0800306 ret = mt6397_irq_init(pmic);
307 if (ret)
308 return ret;
309
Laxman Dewangan08e380a2016-04-08 00:13:04 +0530310 ret = devm_mfd_add_devices(&pdev->dev, -1, mt6323_devs,
311 ARRAY_SIZE(mt6323_devs), NULL,
Chen Zhonge695d3a2017-10-25 21:15:59 +0800312 0, pmic->irq_domain);
John Crispin44760cf2016-01-27 12:47:38 +0100313 break;
314
John Crispin1d2c25e2016-01-27 12:47:37 +0100315 case MT6397_CID_CODE:
316 case MT6391_CID_CODE:
317 pmic->int_con[0] = MT6397_INT_CON0;
318 pmic->int_con[1] = MT6397_INT_CON1;
319 pmic->int_status[0] = MT6397_INT_STATUS0;
320 pmic->int_status[1] = MT6397_INT_STATUS1;
Henry Chen1387ff52016-04-15 16:30:29 +0800321 ret = mt6397_irq_init(pmic);
322 if (ret)
323 return ret;
324
Laxman Dewangan08e380a2016-04-08 00:13:04 +0530325 ret = devm_mfd_add_devices(&pdev->dev, -1, mt6397_devs,
326 ARRAY_SIZE(mt6397_devs), NULL,
Chen Zhonge695d3a2017-10-25 21:15:59 +0800327 0, pmic->irq_domain);
John Crispin1d2c25e2016-01-27 12:47:37 +0100328 break;
329
330 default:
331 dev_err(&pdev->dev, "unsupported chip: %d\n", id);
332 ret = -ENODEV;
333 break;
334 }
335
John Crispin1d2c25e2016-01-27 12:47:37 +0100336 if (ret) {
337 irq_domain_remove(pmic->irq_domain);
Flora Fu6df8dd52015-02-22 13:15:29 +0100338 dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
John Crispin1d2c25e2016-01-27 12:47:37 +0100339 }
Flora Fu6df8dd52015-02-22 13:15:29 +0100340
341 return ret;
342}
343
Flora Fu6df8dd52015-02-22 13:15:29 +0100344static const struct of_device_id mt6397_of_match[] = {
345 { .compatible = "mediatek,mt6397" },
John Crispin44760cf2016-01-27 12:47:38 +0100346 { .compatible = "mediatek,mt6323" },
Flora Fu6df8dd52015-02-22 13:15:29 +0100347 { }
348};
349MODULE_DEVICE_TABLE(of, mt6397_of_match);
350
Javier Martinez Canillase1d9a102016-02-10 13:50:18 -0300351static const struct platform_device_id mt6397_id[] = {
352 { "mt6397", 0 },
353 { },
354};
355MODULE_DEVICE_TABLE(platform, mt6397_id);
356
Flora Fu6df8dd52015-02-22 13:15:29 +0100357static struct platform_driver mt6397_driver = {
358 .probe = mt6397_probe,
Flora Fu6df8dd52015-02-22 13:15:29 +0100359 .driver = {
360 .name = "mt6397",
361 .of_match_table = of_match_ptr(mt6397_of_match),
Henry Chenf3151ab2015-08-10 21:10:45 +0800362 .pm = &mt6397_pm_ops,
Flora Fu6df8dd52015-02-22 13:15:29 +0100363 },
Javier Martinez Canillase1d9a102016-02-10 13:50:18 -0300364 .id_table = mt6397_id,
Flora Fu6df8dd52015-02-22 13:15:29 +0100365};
366
367module_platform_driver(mt6397_driver);
368
369MODULE_AUTHOR("Flora Fu, MediaTek");
370MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
371MODULE_LICENSE("GPL");