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gerrit-public.fairphone.software / kernel / msm-4.19 / 2d32ffa44a5323fda147bd5b0723744a9163e37f / . / include / asm-mips / mach-au1x00 / au1000.h
blob: ffcd0492eb3a00752bdc491a6b197feabe29aa85 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 *
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31 /*
32 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
33 */
34
35#ifndef _AU1000_H_
36#define _AU1000_H_
37
38#include <linux/config.h>
39
40#ifndef _LANGUAGE_ASSEMBLY
41
42#include <linux/delay.h>
43#include <asm/io.h>
44
45/* cpu pipeline flush */
46void static inline au_sync(void)
47{
48 __asm__ volatile ("sync");
49}
50
51void static inline au_sync_udelay(int us)
52{
53 __asm__ volatile ("sync");
54 udelay(us);
55}
56
57void static inline au_sync_delay(int ms)
58{
59 __asm__ volatile ("sync");
60 mdelay(ms);
61}
62
63void static inline au_writeb(u8 val, int reg)
64{
65 *(volatile u8 *)(reg) = val;
66}
67
68void static inline au_writew(u16 val, int reg)
69{
70 *(volatile u16 *)(reg) = val;
71}
72
73void static inline au_writel(u32 val, int reg)
74{
75 *(volatile u32 *)(reg) = val;
76}
77
78static inline u8 au_readb(unsigned long port)
79{
80 return (*(volatile u8 *)port);
81}
82
83static inline u16 au_readw(unsigned long port)
84{
85 return (*(volatile u16 *)port);
86}
87
88static inline u32 au_readl(unsigned long port)
89{
90 return (*(volatile u32 *)port);
91}
92
93/* These next three functions should be a generic part of the MIPS
94 * kernel (with the 'au_' removed from the name) and selected for
95 * processors that support the instructions.
96 * Taken from PPC tree. -- Dan
97 */
98/* Return the bit position of the most significant 1 bit in a word */
99static __inline__ int __ilog2(unsigned int x)
100{
101 int lz;
102
103 asm volatile (
104 ".set\tnoreorder\n\t"
105 ".set\tnoat\n\t"
106 ".set\tmips32\n\t"
107 "clz\t%0,%1\n\t"
108 ".set\tmips0\n\t"
109 ".set\tat\n\t"
110 ".set\treorder"
111 : "=r" (lz)
112 : "r" (x));
113
114 return 31 - lz;
115}
116
117static __inline__ int au_ffz(unsigned int x)
118{
119 if ((x = ~x) == 0)
120 return 32;
121 return __ilog2(x & -x);
122}
123
124/*
125 * ffs: find first bit set. This is defined the same way as
126 * the libc and compiler builtin ffs routines, therefore
127 * differs in spirit from the above ffz (man ffs).
128 */
129static __inline__ int au_ffs(int x)
130{
131 return __ilog2(x & -x) + 1;
132}
133
134/* arch/mips/au1000/common/clocks.c */
135extern void set_au1x00_speed(unsigned int new_freq);
136extern unsigned int get_au1x00_speed(void);
137extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
138extern unsigned long get_au1x00_uart_baud_base(void);
139extern void set_au1x00_lcd_clock(void);
140extern unsigned int get_au1x00_lcd_clock(void);
141
142/*
143 * Every board describes its IRQ mapping with this table.
144 */
145typedef struct au1xxx_irqmap {
146 int im_irq;
147 int im_type;
148 int im_request;
149} au1xxx_irq_map_t;
150
151/*
152 * init_IRQ looks for a table with this name.
153 */
154extern au1xxx_irq_map_t au1xxx_irq_map[];
155
156#endif /* !defined (_LANGUAGE_ASSEMBLY) */
157
158#ifdef CONFIG_PM
159/* no CP0 timer irq */
160#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
161#else
162#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
163#endif
164
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]165/*
166 * SDRAM Register Offsets
167 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]168#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]169#define MEM_SDMODE0 (0x0000)
170#define MEM_SDMODE1 (0x0004)
171#define MEM_SDMODE2 (0x0008)
172#define MEM_SDADDR0 (0x000C)
173#define MEM_SDADDR1 (0x0010)
174#define MEM_SDADDR2 (0x0014)
175#define MEM_SDREFCFG (0x0018)
176#define MEM_SDPRECMD (0x001C)
177#define MEM_SDAUTOREF (0x0020)
178#define MEM_SDWRMD0 (0x0024)
179#define MEM_SDWRMD1 (0x0028)
180#define MEM_SDWRMD2 (0x002C)
181#define MEM_SDSLEEP (0x0030)
182#define MEM_SDSMCKE (0x0034)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]183
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]184#ifndef ASSEMBLER
185/*typedef volatile struct
186{
187 uint32 sdmode0;
188 uint32 sdmode1;
189 uint32 sdmode2;
190 uint32 sdaddr0;
191 uint32 sdaddr1;
192 uint32 sdaddr2;
193 uint32 sdrefcfg;
194 uint32 sdautoref;
195 uint32 sdwrmd0;
196 uint32 sdwrmd1;
197 uint32 sdwrmd2;
198 uint32 sdsleep;
199 uint32 sdsmcke;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]200
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]201} AU1X00_SDRAM;*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]202#endif
203
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]204/*
205 * MEM_SDMODE register content definitions
206 */
207#define MEM_SDMODE_F (1<<22)
208#define MEM_SDMODE_SR (1<<21)
209#define MEM_SDMODE_BS (1<<20)
210#define MEM_SDMODE_RS (3<<18)
211#define MEM_SDMODE_CS (7<<15)
212#define MEM_SDMODE_TRAS (15<<11)
213#define MEM_SDMODE_TMRD (3<<9)
214#define MEM_SDMODE_TWR (3<<7)
215#define MEM_SDMODE_TRP (3<<5)
216#define MEM_SDMODE_TRCD (3<<3)
217#define MEM_SDMODE_TCL (7<<0)
218
219#define MEM_SDMODE_BS_2Bank (0<<20)
220#define MEM_SDMODE_BS_4Bank (1<<20)
221#define MEM_SDMODE_RS_11Row (0<<18)
222#define MEM_SDMODE_RS_12Row (1<<18)
223#define MEM_SDMODE_RS_13Row (2<<18)
224#define MEM_SDMODE_RS_N(N) ((N)<<18)
225#define MEM_SDMODE_CS_7Col (0<<15)
226#define MEM_SDMODE_CS_8Col (1<<15)
227#define MEM_SDMODE_CS_9Col (2<<15)
228#define MEM_SDMODE_CS_10Col (3<<15)
229#define MEM_SDMODE_CS_11Col (4<<15)
230#define MEM_SDMODE_CS_N(N) ((N)<<15)
231#define MEM_SDMODE_TRAS_N(N) ((N)<<11)
232#define MEM_SDMODE_TMRD_N(N) ((N)<<9)
233#define MEM_SDMODE_TWR_N(N) ((N)<<7)
234#define MEM_SDMODE_TRP_N(N) ((N)<<5)
235#define MEM_SDMODE_TRCD_N(N) ((N)<<3)
236#define MEM_SDMODE_TCL_N(N) ((N)<<0)
237
238/*
239 * MEM_SDADDR register contents definitions
240 */
241#define MEM_SDADDR_E (1<<20)
242#define MEM_SDADDR_CSBA (0x03FF<<10)
243#define MEM_SDADDR_CSMASK (0x03FF<<0)
244#define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12)
245#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22)
246
247/*
248 * MEM_SDREFCFG register content definitions
249 */
250#define MEM_SDREFCFG_TRC (15<<28)
251#define MEM_SDREFCFG_TRPM (3<<26)
252#define MEM_SDREFCFG_E (1<<25)
253#define MEM_SDREFCFG_RE (0x1ffffff<<0)
254#define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC)
255#define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM)
256#define MEM_SDREFCFG_REF_N(N) (N)
257#endif
258
259/***********************************************************************/
260
261/*
262 * Au1550 SDRAM Register Offsets
263 */
264
265/***********************************************************************/
266
267#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
268#define MEM_SDMODE0 (0x0800)
269#define MEM_SDMODE1 (0x0808)
270#define MEM_SDMODE2 (0x0810)
271#define MEM_SDADDR0 (0x0820)
272#define MEM_SDADDR1 (0x0828)
273#define MEM_SDADDR2 (0x0830)
274#define MEM_SDCONFIGA (0x0840)
275#define MEM_SDCONFIGB (0x0848)
276#define MEM_SDSTAT (0x0850)
277#define MEM_SDERRADDR (0x0858)
278#define MEM_SDSTRIDE0 (0x0860)
279#define MEM_SDSTRIDE1 (0x0868)
280#define MEM_SDSTRIDE2 (0x0870)
281#define MEM_SDWRMD0 (0x0880)
282#define MEM_SDWRMD1 (0x0888)
283#define MEM_SDWRMD2 (0x0890)
284#define MEM_SDPRECMD (0x08C0)
285#define MEM_SDAUTOREF (0x08C8)
286#define MEM_SDSREF (0x08D0)
287#define MEM_SDSLEEP MEM_SDSREF
288
289#ifndef ASSEMBLER
290/*typedef volatile struct
291{
292 uint32 sdmode0;
293 uint32 reserved0;
294 uint32 sdmode1;
295 uint32 reserved1;
296 uint32 sdmode2;
297 uint32 reserved2[3];
298 uint32 sdaddr0;
299 uint32 reserved3;
300 uint32 sdaddr1;
301 uint32 reserved4;
302 uint32 sdaddr2;
303 uint32 reserved5[3];
304 uint32 sdconfiga;
305 uint32 reserved6;
306 uint32 sdconfigb;
307 uint32 reserved7;
308 uint32 sdstat;
309 uint32 reserved8;
310 uint32 sderraddr;
311 uint32 reserved9;
312 uint32 sdstride0;
313 uint32 reserved10;
314 uint32 sdstride1;
315 uint32 reserved11;
316 uint32 sdstride2;
317 uint32 reserved12[3];
318 uint32 sdwrmd0;
319 uint32 reserved13;
320 uint32 sdwrmd1;
321 uint32 reserved14;
322 uint32 sdwrmd2;
323 uint32 reserved15[11];
324 uint32 sdprecmd;
325 uint32 reserved16;
326 uint32 sdautoref;
327 uint32 reserved17;
328 uint32 sdsref;
329
330} AU1550_SDRAM;*/
331#endif
332#endif
333
334/*
335 * Physical base addresses for integrated peripherals
336 */
337
338#ifdef CONFIG_SOC_AU1000
339#define MEM_PHYS_ADDR 0x14000000
340#define STATIC_MEM_PHYS_ADDR 0x14001000
341#define DMA0_PHYS_ADDR 0x14002000
342#define DMA1_PHYS_ADDR 0x14002100
343#define DMA2_PHYS_ADDR 0x14002200
344#define DMA3_PHYS_ADDR 0x14002300
345#define DMA4_PHYS_ADDR 0x14002400
346#define DMA5_PHYS_ADDR 0x14002500
347#define DMA6_PHYS_ADDR 0x14002600
348#define DMA7_PHYS_ADDR 0x14002700
349#define IC0_PHYS_ADDR 0x10400000
350#define IC1_PHYS_ADDR 0x11800000
351#define AC97_PHYS_ADDR 0x10000000
352#define USBH_PHYS_ADDR 0x10100000
353#define USBD_PHYS_ADDR 0x10200000
354#define IRDA_PHYS_ADDR 0x10300000
355#define MAC0_PHYS_ADDR 0x10500000
356#define MAC1_PHYS_ADDR 0x10510000
357#define MACEN_PHYS_ADDR 0x10520000
358#define MACDMA0_PHYS_ADDR 0x14004000
359#define MACDMA1_PHYS_ADDR 0x14004200
360#define I2S_PHYS_ADDR 0x11000000
361#define UART0_PHYS_ADDR 0x11100000
362#define UART1_PHYS_ADDR 0x11200000
363#define UART2_PHYS_ADDR 0x11300000
364#define UART3_PHYS_ADDR 0x11400000
365#define SSI0_PHYS_ADDR 0x11600000
366#define SSI1_PHYS_ADDR 0x11680000
367#define SYS_PHYS_ADDR 0x11900000
368#define PCMCIA_IO_PHYS_ADDR 0xF00000000
369#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
370#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
371#endif
372
373/********************************************************************/
374
375#ifdef CONFIG_SOC_AU1500
376#define MEM_PHYS_ADDR 0x14000000
377#define STATIC_MEM_PHYS_ADDR 0x14001000
378#define DMA0_PHYS_ADDR 0x14002000
379#define DMA1_PHYS_ADDR 0x14002100
380#define DMA2_PHYS_ADDR 0x14002200
381#define DMA3_PHYS_ADDR 0x14002300
382#define DMA4_PHYS_ADDR 0x14002400
383#define DMA5_PHYS_ADDR 0x14002500
384#define DMA6_PHYS_ADDR 0x14002600
385#define DMA7_PHYS_ADDR 0x14002700
386#define IC0_PHYS_ADDR 0x10400000
387#define IC1_PHYS_ADDR 0x11800000
388#define AC97_PHYS_ADDR 0x10000000
389#define USBH_PHYS_ADDR 0x10100000
390#define USBD_PHYS_ADDR 0x10200000
391#define PCI_PHYS_ADDR 0x14005000
392#define MAC0_PHYS_ADDR 0x11500000
393#define MAC1_PHYS_ADDR 0x11510000
394#define MACEN_PHYS_ADDR 0x11520000
395#define MACDMA0_PHYS_ADDR 0x14004000
396#define MACDMA1_PHYS_ADDR 0x14004200
397#define I2S_PHYS_ADDR 0x11000000
398#define UART0_PHYS_ADDR 0x11100000
399#define UART3_PHYS_ADDR 0x11400000
400#define GPIO2_PHYS_ADDR 0x11700000
401#define SYS_PHYS_ADDR 0x11900000
402#define PCI_MEM_PHYS_ADDR 0x400000000
403#define PCI_IO_PHYS_ADDR 0x500000000
404#define PCI_CONFIG0_PHYS_ADDR 0x600000000
405#define PCI_CONFIG1_PHYS_ADDR 0x680000000
406#define PCMCIA_IO_PHYS_ADDR 0xF00000000
407#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
408#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
409#endif
410
411/********************************************************************/
412
413#ifdef CONFIG_SOC_AU1100
414#define MEM_PHYS_ADDR 0x14000000
415#define STATIC_MEM_PHYS_ADDR 0x14001000
416#define DMA0_PHYS_ADDR 0x14002000
417#define DMA1_PHYS_ADDR 0x14002100
418#define DMA2_PHYS_ADDR 0x14002200
419#define DMA3_PHYS_ADDR 0x14002300
420#define DMA4_PHYS_ADDR 0x14002400
421#define DMA5_PHYS_ADDR 0x14002500
422#define DMA6_PHYS_ADDR 0x14002600
423#define DMA7_PHYS_ADDR 0x14002700
424#define IC0_PHYS_ADDR 0x10400000
425#define SD0_PHYS_ADDR 0x10600000
426#define SD1_PHYS_ADDR 0x10680000
427#define IC1_PHYS_ADDR 0x11800000
428#define AC97_PHYS_ADDR 0x10000000
429#define USBH_PHYS_ADDR 0x10100000
430#define USBD_PHYS_ADDR 0x10200000
431#define IRDA_PHYS_ADDR 0x10300000
432#define MAC0_PHYS_ADDR 0x10500000
433#define MACEN_PHYS_ADDR 0x10520000
434#define MACDMA0_PHYS_ADDR 0x14004000
435#define MACDMA1_PHYS_ADDR 0x14004200
436#define I2S_PHYS_ADDR 0x11000000
437#define UART0_PHYS_ADDR 0x11100000
438#define UART1_PHYS_ADDR 0x11200000
439#define UART3_PHYS_ADDR 0x11400000
440#define SSI0_PHYS_ADDR 0x11600000
441#define SSI1_PHYS_ADDR 0x11680000
442#define GPIO2_PHYS_ADDR 0x11700000
443#define SYS_PHYS_ADDR 0x11900000
444#define LCD_PHYS_ADDR 0x15000000
445#define PCMCIA_IO_PHYS_ADDR 0xF00000000
446#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
447#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
448#endif
449
450/***********************************************************************/
451
452#ifdef CONFIG_SOC_AU1550
453#define MEM_PHYS_ADDR 0x14000000
454#define STATIC_MEM_PHYS_ADDR 0x14001000
455#define IC0_PHYS_ADDR 0x10400000
456#define IC1_PHYS_ADDR 0x11800000
457#define USBH_PHYS_ADDR 0x14020000
458#define USBD_PHYS_ADDR 0x10200000
459#define PCI_PHYS_ADDR 0x14005000
460#define MAC0_PHYS_ADDR 0x10500000
461#define MAC1_PHYS_ADDR 0x10510000
462#define MACEN_PHYS_ADDR 0x10520000
463#define MACDMA0_PHYS_ADDR 0x14004000
464#define MACDMA1_PHYS_ADDR 0x14004200
465#define UART0_PHYS_ADDR 0x11100000
466#define UART1_PHYS_ADDR 0x11200000
467#define UART3_PHYS_ADDR 0x11400000
468#define GPIO2_PHYS_ADDR 0x11700000
469#define SYS_PHYS_ADDR 0x11900000
470#define DDMA_PHYS_ADDR 0x14002000
471#define PE_PHYS_ADDR 0x14008000
472#define PSC0_PHYS_ADDR 0x11A00000
473#define PSC1_PHYS_ADDR 0x11B00000
474#define PSC2_PHYS_ADDR 0x10A00000
475#define PSC3_PHYS_ADDR 0x10B00000
476#define PCI_MEM_PHYS_ADDR 0x400000000
477#define PCI_IO_PHYS_ADDR 0x500000000
478#define PCI_CONFIG0_PHYS_ADDR 0x600000000
479#define PCI_CONFIG1_PHYS_ADDR 0x680000000
480#define PCMCIA_IO_PHYS_ADDR 0xF00000000
481#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
482#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
483#endif
484
485/***********************************************************************/
486
487#ifdef CONFIG_SOC_AU1200
488#define MEM_PHYS_ADDR 0x14000000
489#define STATIC_MEM_PHYS_ADDR 0x14001000
490#define AES_PHYS_ADDR 0x10300000
491#define CIM_PHYS_ADDR 0x14004000
492#define IC0_PHYS_ADDR 0x10400000
493#define IC1_PHYS_ADDR 0x11800000
494#define USBM_PHYS_ADDR 0x14020000
495#define USBH_PHYS_ADDR 0x14020100
496#define UART0_PHYS_ADDR 0x11100000
497#define UART1_PHYS_ADDR 0x11200000
498#define GPIO2_PHYS_ADDR 0x11700000
499#define SYS_PHYS_ADDR 0x11900000
500#define DDMA_PHYS_ADDR 0x14002000
501#define PSC0_PHYS_ADDR 0x11A00000
502#define PSC1_PHYS_ADDR 0x11B00000
503#define PCMCIA_IO_PHYS_ADDR 0xF00000000
504#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
505#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
506#define SD0_PHYS_ADDR 0x10600000
507#define SD1_PHYS_ADDR 0x10680000
508#define LCD_PHYS_ADDR 0x15000000
509#define SWCNT_PHYS_ADDR 0x1110010C
510#define MAEFE_PHYS_ADDR 0x14012000
511#define MAEBE_PHYS_ADDR 0x14010000
512#endif
513
514
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]515/* Static Bus Controller */
516#define MEM_STCFG0 0xB4001000
517#define MEM_STTIME0 0xB4001004
518#define MEM_STADDR0 0xB4001008
519
520#define MEM_STCFG1 0xB4001010
521#define MEM_STTIME1 0xB4001014
522#define MEM_STADDR1 0xB4001018
523
524#define MEM_STCFG2 0xB4001020
525#define MEM_STTIME2 0xB4001024
526#define MEM_STADDR2 0xB4001028
527
528#define MEM_STCFG3 0xB4001030
529#define MEM_STTIME3 0xB4001034
530#define MEM_STADDR3 0xB4001038
531
532#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
533#define MEM_STNDCTL 0xB4001100
534#define MEM_STSTAT 0xB4001104
535
536#define MEM_STNAND_CMD (0x0)
537#define MEM_STNAND_ADDR (0x4)
538#define MEM_STNAND_DATA (0x20)
539#endif
540
541/* Interrupt Controller 0 */
542#define IC0_CFG0RD 0xB0400040
543#define IC0_CFG0SET 0xB0400040
544#define IC0_CFG0CLR 0xB0400044
545
546#define IC0_CFG1RD 0xB0400048
547#define IC0_CFG1SET 0xB0400048
548#define IC0_CFG1CLR 0xB040004C
549
550#define IC0_CFG2RD 0xB0400050
551#define IC0_CFG2SET 0xB0400050
552#define IC0_CFG2CLR 0xB0400054
553
554#define IC0_REQ0INT 0xB0400054
555#define IC0_SRCRD 0xB0400058
556#define IC0_SRCSET 0xB0400058
557#define IC0_SRCCLR 0xB040005C
558#define IC0_REQ1INT 0xB040005C
559
560#define IC0_ASSIGNRD 0xB0400060
561#define IC0_ASSIGNSET 0xB0400060
562#define IC0_ASSIGNCLR 0xB0400064
563
564#define IC0_WAKERD 0xB0400068
565#define IC0_WAKESET 0xB0400068
566#define IC0_WAKECLR 0xB040006C
567
568#define IC0_MASKRD 0xB0400070
569#define IC0_MASKSET 0xB0400070
570#define IC0_MASKCLR 0xB0400074
571
572#define IC0_RISINGRD 0xB0400078
573#define IC0_RISINGCLR 0xB0400078
574#define IC0_FALLINGRD 0xB040007C
575#define IC0_FALLINGCLR 0xB040007C
576
577#define IC0_TESTBIT 0xB0400080
578
579/* Interrupt Controller 1 */
580#define IC1_CFG0RD 0xB1800040
581#define IC1_CFG0SET 0xB1800040
582#define IC1_CFG0CLR 0xB1800044
583
584#define IC1_CFG1RD 0xB1800048
585#define IC1_CFG1SET 0xB1800048
586#define IC1_CFG1CLR 0xB180004C
587
588#define IC1_CFG2RD 0xB1800050
589#define IC1_CFG2SET 0xB1800050
590#define IC1_CFG2CLR 0xB1800054
591
592#define IC1_REQ0INT 0xB1800054
593#define IC1_SRCRD 0xB1800058
594#define IC1_SRCSET 0xB1800058
595#define IC1_SRCCLR 0xB180005C
596#define IC1_REQ1INT 0xB180005C
597
598#define IC1_ASSIGNRD 0xB1800060
599#define IC1_ASSIGNSET 0xB1800060
600#define IC1_ASSIGNCLR 0xB1800064
601
602#define IC1_WAKERD 0xB1800068
603#define IC1_WAKESET 0xB1800068
604#define IC1_WAKECLR 0xB180006C
605
606#define IC1_MASKRD 0xB1800070
607#define IC1_MASKSET 0xB1800070
608#define IC1_MASKCLR 0xB1800074
609
610#define IC1_RISINGRD 0xB1800078
611#define IC1_RISINGCLR 0xB1800078
612#define IC1_FALLINGRD 0xB180007C
613#define IC1_FALLINGCLR 0xB180007C
614
615#define IC1_TESTBIT 0xB1800080
616
617/* Interrupt Configuration Modes */
618#define INTC_INT_DISABLED 0
619#define INTC_INT_RISE_EDGE 0x1
620#define INTC_INT_FALL_EDGE 0x2
621#define INTC_INT_RISE_AND_FALL_EDGE 0x3
622#define INTC_INT_HIGH_LEVEL 0x5
623#define INTC_INT_LOW_LEVEL 0x6
624#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
625
626/* Interrupt Numbers */
627/* Au1000 */
628#ifdef CONFIG_SOC_AU1000
629#define AU1000_UART0_INT 0
630#define AU1000_UART1_INT 1 /* au1000 */
631#define AU1000_UART2_INT 2 /* au1000 */
632#define AU1000_UART3_INT 3
633#define AU1000_SSI0_INT 4 /* au1000 */
634#define AU1000_SSI1_INT 5 /* au1000 */
635#define AU1000_DMA_INT_BASE 6
636#define AU1000_TOY_INT 14
637#define AU1000_TOY_MATCH0_INT 15
638#define AU1000_TOY_MATCH1_INT 16
639#define AU1000_TOY_MATCH2_INT 17
640#define AU1000_RTC_INT 18
641#define AU1000_RTC_MATCH0_INT 19
642#define AU1000_RTC_MATCH1_INT 20
643#define AU1000_RTC_MATCH2_INT 21
644#define AU1000_IRDA_TX_INT 22 /* au1000 */
645#define AU1000_IRDA_RX_INT 23 /* au1000 */
646#define AU1000_USB_DEV_REQ_INT 24
647#define AU1000_USB_DEV_SUS_INT 25
648#define AU1000_USB_HOST_INT 26
649#define AU1000_ACSYNC_INT 27
650#define AU1000_MAC0_DMA_INT 28
651#define AU1000_MAC1_DMA_INT 29
652#define AU1000_I2S_UO_INT 30 /* au1000 */
653#define AU1000_AC97C_INT 31
654#define AU1000_GPIO_0 32
655#define AU1000_GPIO_1 33
656#define AU1000_GPIO_2 34
657#define AU1000_GPIO_3 35
658#define AU1000_GPIO_4 36
659#define AU1000_GPIO_5 37
660#define AU1000_GPIO_6 38
661#define AU1000_GPIO_7 39
662#define AU1000_GPIO_8 40
663#define AU1000_GPIO_9 41
664#define AU1000_GPIO_10 42
665#define AU1000_GPIO_11 43
666#define AU1000_GPIO_12 44
667#define AU1000_GPIO_13 45
668#define AU1000_GPIO_14 46
669#define AU1000_GPIO_15 47
670#define AU1000_GPIO_16 48
671#define AU1000_GPIO_17 49
672#define AU1000_GPIO_18 50
673#define AU1000_GPIO_19 51
674#define AU1000_GPIO_20 52
675#define AU1000_GPIO_21 53
676#define AU1000_GPIO_22 54
677#define AU1000_GPIO_23 55
678#define AU1000_GPIO_24 56
679#define AU1000_GPIO_25 57
680#define AU1000_GPIO_26 58
681#define AU1000_GPIO_27 59
682#define AU1000_GPIO_28 60
683#define AU1000_GPIO_29 61
684#define AU1000_GPIO_30 62
685#define AU1000_GPIO_31 63
686
687#define UART0_ADDR 0xB1100000
688#define UART1_ADDR 0xB1200000
689#define UART2_ADDR 0xB1300000
690#define UART3_ADDR 0xB1400000
691
692#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
693#define USB_HOST_CONFIG 0xB017fffc
694
695#define AU1000_ETH0_BASE 0xB0500000
696#define AU1000_ETH1_BASE 0xB0510000
697#define AU1000_MAC0_ENABLE 0xB0520000
698#define AU1000_MAC1_ENABLE 0xB0520004
699#define NUM_ETH_INTERFACES 2
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]700#endif /* CONFIG_SOC_AU1000 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]701
702/* Au1500 */
703#ifdef CONFIG_SOC_AU1500
704#define AU1500_UART0_INT 0
705#define AU1000_PCI_INTA 1 /* au1500 */
706#define AU1000_PCI_INTB 2 /* au1500 */
707#define AU1500_UART3_INT 3
708#define AU1000_PCI_INTC 4 /* au1500 */
709#define AU1000_PCI_INTD 5 /* au1500 */
710#define AU1000_DMA_INT_BASE 6
711#define AU1000_TOY_INT 14
712#define AU1000_TOY_MATCH0_INT 15
713#define AU1000_TOY_MATCH1_INT 16
714#define AU1000_TOY_MATCH2_INT 17
715#define AU1000_RTC_INT 18
716#define AU1000_RTC_MATCH0_INT 19
717#define AU1000_RTC_MATCH1_INT 20
718#define AU1000_RTC_MATCH2_INT 21
719#define AU1500_PCI_ERR_INT 22
720#define AU1000_USB_DEV_REQ_INT 24
721#define AU1000_USB_DEV_SUS_INT 25
722#define AU1000_USB_HOST_INT 26
723#define AU1000_ACSYNC_INT 27
724#define AU1500_MAC0_DMA_INT 28
725#define AU1500_MAC1_DMA_INT 29
726#define AU1000_AC97C_INT 31
727#define AU1000_GPIO_0 32
728#define AU1000_GPIO_1 33
729#define AU1000_GPIO_2 34
730#define AU1000_GPIO_3 35
731#define AU1000_GPIO_4 36
732#define AU1000_GPIO_5 37
733#define AU1000_GPIO_6 38
734#define AU1000_GPIO_7 39
735#define AU1000_GPIO_8 40
736#define AU1000_GPIO_9 41
737#define AU1000_GPIO_10 42
738#define AU1000_GPIO_11 43
739#define AU1000_GPIO_12 44
740#define AU1000_GPIO_13 45
741#define AU1000_GPIO_14 46
742#define AU1000_GPIO_15 47
743#define AU1500_GPIO_200 48
744#define AU1500_GPIO_201 49
745#define AU1500_GPIO_202 50
746#define AU1500_GPIO_203 51
747#define AU1500_GPIO_20 52
748#define AU1500_GPIO_204 53
749#define AU1500_GPIO_205 54
750#define AU1500_GPIO_23 55
751#define AU1500_GPIO_24 56
752#define AU1500_GPIO_25 57
753#define AU1500_GPIO_26 58
754#define AU1500_GPIO_27 59
755#define AU1500_GPIO_28 60
756#define AU1500_GPIO_206 61
757#define AU1500_GPIO_207 62
758#define AU1500_GPIO_208_215 63
759
Pete Popov2d32ffa2005-03-01 07:54:50 +0000[diff] [blame^]760/* shortcuts */
761#define INTA AU1000_PCI_INTA
762#define INTB AU1000_PCI_INTB
763#define INTC AU1000_PCI_INTC
764#define INTD AU1000_PCI_INTD
765
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]766#define UART0_ADDR 0xB1100000
767#define UART3_ADDR 0xB1400000
768
769#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
770#define USB_HOST_CONFIG 0xB017fffc
771
772#define AU1500_ETH0_BASE 0xB1500000
773#define AU1500_ETH1_BASE 0xB1510000
774#define AU1500_MAC0_ENABLE 0xB1520000
775#define AU1500_MAC1_ENABLE 0xB1520004
776#define NUM_ETH_INTERFACES 2
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]777#endif /* CONFIG_SOC_AU1500 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]778
779/* Au1100 */
780#ifdef CONFIG_SOC_AU1100
781#define AU1100_UART0_INT 0
782#define AU1100_UART1_INT 1
783#define AU1100_SD_INT 2
784#define AU1100_UART3_INT 3
785#define AU1000_SSI0_INT 4
786#define AU1000_SSI1_INT 5
787#define AU1000_DMA_INT_BASE 6
788#define AU1000_TOY_INT 14
789#define AU1000_TOY_MATCH0_INT 15
790#define AU1000_TOY_MATCH1_INT 16
791#define AU1000_TOY_MATCH2_INT 17
792#define AU1000_RTC_INT 18
793#define AU1000_RTC_MATCH0_INT 19
794#define AU1000_RTC_MATCH1_INT 20
795#define AU1000_RTC_MATCH2_INT 21
796#define AU1000_IRDA_TX_INT 22
797#define AU1000_IRDA_RX_INT 23
798#define AU1000_USB_DEV_REQ_INT 24
799#define AU1000_USB_DEV_SUS_INT 25
800#define AU1000_USB_HOST_INT 26
801#define AU1000_ACSYNC_INT 27
802#define AU1100_MAC0_DMA_INT 28
803#define AU1100_GPIO_208_215 29
804#define AU1100_LCD_INT 30
805#define AU1000_AC97C_INT 31
806#define AU1000_GPIO_0 32
807#define AU1000_GPIO_1 33
808#define AU1000_GPIO_2 34
809#define AU1000_GPIO_3 35
810#define AU1000_GPIO_4 36
811#define AU1000_GPIO_5 37
812#define AU1000_GPIO_6 38
813#define AU1000_GPIO_7 39
814#define AU1000_GPIO_8 40
815#define AU1000_GPIO_9 41
816#define AU1000_GPIO_10 42
817#define AU1000_GPIO_11 43
818#define AU1000_GPIO_12 44
819#define AU1000_GPIO_13 45
820#define AU1000_GPIO_14 46
821#define AU1000_GPIO_15 47
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]822#define AU1000_GPIO_16 48
823#define AU1000_GPIO_17 49
824#define AU1000_GPIO_18 50
825#define AU1000_GPIO_19 51
826#define AU1000_GPIO_20 52
827#define AU1000_GPIO_21 53
828#define AU1000_GPIO_22 54
829#define AU1000_GPIO_23 55
830#define AU1000_GPIO_24 56
831#define AU1000_GPIO_25 57
832#define AU1000_GPIO_26 58
833#define AU1000_GPIO_27 59
834#define AU1000_GPIO_28 60
835#define AU1000_GPIO_29 61
836#define AU1000_GPIO_30 62
837#define AU1000_GPIO_31 63
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]838
839#define UART0_ADDR 0xB1100000
840#define UART1_ADDR 0xB1200000
841#define UART3_ADDR 0xB1400000
842
843#define USB_OHCI_BASE 0x10100000 // phys addr for ioremap
844#define USB_HOST_CONFIG 0xB017fffc
845
846#define AU1100_ETH0_BASE 0xB0500000
847#define AU1100_MAC0_ENABLE 0xB0520000
848#define NUM_ETH_INTERFACES 1
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]849#endif /* CONFIG_SOC_AU1100 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]850
851#ifdef CONFIG_SOC_AU1550
852#define AU1550_UART0_INT 0
853#define AU1550_PCI_INTA 1
854#define AU1550_PCI_INTB 2
855#define AU1550_DDMA_INT 3
856#define AU1550_CRYPTO_INT 4
857#define AU1550_PCI_INTC 5
858#define AU1550_PCI_INTD 6
859#define AU1550_PCI_RST_INT 7
860#define AU1550_UART1_INT 8
861#define AU1550_UART3_INT 9
862#define AU1550_PSC0_INT 10
863#define AU1550_PSC1_INT 11
864#define AU1550_PSC2_INT 12
865#define AU1550_PSC3_INT 13
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]866#define AU1000_TOY_INT 14
867#define AU1000_TOY_MATCH0_INT 15
868#define AU1000_TOY_MATCH1_INT 16
869#define AU1000_TOY_MATCH2_INT 17
870#define AU1000_RTC_INT 18
871#define AU1000_RTC_MATCH0_INT 19
872#define AU1000_RTC_MATCH1_INT 20
873#define AU1000_RTC_MATCH2_INT 21
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]874#define AU1550_NAND_INT 23
875#define AU1550_USB_DEV_REQ_INT 24
876#define AU1550_USB_DEV_SUS_INT 25
877#define AU1550_USB_HOST_INT 26
878#define AU1000_USB_DEV_REQ_INT AU1550_USB_DEV_REQ_INT
879#define AU1000_USB_DEV_SUS_INT AU1550_USB_DEV_SUS_INT
880#define AU1000_USB_HOST_INT AU1550_USB_HOST_INT
881#define AU1550_MAC0_DMA_INT 27
882#define AU1550_MAC1_DMA_INT 28
883#define AU1000_GPIO_0 32
884#define AU1000_GPIO_1 33
885#define AU1000_GPIO_2 34
886#define AU1000_GPIO_3 35
887#define AU1000_GPIO_4 36
888#define AU1000_GPIO_5 37
889#define AU1000_GPIO_6 38
890#define AU1000_GPIO_7 39
891#define AU1000_GPIO_8 40
892#define AU1000_GPIO_9 41
893#define AU1000_GPIO_10 42
894#define AU1000_GPIO_11 43
895#define AU1000_GPIO_12 44
896#define AU1000_GPIO_13 45
897#define AU1000_GPIO_14 46
898#define AU1000_GPIO_15 47
899#define AU1550_GPIO_200 48
900#define AU1500_GPIO_201_205 49 // Logical or of GPIO201:205
901#define AU1500_GPIO_16 50
902#define AU1500_GPIO_17 51
903#define AU1500_GPIO_20 52
904#define AU1500_GPIO_21 53
905#define AU1500_GPIO_22 54
906#define AU1500_GPIO_23 55
907#define AU1500_GPIO_24 56
908#define AU1500_GPIO_25 57
909#define AU1500_GPIO_26 58
910#define AU1500_GPIO_27 59
911#define AU1500_GPIO_28 60
912#define AU1500_GPIO_206 61
913#define AU1500_GPIO_207 62
914#define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218
915
Pete Popov2d32ffa2005-03-01 07:54:50 +0000[diff] [blame^]916/* shortcuts */
917#define INTA AU1550_PCI_INTA
918#define INTB AU1550_PCI_INTB
919#define INTC AU1550_PCI_INTC
920#define INTD AU1550_PCI_INTD
921
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]922#define UART0_ADDR 0xB1100000
923#define UART1_ADDR 0xB1200000
924#define UART3_ADDR 0xB1400000
925
926#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap
927#define USB_HOST_CONFIG 0xB4027ffc
928
929#define AU1550_ETH0_BASE 0xB0500000
930#define AU1550_ETH1_BASE 0xB0510000
931#define AU1550_MAC0_ENABLE 0xB0520000
932#define AU1550_MAC1_ENABLE 0xB0520004
933#define NUM_ETH_INTERFACES 2
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]934#endif /* CONFIG_SOC_AU1550 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]935
936#ifdef CONFIG_SOC_AU1200
937#define AU1200_UART0_INT 0
938#define AU1200_SWT_INT 1
939#define AU1200_SD_INT 2
940#define AU1200_DDMA_INT 3
941#define AU1200_MAE_BE_INT 4
942#define AU1200_GPIO_200 5
943#define AU1200_GPIO_201 6
944#define AU1200_GPIO_202 7
945#define AU1200_UART1_INT 8
946#define AU1200_MAE_FE_INT 9
947#define AU1200_PSC0_INT 10
948#define AU1200_PSC1_INT 11
949#define AU1200_AES_INT 12
950#define AU1200_CAMERA_INT 13
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]951#define AU1000_TOY_INT 14
952#define AU1000_TOY_MATCH0_INT 15
953#define AU1000_TOY_MATCH1_INT 16
954#define AU1000_TOY_MATCH2_INT 17
955#define AU1000_RTC_INT 18
956#define AU1000_RTC_MATCH0_INT 19
957#define AU1000_RTC_MATCH1_INT 20
958#define AU1000_RTC_MATCH2_INT 21
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]959#define AU1200_NAND_INT 23
960#define AU1200_GPIO_204 24
961#define AU1200_GPIO_205 25
962#define AU1200_GPIO_206 26
963#define AU1200_GPIO_207 27
964#define AU1200_GPIO_208_215 28 // Logical OR of 208:215
965#define AU1200_USB_INT 29
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]966#define AU1000_USB_HOST_INT AU1200_USB_INT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]967#define AU1200_LCD_INT 30
968#define AU1200_MAE_BOTH_INT 31
969#define AU1000_GPIO_0 32
970#define AU1000_GPIO_1 33
971#define AU1000_GPIO_2 34
972#define AU1000_GPIO_3 35
973#define AU1000_GPIO_4 36
974#define AU1000_GPIO_5 37
975#define AU1000_GPIO_6 38
976#define AU1000_GPIO_7 39
977#define AU1000_GPIO_8 40
978#define AU1000_GPIO_9 41
979#define AU1000_GPIO_10 42
980#define AU1000_GPIO_11 43
981#define AU1000_GPIO_12 44
982#define AU1000_GPIO_13 45
983#define AU1000_GPIO_14 46
984#define AU1000_GPIO_15 47
985#define AU1000_GPIO_16 48
986#define AU1000_GPIO_17 49
987#define AU1000_GPIO_18 50
988#define AU1000_GPIO_19 51
989#define AU1000_GPIO_20 52
990#define AU1000_GPIO_21 53
991#define AU1000_GPIO_22 54
992#define AU1000_GPIO_23 55
993#define AU1000_GPIO_24 56
994#define AU1000_GPIO_25 57
995#define AU1000_GPIO_26 58
996#define AU1000_GPIO_27 59
997#define AU1000_GPIO_28 60
998#define AU1000_GPIO_29 61
999#define AU1000_GPIO_30 62
1000#define AU1000_GPIO_31 63
1001
1002#define UART0_ADDR 0xB1100000
1003#define UART1_ADDR 0xB1200000
1004
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]1005#define USB_UOC_BASE 0x14020020
1006#define USB_UOC_LEN 0x20
1007#define USB_OHCI_BASE 0x14020100
1008#define USB_OHCI_LEN 0x100
1009#define USB_EHCI_BASE 0x14020200
1010#define USB_EHCI_LEN 0x100
1011#define USB_UDC_BASE 0x14022000
1012#define USB_UDC_LEN 0x2000
1013#define USB_MSR_BASE 0xB4020000
1014#define USB_MSR_MCFG 4
1015#define USBMSRMCFG_OMEMEN 0
1016#define USBMSRMCFG_OBMEN 1
1017#define USBMSRMCFG_EMEMEN 2
1018#define USBMSRMCFG_EBMEN 3
1019#define USBMSRMCFG_DMEMEN 4
1020#define USBMSRMCFG_DBMEN 5
1021#define USBMSRMCFG_GMEMEN 6
1022#define USBMSRMCFG_OHCCLKEN 16
1023#define USBMSRMCFG_EHCCLKEN 17
1024#define USBMSRMCFG_UDCCLKEN 18
1025#define USBMSRMCFG_PHYPLLEN 19
1026#define USBMSRMCFG_RDCOMB 30
1027#define USBMSRMCFG_PFEN 31
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1028
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]1029#endif /* CONFIG_SOC_AU1200 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1030
1031#define AU1000_LAST_INTC0_INT 31
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]1032#define AU1000_LAST_INTC1_INT 63
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1033#define AU1000_MAX_INTR 63
Pete Popov2d32ffa2005-03-01 07:54:50 +0000[diff] [blame^]1034#define INTX 0xFF /* not valid */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1035
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1036/* Programmable Counters 0 and 1 */
1037#define SYS_BASE 0xB1900000
1038#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
1039 #define SYS_CNTRL_E1S (1<<23)
1040 #define SYS_CNTRL_T1S (1<<20)
1041 #define SYS_CNTRL_M21 (1<<19)
1042 #define SYS_CNTRL_M11 (1<<18)
1043 #define SYS_CNTRL_M01 (1<<17)
1044 #define SYS_CNTRL_C1S (1<<16)
1045 #define SYS_CNTRL_BP (1<<14)
1046 #define SYS_CNTRL_EN1 (1<<13)
1047 #define SYS_CNTRL_BT1 (1<<12)
1048 #define SYS_CNTRL_EN0 (1<<11)
1049 #define SYS_CNTRL_BT0 (1<<10)
1050 #define SYS_CNTRL_E0 (1<<8)
1051 #define SYS_CNTRL_E0S (1<<7)
1052 #define SYS_CNTRL_32S (1<<5)
1053 #define SYS_CNTRL_T0S (1<<4)
1054 #define SYS_CNTRL_M20 (1<<3)
1055 #define SYS_CNTRL_M10 (1<<2)
1056 #define SYS_CNTRL_M00 (1<<1)
1057 #define SYS_CNTRL_C0S (1<<0)
1058
1059/* Programmable Counter 0 Registers */
1060#define SYS_TOYTRIM (SYS_BASE + 0)
1061#define SYS_TOYWRITE (SYS_BASE + 4)
1062#define SYS_TOYMATCH0 (SYS_BASE + 8)
1063#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
1064#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
1065#define SYS_TOYREAD (SYS_BASE + 0x40)
1066
1067/* Programmable Counter 1 Registers */
1068#define SYS_RTCTRIM (SYS_BASE + 0x44)
1069#define SYS_RTCWRITE (SYS_BASE + 0x48)
1070#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
1071#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
1072#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
1073#define SYS_RTCREAD (SYS_BASE + 0x58)
1074
1075/* I2S Controller */
1076#define I2S_DATA 0xB1000000
1077 #define I2S_DATA_MASK (0xffffff)
1078#define I2S_CONFIG 0xB1000004
1079 #define I2S_CONFIG_XU (1<<25)
1080 #define I2S_CONFIG_XO (1<<24)
1081 #define I2S_CONFIG_RU (1<<23)
1082 #define I2S_CONFIG_RO (1<<22)
1083 #define I2S_CONFIG_TR (1<<21)
1084 #define I2S_CONFIG_TE (1<<20)
1085 #define I2S_CONFIG_TF (1<<19)
1086 #define I2S_CONFIG_RR (1<<18)
1087 #define I2S_CONFIG_RE (1<<17)
1088 #define I2S_CONFIG_RF (1<<16)
1089 #define I2S_CONFIG_PD (1<<11)
1090 #define I2S_CONFIG_LB (1<<10)
1091 #define I2S_CONFIG_IC (1<<9)
1092 #define I2S_CONFIG_FM_BIT 7
1093 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1094 #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1095 #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1096 #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1097 #define I2S_CONFIG_TN (1<<6)
1098 #define I2S_CONFIG_RN (1<<5)
1099 #define I2S_CONFIG_SZ_BIT 0
1100 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1101
1102#define I2S_CONTROL 0xB1000008
1103 #define I2S_CONTROL_D (1<<1)
1104 #define I2S_CONTROL_CE (1<<0)
1105
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]1106#ifndef CONFIG_SOC_AU1200
1107
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1108/* USB Host Controller */
1109#define USB_OHCI_LEN 0x00100000
1110
1111/* USB Device Controller */
1112#define USBD_EP0RD 0xB0200000
1113#define USBD_EP0WR 0xB0200004
1114#define USBD_EP2WR 0xB0200008
1115#define USBD_EP3WR 0xB020000C
1116#define USBD_EP4RD 0xB0200010
1117#define USBD_EP5RD 0xB0200014
1118#define USBD_INTEN 0xB0200018
1119#define USBD_INTSTAT 0xB020001C
1120 #define USBDEV_INT_SOF (1<<12)
1121 #define USBDEV_INT_HF_BIT 6
1122 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1123 #define USBDEV_INT_CMPLT_BIT 0
1124 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1125#define USBD_CONFIG 0xB0200020
1126#define USBD_EP0CS 0xB0200024
1127#define USBD_EP2CS 0xB0200028
1128#define USBD_EP3CS 0xB020002C
1129#define USBD_EP4CS 0xB0200030
1130#define USBD_EP5CS 0xB0200034
1131 #define USBDEV_CS_SU (1<<14)
1132 #define USBDEV_CS_NAK (1<<13)
1133 #define USBDEV_CS_ACK (1<<12)
1134 #define USBDEV_CS_BUSY (1<<11)
1135 #define USBDEV_CS_TSIZE_BIT 1
1136 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1137 #define USBDEV_CS_STALL (1<<0)
1138#define USBD_EP0RDSTAT 0xB0200040
1139#define USBD_EP0WRSTAT 0xB0200044
1140#define USBD_EP2WRSTAT 0xB0200048
1141#define USBD_EP3WRSTAT 0xB020004C
1142#define USBD_EP4RDSTAT 0xB0200050
1143#define USBD_EP5RDSTAT 0xB0200054
1144 #define USBDEV_FSTAT_FLUSH (1<<6)
1145 #define USBDEV_FSTAT_UF (1<<5)
1146 #define USBDEV_FSTAT_OF (1<<4)
1147 #define USBDEV_FSTAT_FCNT_BIT 0
1148 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1149#define USBD_ENABLE 0xB0200058
1150 #define USBDEV_ENABLE (1<<1)
1151 #define USBDEV_CE (1<<0)
1152
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]1153#endif /* !CONFIG_SOC_AU1200 */
1154
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1155/* Ethernet Controllers */
1156
1157/* 4 byte offsets from AU1000_ETH_BASE */
1158#define MAC_CONTROL 0x0
1159 #define MAC_RX_ENABLE (1<<2)
1160 #define MAC_TX_ENABLE (1<<3)
1161 #define MAC_DEF_CHECK (1<<5)
1162 #define MAC_SET_BL(X) (((X)&0x3)<<6)
1163 #define MAC_AUTO_PAD (1<<8)
1164 #define MAC_DISABLE_RETRY (1<<10)
1165 #define MAC_DISABLE_BCAST (1<<11)
1166 #define MAC_LATE_COL (1<<12)
1167 #define MAC_HASH_MODE (1<<13)
1168 #define MAC_HASH_ONLY (1<<15)
1169 #define MAC_PASS_ALL (1<<16)
1170 #define MAC_INVERSE_FILTER (1<<17)
1171 #define MAC_PROMISCUOUS (1<<18)
1172 #define MAC_PASS_ALL_MULTI (1<<19)
1173 #define MAC_FULL_DUPLEX (1<<20)
1174 #define MAC_NORMAL_MODE 0
1175 #define MAC_INT_LOOPBACK (1<<21)
1176 #define MAC_EXT_LOOPBACK (1<<22)
1177 #define MAC_DISABLE_RX_OWN (1<<23)
1178 #define MAC_BIG_ENDIAN (1<<30)
1179 #define MAC_RX_ALL (1<<31)
1180#define MAC_ADDRESS_HIGH 0x4
1181#define MAC_ADDRESS_LOW 0x8
1182#define MAC_MCAST_HIGH 0xC
1183#define MAC_MCAST_LOW 0x10
1184#define MAC_MII_CNTRL 0x14
1185 #define MAC_MII_BUSY (1<<0)
1186 #define MAC_MII_READ 0
1187 #define MAC_MII_WRITE (1<<1)
1188 #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
1189 #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
1190#define MAC_MII_DATA 0x18
1191#define MAC_FLOW_CNTRL 0x1C
1192 #define MAC_FLOW_CNTRL_BUSY (1<<0)
1193 #define MAC_FLOW_CNTRL_ENABLE (1<<1)
1194 #define MAC_PASS_CONTROL (1<<2)
1195 #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
1196#define MAC_VLAN1_TAG 0x20
1197#define MAC_VLAN2_TAG 0x24
1198
1199/* Ethernet Controller Enable */
1200
1201 #define MAC_EN_CLOCK_ENABLE (1<<0)
1202 #define MAC_EN_RESET0 (1<<1)
1203 #define MAC_EN_TOSS (0<<2)
1204 #define MAC_EN_CACHEABLE (1<<3)
1205 #define MAC_EN_RESET1 (1<<4)
1206 #define MAC_EN_RESET2 (1<<5)
1207 #define MAC_DMA_RESET (1<<6)
1208
1209/* Ethernet Controller DMA Channels */
1210
1211#define MAC0_TX_DMA_ADDR 0xB4004000
1212#define MAC1_TX_DMA_ADDR 0xB4004200
1213/* offsets from MAC_TX_RING_ADDR address */
1214#define MAC_TX_BUFF0_STATUS 0x0
1215 #define TX_FRAME_ABORTED (1<<0)
1216 #define TX_JAB_TIMEOUT (1<<1)
1217 #define TX_NO_CARRIER (1<<2)
1218 #define TX_LOSS_CARRIER (1<<3)
1219 #define TX_EXC_DEF (1<<4)
1220 #define TX_LATE_COLL_ABORT (1<<5)
1221 #define TX_EXC_COLL (1<<6)
1222 #define TX_UNDERRUN (1<<7)
1223 #define TX_DEFERRED (1<<8)
1224 #define TX_LATE_COLL (1<<9)
1225 #define TX_COLL_CNT_MASK (0xF<<10)
1226 #define TX_PKT_RETRY (1<<31)
1227#define MAC_TX_BUFF0_ADDR 0x4
1228 #define TX_DMA_ENABLE (1<<0)
1229 #define TX_T_DONE (1<<1)
1230 #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
1231#define MAC_TX_BUFF0_LEN 0x8
1232#define MAC_TX_BUFF1_STATUS 0x10
1233#define MAC_TX_BUFF1_ADDR 0x14
1234#define MAC_TX_BUFF1_LEN 0x18
1235#define MAC_TX_BUFF2_STATUS 0x20
1236#define MAC_TX_BUFF2_ADDR 0x24
1237#define MAC_TX_BUFF2_LEN 0x28
1238#define MAC_TX_BUFF3_STATUS 0x30
1239#define MAC_TX_BUFF3_ADDR 0x34
1240#define MAC_TX_BUFF3_LEN 0x38
1241
1242#define MAC0_RX_DMA_ADDR 0xB4004100
1243#define MAC1_RX_DMA_ADDR 0xB4004300
1244/* offsets from MAC_RX_RING_ADDR */
1245#define MAC_RX_BUFF0_STATUS 0x0
1246 #define RX_FRAME_LEN_MASK 0x3fff
1247 #define RX_WDOG_TIMER (1<<14)
1248 #define RX_RUNT (1<<15)
1249 #define RX_OVERLEN (1<<16)
1250 #define RX_COLL (1<<17)
1251 #define RX_ETHER (1<<18)
1252 #define RX_MII_ERROR (1<<19)
1253 #define RX_DRIBBLING (1<<20)
1254 #define RX_CRC_ERROR (1<<21)
1255 #define RX_VLAN1 (1<<22)
1256 #define RX_VLAN2 (1<<23)
1257 #define RX_LEN_ERROR (1<<24)
1258 #define RX_CNTRL_FRAME (1<<25)
1259 #define RX_U_CNTRL_FRAME (1<<26)
1260 #define RX_MCAST_FRAME (1<<27)
1261 #define RX_BCAST_FRAME (1<<28)
1262 #define RX_FILTER_FAIL (1<<29)
1263 #define RX_PACKET_FILTER (1<<30)
1264 #define RX_MISSED_FRAME (1<<31)
1265
1266 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1267 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1268 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1269#define MAC_RX_BUFF0_ADDR 0x4
1270 #define RX_DMA_ENABLE (1<<0)
1271 #define RX_T_DONE (1<<1)
1272 #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
1273 #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
1274#define MAC_RX_BUFF1_STATUS 0x10
1275#define MAC_RX_BUFF1_ADDR 0x14
1276#define MAC_RX_BUFF2_STATUS 0x20
1277#define MAC_RX_BUFF2_ADDR 0x24
1278#define MAC_RX_BUFF3_STATUS 0x30
1279#define MAC_RX_BUFF3_ADDR 0x34
1280
1281
1282/* UARTS 0-3 */
1283#define UART_BASE UART0_ADDR
1284#define UART_DEBUG_BASE UART3_ADDR
1285
1286#define UART_RX 0 /* Receive buffer */
1287#define UART_TX 4 /* Transmit buffer */
1288#define UART_IER 8 /* Interrupt Enable Register */
1289#define UART_IIR 0xC /* Interrupt ID Register */
1290#define UART_FCR 0x10 /* FIFO Control Register */
1291#define UART_LCR 0x14 /* Line Control Register */
1292#define UART_MCR 0x18 /* Modem Control Register */
1293#define UART_LSR 0x1C /* Line Status Register */
1294#define UART_MSR 0x20 /* Modem Status Register */
1295#define UART_CLK 0x28 /* Baud Rate Clock Divider */
1296#define UART_MOD_CNTRL 0x100 /* Module Control */
1297
1298#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1299#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1300#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1301#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1302#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
1303#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
1304#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
1305#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
1306#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
1307#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
1308#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
1309#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
1310#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
1311
1312/*
1313 * These are the definitions for the Line Control Register
1314 */
1315#define UART_LCR_SBC 0x40 /* Set break control */
1316#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1317#define UART_LCR_EPAR 0x10 /* Even parity select */
1318#define UART_LCR_PARITY 0x08 /* Parity Enable */
1319#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
1320#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1321#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1322#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1323#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1324
1325/*
1326 * These are the definitions for the Line Status Register
1327 */
1328#define UART_LSR_TEMT 0x40 /* Transmitter empty */
1329#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1330#define UART_LSR_BI 0x10 /* Break interrupt indicator */
1331#define UART_LSR_FE 0x08 /* Frame error indicator */
1332#define UART_LSR_PE 0x04 /* Parity error indicator */
1333#define UART_LSR_OE 0x02 /* Overrun error indicator */
1334#define UART_LSR_DR 0x01 /* Receiver data ready */
1335
1336/*
1337 * These are the definitions for the Interrupt Identification Register
1338 */
1339#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1340#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1341#define UART_IIR_MSI 0x00 /* Modem status interrupt */
1342#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1343#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1344#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1345
1346/*
1347 * These are the definitions for the Interrupt Enable Register
1348 */
1349#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1350#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1351#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1352#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1353
1354/*
1355 * These are the definitions for the Modem Control Register
1356 */
1357#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1358#define UART_MCR_OUT2 0x08 /* Out2 complement */
1359#define UART_MCR_OUT1 0x04 /* Out1 complement */
1360#define UART_MCR_RTS 0x02 /* RTS complement */
1361#define UART_MCR_DTR 0x01 /* DTR complement */
1362
1363/*
1364 * These are the definitions for the Modem Status Register
1365 */
1366#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1367#define UART_MSR_RI 0x40 /* Ring Indicator */
1368#define UART_MSR_DSR 0x20 /* Data Set Ready */
1369#define UART_MSR_CTS 0x10 /* Clear to Send */
1370#define UART_MSR_DDCD 0x08 /* Delta DCD */
1371#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1372#define UART_MSR_DDSR 0x02 /* Delta DSR */
1373#define UART_MSR_DCTS 0x01 /* Delta CTS */
1374#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1375
1376
1377
1378/* SSIO */
1379#define SSI0_STATUS 0xB1600000
1380 #define SSI_STATUS_BF (1<<4)
1381 #define SSI_STATUS_OF (1<<3)
1382 #define SSI_STATUS_UF (1<<2)
1383 #define SSI_STATUS_D (1<<1)
1384 #define SSI_STATUS_B (1<<0)
1385#define SSI0_INT 0xB1600004
1386 #define SSI_INT_OI (1<<3)
1387 #define SSI_INT_UI (1<<2)
1388 #define SSI_INT_DI (1<<1)
1389#define SSI0_INT_ENABLE 0xB1600008
1390 #define SSI_INTE_OIE (1<<3)
1391 #define SSI_INTE_UIE (1<<2)
1392 #define SSI_INTE_DIE (1<<1)
1393#define SSI0_CONFIG 0xB1600020
1394 #define SSI_CONFIG_AO (1<<24)
1395 #define SSI_CONFIG_DO (1<<23)
1396 #define SSI_CONFIG_ALEN_BIT 20
1397 #define SSI_CONFIG_ALEN_MASK (0x7<<20)
1398 #define SSI_CONFIG_DLEN_BIT 16
1399 #define SSI_CONFIG_DLEN_MASK (0x7<<16)
1400 #define SSI_CONFIG_DD (1<<11)
1401 #define SSI_CONFIG_AD (1<<10)
1402 #define SSI_CONFIG_BM_BIT 8
1403 #define SSI_CONFIG_BM_MASK (0x3<<8)
1404 #define SSI_CONFIG_CE (1<<7)
1405 #define SSI_CONFIG_DP (1<<6)
1406 #define SSI_CONFIG_DL (1<<5)
1407 #define SSI_CONFIG_EP (1<<4)
1408#define SSI0_ADATA 0xB1600024
1409 #define SSI_AD_D (1<<24)
1410 #define SSI_AD_ADDR_BIT 16
1411 #define SSI_AD_ADDR_MASK (0xff<<16)
1412 #define SSI_AD_DATA_BIT 0
1413 #define SSI_AD_DATA_MASK (0xfff<<0)
1414#define SSI0_CLKDIV 0xB1600028
1415#define SSI0_CONTROL 0xB1600100
1416 #define SSI_CONTROL_CD (1<<1)
1417 #define SSI_CONTROL_E (1<<0)
1418
1419/* SSI1 */
1420#define SSI1_STATUS 0xB1680000
1421#define SSI1_INT 0xB1680004
1422#define SSI1_INT_ENABLE 0xB1680008
1423#define SSI1_CONFIG 0xB1680020
1424#define SSI1_ADATA 0xB1680024
1425#define SSI1_CLKDIV 0xB1680028
1426#define SSI1_ENABLE 0xB1680100
1427
1428/*
1429 * Register content definitions
1430 */
1431#define SSI_STATUS_BF (1<<4)
1432#define SSI_STATUS_OF (1<<3)
1433#define SSI_STATUS_UF (1<<2)
1434#define SSI_STATUS_D (1<<1)
1435#define SSI_STATUS_B (1<<0)
1436
1437/* SSI_INT */
1438#define SSI_INT_OI (1<<3)
1439#define SSI_INT_UI (1<<2)
1440#define SSI_INT_DI (1<<1)
1441
1442/* SSI_INTEN */
1443#define SSI_INTEN_OIE (1<<3)
1444#define SSI_INTEN_UIE (1<<2)
1445#define SSI_INTEN_DIE (1<<1)
1446
1447#define SSI_CONFIG_AO (1<<24)
1448#define SSI_CONFIG_DO (1<<23)
1449#define SSI_CONFIG_ALEN (7<<20)
1450#define SSI_CONFIG_DLEN (15<<16)
1451#define SSI_CONFIG_DD (1<<11)
1452#define SSI_CONFIG_AD (1<<10)
1453#define SSI_CONFIG_BM (3<<8)
1454#define SSI_CONFIG_CE (1<<7)
1455#define SSI_CONFIG_DP (1<<6)
1456#define SSI_CONFIG_DL (1<<5)
1457#define SSI_CONFIG_EP (1<<4)
1458#define SSI_CONFIG_ALEN_N(N) ((N-1)<<20)
1459#define SSI_CONFIG_DLEN_N(N) ((N-1)<<16)
1460#define SSI_CONFIG_BM_HI (0<<8)
1461#define SSI_CONFIG_BM_LO (1<<8)
1462#define SSI_CONFIG_BM_CY (2<<8)
1463
1464#define SSI_ADATA_D (1<<24)
1465#define SSI_ADATA_ADDR (0xFF<<16)
1466#define SSI_ADATA_DATA (0x0FFF)
1467#define SSI_ADATA_ADDR_N(N) (N<<16)
1468
1469#define SSI_ENABLE_CD (1<<1)
1470#define SSI_ENABLE_E (1<<0)
1471
1472
1473/* IrDA Controller */
1474#define IRDA_BASE 0xB0300000
1475#define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
1476#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
1477#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
1478#define IR_RING_SIZE (IRDA_BASE+0x0C)
1479#define IR_RING_PROMPT (IRDA_BASE+0x10)
1480#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
1481#define IR_INT_CLEAR (IRDA_BASE+0x18)
1482#define IR_CONFIG_1 (IRDA_BASE+0x20)
1483 #define IR_RX_INVERT_LED (1<<0)
1484 #define IR_TX_INVERT_LED (1<<1)
1485 #define IR_ST (1<<2)
1486 #define IR_SF (1<<3)
1487 #define IR_SIR (1<<4)
1488 #define IR_MIR (1<<5)
1489 #define IR_FIR (1<<6)
1490 #define IR_16CRC (1<<7)
1491 #define IR_TD (1<<8)
1492 #define IR_RX_ALL (1<<9)
1493 #define IR_DMA_ENABLE (1<<10)
1494 #define IR_RX_ENABLE (1<<11)
1495 #define IR_TX_ENABLE (1<<12)
1496 #define IR_LOOPBACK (1<<14)
1497 #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1498 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1499#define IR_SIR_FLAGS (IRDA_BASE+0x24)
1500#define IR_ENABLE (IRDA_BASE+0x28)
1501 #define IR_RX_STATUS (1<<9)
1502 #define IR_TX_STATUS (1<<10)
1503#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
1504#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
1505#define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
1506#define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
1507#define IR_CONFIG_2 (IRDA_BASE+0x3C)
1508 #define IR_MODE_INV (1<<0)
1509 #define IR_ONE_PIN (1<<1)
1510#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
1511
1512/* GPIO */
1513#define SYS_PINFUNC 0xB190002C
1514 #define SYS_PF_USB (1<<15) /* 2nd USB device/host */
1515 #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
1516 #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
1517 #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
1518 #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
1519 #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
1520 #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
1521 #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
1522 #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
1523 #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
1524 #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
1525 #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
1526 #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
1527 #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
1528 #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
1529 #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
1530
1531/* Au1100 Only */
1532 #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */
1533 #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */
1534 #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */
1535 #define SYS_PF_EX0 (1<<9) /* gpio2/clock */
1536
1537/* Au1550 Only. Redefines lots of pins */
1538 #define SYS_PF_PSC2_MASK (7 << 17)
1539 #define SYS_PF_PSC2_AC97 (0)
1540 #define SYS_PF_PSC2_SPI (0)
1541 #define SYS_PF_PSC2_I2S (1 << 17)
1542 #define SYS_PF_PSC2_SMBUS (3 << 17)
1543 #define SYS_PF_PSC2_GPIO (7 << 17)
1544 #define SYS_PF_PSC3_MASK (7 << 20)
1545 #define SYS_PF_PSC3_AC97 (0)
1546 #define SYS_PF_PSC3_SPI (0)
1547 #define SYS_PF_PSC3_I2S (1 << 20)
1548 #define SYS_PF_PSC3_SMBUS (3 << 20)
1549 #define SYS_PF_PSC3_GPIO (7 << 20)
1550 #define SYS_PF_PSC1_S1 (1 << 1)
1551 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1552
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]1553/* Au1200 Only */
1554#ifdef CONFIG_SOC_AU1200
1555#define SYS_PINFUNC_DMA (1<<31)
1556#define SYS_PINFUNC_S0A (1<<30)
1557#define SYS_PINFUNC_S1A (1<<29)
1558#define SYS_PINFUNC_LP0 (1<<28)
1559#define SYS_PINFUNC_LP1 (1<<27)
1560#define SYS_PINFUNC_LD16 (1<<26)
1561#define SYS_PINFUNC_LD8 (1<<25)
1562#define SYS_PINFUNC_LD1 (1<<24)
1563#define SYS_PINFUNC_LD0 (1<<23)
1564#define SYS_PINFUNC_P1A (3<<21)
1565#define SYS_PINFUNC_P1B (1<<20)
1566#define SYS_PINFUNC_FS3 (1<<19)
1567#define SYS_PINFUNC_P0A (3<<17)
1568#define SYS_PINFUNC_CS (1<<16)
1569#define SYS_PINFUNC_CIM (1<<15)
1570#define SYS_PINFUNC_P1C (1<<14)
1571#define SYS_PINFUNC_U1T (1<<12)
1572#define SYS_PINFUNC_U1R (1<<11)
1573#define SYS_PINFUNC_EX1 (1<<10)
1574#define SYS_PINFUNC_EX0 (1<<9)
1575#define SYS_PINFUNC_U0R (1<<8)
1576#define SYS_PINFUNC_MC (1<<7)
1577#define SYS_PINFUNC_S0B (1<<6)
1578#define SYS_PINFUNC_S0C (1<<5)
1579#define SYS_PINFUNC_P0B (1<<4)
1580#define SYS_PINFUNC_U0T (1<<3)
1581#define SYS_PINFUNC_S1B (1<<2)
1582#endif
1583
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1584#define SYS_TRIOUTRD 0xB1900100
1585#define SYS_TRIOUTCLR 0xB1900100
1586#define SYS_OUTPUTRD 0xB1900108
1587#define SYS_OUTPUTSET 0xB1900108
1588#define SYS_OUTPUTCLR 0xB190010C
1589#define SYS_PINSTATERD 0xB1900110
1590#define SYS_PININPUTEN 0xB1900110
1591
1592/* GPIO2, Au1500, Au1550 only */
1593#define GPIO2_BASE 0xB1700000
1594#define GPIO2_DIR (GPIO2_BASE + 0)
1595#define GPIO2_OUTPUT (GPIO2_BASE + 8)
1596#define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1597#define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1598#define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1599
1600/* Power Management */
1601#define SYS_SCRATCH0 0xB1900018
1602#define SYS_SCRATCH1 0xB190001C
1603#define SYS_WAKEMSK 0xB1900034
1604#define SYS_ENDIAN 0xB1900038
1605#define SYS_POWERCTRL 0xB190003C
1606#define SYS_WAKESRC 0xB190005C
1607#define SYS_SLPPWR 0xB1900078
1608#define SYS_SLEEP 0xB190007C
1609
1610/* Clock Controller */
1611#define SYS_FREQCTRL0 0xB1900020
1612 #define SYS_FC_FRDIV2_BIT 22
1613 #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1614 #define SYS_FC_FE2 (1<<21)
1615 #define SYS_FC_FS2 (1<<20)
1616 #define SYS_FC_FRDIV1_BIT 12
1617 #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1618 #define SYS_FC_FE1 (1<<11)
1619 #define SYS_FC_FS1 (1<<10)
1620 #define SYS_FC_FRDIV0_BIT 2
1621 #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1622 #define SYS_FC_FE0 (1<<1)
1623 #define SYS_FC_FS0 (1<<0)
1624#define SYS_FREQCTRL1 0xB1900024
1625 #define SYS_FC_FRDIV5_BIT 22
1626 #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1627 #define SYS_FC_FE5 (1<<21)
1628 #define SYS_FC_FS5 (1<<20)
1629 #define SYS_FC_FRDIV4_BIT 12
1630 #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1631 #define SYS_FC_FE4 (1<<11)
1632 #define SYS_FC_FS4 (1<<10)
1633 #define SYS_FC_FRDIV3_BIT 2
1634 #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1635 #define SYS_FC_FE3 (1<<1)
1636 #define SYS_FC_FS3 (1<<0)
1637#define SYS_CLKSRC 0xB1900028
1638 #define SYS_CS_ME1_BIT 27
1639 #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT)
1640 #define SYS_CS_DE1 (1<<26)
1641 #define SYS_CS_CE1 (1<<25)
1642 #define SYS_CS_ME0_BIT 22
1643 #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT)
1644 #define SYS_CS_DE0 (1<<21)
1645 #define SYS_CS_CE0 (1<<20)
1646 #define SYS_CS_MI2_BIT 17
1647 #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
1648 #define SYS_CS_DI2 (1<<16)
1649 #define SYS_CS_CI2 (1<<15)
1650 #define SYS_CS_MUH_BIT 12
1651 #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
1652 #define SYS_CS_DUH (1<<11)
1653 #define SYS_CS_CUH (1<<10)
1654 #define SYS_CS_MUD_BIT 7
1655 #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
1656 #define SYS_CS_DUD (1<<6)
1657 #define SYS_CS_CUD (1<<5)
1658 #define SYS_CS_MIR_BIT 2
1659 #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
1660 #define SYS_CS_DIR (1<<1)
1661 #define SYS_CS_CIR (1<<0)
1662
1663 #define SYS_CS_MUX_AUX 0x1
1664 #define SYS_CS_MUX_FQ0 0x2
1665 #define SYS_CS_MUX_FQ1 0x3
1666 #define SYS_CS_MUX_FQ2 0x4
1667 #define SYS_CS_MUX_FQ3 0x5
1668 #define SYS_CS_MUX_FQ4 0x6
1669 #define SYS_CS_MUX_FQ5 0x7
1670#define SYS_CPUPLL 0xB1900060
1671#define SYS_AUXPLL 0xB1900064
1672
1673/* AC97 Controller */
1674#define AC97C_CONFIG 0xB0000000
1675 #define AC97C_RECV_SLOTS_BIT 13
1676 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1677 #define AC97C_XMIT_SLOTS_BIT 3
1678 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1679 #define AC97C_SG (1<<2)
1680 #define AC97C_SYNC (1<<1)
1681 #define AC97C_RESET (1<<0)
1682#define AC97C_STATUS 0xB0000004
1683 #define AC97C_XU (1<<11)
1684 #define AC97C_XO (1<<10)
1685 #define AC97C_RU (1<<9)
1686 #define AC97C_RO (1<<8)
1687 #define AC97C_READY (1<<7)
1688 #define AC97C_CP (1<<6)
1689 #define AC97C_TR (1<<5)
1690 #define AC97C_TE (1<<4)
1691 #define AC97C_TF (1<<3)
1692 #define AC97C_RR (1<<2)
1693 #define AC97C_RE (1<<1)
1694 #define AC97C_RF (1<<0)
1695#define AC97C_DATA 0xB0000008
1696#define AC97C_CMD 0xB000000C
1697 #define AC97C_WD_BIT 16
1698 #define AC97C_READ (1<<7)
1699 #define AC97C_INDEX_MASK 0x7f
1700#define AC97C_CNTRL 0xB0000010
1701 #define AC97C_RS (1<<1)
1702 #define AC97C_CE (1<<0)
1703
1704
1705/* Secure Digital (SD) Controller */
1706#define SD0_XMIT_FIFO 0xB0600000
1707#define SD0_RECV_FIFO 0xB0600004
1708#define SD1_XMIT_FIFO 0xB0680000
1709#define SD1_RECV_FIFO 0xB0680004
1710
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1711#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1712/* Au1500 PCI Controller */
1713#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
1714#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1715#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1716 #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
1717#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1718#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1719#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1720#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1721#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1722#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1723#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1724#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1725#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1726#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1727#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1728#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1729
1730#define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr
1731
1732/* All of our structures, like pci resource, have 32 bit members.
1733 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1734 * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch
1735 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1736 * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
1737 * addresses. For PCI IO, it's simpler because we get to do the ioremap
1738 * ourselves and then adjust the device's resources.
1739 */
1740#define Au1500_EXT_CFG 0x600000000ULL
1741#define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1742#define Au1500_PCI_IO_START 0x500000000ULL
1743#define Au1500_PCI_IO_END 0x5000FFFFFULL
1744#define Au1500_PCI_MEM_START 0x440000000ULL
1745#define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1746
1747#define PCI_IO_START (Au1500_PCI_IO_START + 0x1000)
1748#define PCI_IO_END (Au1500_PCI_IO_END)
1749#define PCI_MEM_START (Au1500_PCI_MEM_START)
1750#define PCI_MEM_END (Au1500_PCI_MEM_END)
1751#define PCI_FIRST_DEVFN (0<<3)
1752#define PCI_LAST_DEVFN (19<<3)
1753
1754#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1755#define IOPORT_RESOURCE_END 0xffffffff
1756#define IOMEM_RESOURCE_START 0x10000000
1757#define IOMEM_RESOURCE_END 0xffffffff
1758
1759 /*
1760 * Borrowed from the PPC arch:
1761 * The following macro is used to lookup irqs in a standard table
1762 * format for those PPC systems that do not already have PCI
1763 * interrupts properly routed.
1764 */
1765 /* FIXME - double check this from asm-ppc/pci-bridge.h */
1766#define PCI_IRQ_TABLE_LOOKUP \
1767 ({ long _ctl_ = -1; \
1768 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
1769 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
1770 _ctl_; })
1771
1772
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]1773#else /* Au1000 and Au1100 and Au1200 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1774
1775/* don't allow any legacy ports probing */
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]1776#define IOPORT_RESOURCE_START 0x10000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1777#define IOPORT_RESOURCE_END 0xffffffff
1778#define IOMEM_RESOURCE_START 0x10000000
1779#define IOMEM_RESOURCE_END 0xffffffff
1780
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1781#define PCI_IO_START 0
1782#define PCI_IO_END 0
1783#define PCI_MEM_START 0
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700[diff] [blame]1784#define PCI_MEM_END 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1785#define PCI_FIRST_DEVFN 0
1786#define PCI_LAST_DEVFN 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1787
1788#endif
1789
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]1790#ifndef _LANGUAGE_ASSEMBLY
1791typedef volatile struct
1792{
1793 /* 0x0000 */ u32 toytrim;
1794 /* 0x0004 */ u32 toywrite;
1795 /* 0x0008 */ u32 toymatch0;
1796 /* 0x000C */ u32 toymatch1;
1797 /* 0x0010 */ u32 toymatch2;
1798 /* 0x0014 */ u32 cntrctrl;
1799 /* 0x0018 */ u32 scratch0;
1800 /* 0x001C */ u32 scratch1;
1801 /* 0x0020 */ u32 freqctrl0;
1802 /* 0x0024 */ u32 freqctrl1;
1803 /* 0x0028 */ u32 clksrc;
1804 /* 0x002C */ u32 pinfunc;
1805 /* 0x0030 */ u32 reserved0;
1806 /* 0x0034 */ u32 wakemsk;
1807 /* 0x0038 */ u32 endian;
1808 /* 0x003C */ u32 powerctrl;
1809 /* 0x0040 */ u32 toyread;
1810 /* 0x0044 */ u32 rtctrim;
1811 /* 0x0048 */ u32 rtcwrite;
1812 /* 0x004C */ u32 rtcmatch0;
1813 /* 0x0050 */ u32 rtcmatch1;
1814 /* 0x0054 */ u32 rtcmatch2;
1815 /* 0x0058 */ u32 rtcread;
1816 /* 0x005C */ u32 wakesrc;
1817 /* 0x0060 */ u32 cpupll;
1818 /* 0x0064 */ u32 auxpll;
1819 /* 0x0068 */ u32 reserved1;
1820 /* 0x006C */ u32 reserved2;
1821 /* 0x0070 */ u32 reserved3;
1822 /* 0x0074 */ u32 reserved4;
1823 /* 0x0078 */ u32 slppwr;
1824 /* 0x007C */ u32 sleep;
1825 /* 0x0080 */ u32 reserved5[32];
1826 /* 0x0100 */ u32 trioutrd;
1827#define trioutclr trioutrd
1828 /* 0x0104 */ u32 reserved6;
1829 /* 0x0108 */ u32 outputrd;
1830#define outputset outputrd
1831 /* 0x010C */ u32 outputclr;
1832 /* 0x0110 */ u32 pinstaterd;
1833#define pininputen pinstaterd
1834
1835} AU1X00_SYS;
1836
1837static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE;
1838
1839#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1840/* Processor information base on prid.
1841 * Copied from PowerPC.
1842 */
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]1843#ifndef _LANGUAGE_ASSEMBLY
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1844struct cpu_spec {
1845 /* CPU is matched via (PRID & prid_mask) == prid_value */
1846 unsigned int prid_mask;
1847 unsigned int prid_value;
1848
1849 char *cpu_name;
1850 unsigned char cpu_od; /* Set Config[OD] */
1851 unsigned char cpu_bclk; /* Enable BCLK switching */
1852};
1853
1854extern struct cpu_spec cpu_specs[];
1855extern struct cpu_spec *cur_cpu_spec[];
1856#endif
Pete Popove3ad1c22005-03-01 06:33:16 +0000[diff] [blame]1857
1858#endif
1859