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Ilya Yanok148854c2009-03-11 03:22:00 +03001/*
2 * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
Ilya Yanok148854c2009-03-11 03:22:00 +030013 */
14
15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/memory.h>
19#include <linux/platform_device.h>
20#include <linux/mtd/physmap.h>
21#include <linux/mtd/nand.h>
22#include <linux/gpio.h>
23
24#include <mach/hardware.h>
25#include <mach/irqs.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/time.h>
29#include <asm/mach/map.h>
30#include <mach/common.h>
31#include <asm/page.h>
32#include <asm/setup.h>
Ilya Yanok148854c2009-03-11 03:22:00 +030033#include <mach/iomux-mx3.h>
Uwe Kleine-König16cf5c42010-06-23 11:46:16 +020034
35#include "devices-imx31.h"
Ilya Yanok148854c2009-03-11 03:22:00 +030036#include "devices.h"
37
38/* FPGA defines */
39#define QONG_FPGA_VERSION(major, minor, rev) \
40 (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
41
Uwe Kleine-Königf568dd72009-12-09 11:57:21 +010042#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
Ilya Yanok148854c2009-03-11 03:22:00 +030043#define QONG_FPGA_PERIPH_SIZE (1 << 24)
44
45#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
46#define QONG_FPGA_CTRL_SIZE 0x10
47/* FPGA control registers */
48#define QONG_FPGA_CTRL_VERSION 0x00
49
50#define QONG_DNET_ID 1
51#define QONG_DNET_BASEADDR \
52 (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
53#define QONG_DNET_SIZE 0x00001000
54
55#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
56
Uwe Kleine-König16cf5c42010-06-23 11:46:16 +020057static const struct imxuart_platform_data uart_pdata __initconst = {
Ilya Yanok148854c2009-03-11 03:22:00 +030058 .flags = IMXUART_HAVE_RTSCTS,
59};
60
61static int uart_pins[] = {
62 MX31_PIN_CTS1__CTS1,
63 MX31_PIN_RTS1__RTS1,
64 MX31_PIN_TXD1__TXD1,
65 MX31_PIN_RXD1__RXD1
66};
67
Uwe Kleine-König16cf5c42010-06-23 11:46:16 +020068static inline void __init mxc_init_imx_uart(void)
Ilya Yanok148854c2009-03-11 03:22:00 +030069{
70 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
71 "uart-0");
Uwe Kleine-König16cf5c42010-06-23 11:46:16 +020072 imx31_add_imx_uart0(&uart_pdata);
Ilya Yanok148854c2009-03-11 03:22:00 +030073}
74
75static struct resource dnet_resources[] = {
Sascha Hauer3f4f54b2009-06-23 12:12:00 +020076 {
Ilya Yanok148854c2009-03-11 03:22:00 +030077 .name = "dnet-memory",
78 .start = QONG_DNET_BASEADDR,
79 .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
80 .flags = IORESOURCE_MEM,
Sascha Hauer3f4f54b2009-06-23 12:12:00 +020081 }, {
Ilya Yanok148854c2009-03-11 03:22:00 +030082 .start = QONG_FPGA_IRQ,
83 .end = QONG_FPGA_IRQ,
84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88static struct platform_device dnet_device = {
89 .name = "dnet",
90 .id = -1,
91 .num_resources = ARRAY_SIZE(dnet_resources),
92 .resource = dnet_resources,
93};
94
95static int __init qong_init_dnet(void)
96{
97 int ret;
98
99 ret = platform_device_register(&dnet_device);
100 return ret;
101}
102
103/* MTD NOR flash */
104
105static struct physmap_flash_data qong_flash_data = {
106 .width = 2,
107};
108
109static struct resource qong_flash_resource = {
Uwe Kleine-Königf568dd72009-12-09 11:57:21 +0100110 .start = MX31_CS0_BASE_ADDR,
Uwe Kleine-Königd57351a2010-03-08 16:11:51 +0100111 .end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
Ilya Yanok148854c2009-03-11 03:22:00 +0300112 .flags = IORESOURCE_MEM,
113};
114
115static struct platform_device qong_nor_mtd_device = {
116 .name = "physmap-flash",
117 .id = 0,
118 .dev = {
119 .platform_data = &qong_flash_data,
120 },
121 .resource = &qong_flash_resource,
122 .num_resources = 1,
123};
124
125static void qong_init_nor_mtd(void)
126{
127 (void)platform_device_register(&qong_nor_mtd_device);
128}
129
130/*
131 * Hardware specific access to control-lines
132 */
133static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
134{
135 struct nand_chip *nand_chip = mtd->priv;
136
137 if (cmd == NAND_CMD_NONE)
138 return;
139
140 if (ctrl & NAND_CLE)
141 writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
142 else
143 writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
144}
145
146/*
147 * Read the Device Ready pin.
148 */
149static int qong_nand_device_ready(struct mtd_info *mtd)
150{
151 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
152}
153
154static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
155{
156 if (chip >= 0)
157 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
158 else
159 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
160}
161
162static struct platform_nand_data qong_nand_data = {
163 .chip = {
Marek Vasutef077172010-08-12 02:14:54 +0100164 .nr_chips = 1,
Ilya Yanok148854c2009-03-11 03:22:00 +0300165 .chip_delay = 20,
166 .options = 0,
167 },
168 .ctrl = {
169 .cmd_ctrl = qong_nand_cmd_ctrl,
170 .dev_ready = qong_nand_device_ready,
171 .select_chip = qong_nand_select_chip,
172 }
173};
174
175static struct resource qong_nand_resource = {
Uwe Kleine-Königf568dd72009-12-09 11:57:21 +0100176 .start = MX31_CS3_BASE_ADDR,
177 .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
Ilya Yanok148854c2009-03-11 03:22:00 +0300178 .flags = IORESOURCE_MEM,
179};
180
181static struct platform_device qong_nand_device = {
182 .name = "gen_nand",
183 .id = -1,
184 .dev = {
185 .platform_data = &qong_nand_data,
186 },
187 .num_resources = 1,
188 .resource = &qong_nand_resource,
189};
190
191static void __init qong_init_nand_mtd(void)
192{
193 /* init CS */
Uwe Kleine-Königa8dfb642010-01-07 11:27:17 +0100194 mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800);
Ilya Yanok148854c2009-03-11 03:22:00 +0300195 mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
196
197 /* enable pin */
198 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
199 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
200 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
201
202 /* ready/busy pin */
203 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
204 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
205 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
206
207 /* write protect pin */
208 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
209 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
210 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
211
212 platform_device_register(&qong_nand_device);
213}
214
215static void __init qong_init_fpga(void)
216{
217 void __iomem *regs;
218 u32 fpga_ver;
219
220 regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
221 if (!regs) {
222 printk(KERN_ERR "%s: failed to map registers, aborting.\n",
223 __func__);
224 return;
225 }
226
227 fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
228 iounmap(regs);
229 printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
230 (fpga_ver & 0xF000) >> 12,
231 (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
232 if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
233 printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
234 "devices won't be registered!\n");
235 return;
236 }
237
238 /* register FPGA-based devices */
239 qong_init_nand_mtd();
240 qong_init_dnet();
241}
242
243/*
Ilya Yanok148854c2009-03-11 03:22:00 +0300244 * Board specific initialization.
245 */
Uwe Kleine-Könige134fb22011-02-11 10:23:19 +0100246static void __init qong_init(void)
Ilya Yanok148854c2009-03-11 03:22:00 +0300247{
248 mxc_init_imx_uart();
249 qong_init_nor_mtd();
250 qong_init_fpga();
251}
252
253static void __init qong_timer_init(void)
254{
255 mx31_clocks_init(26000000);
256}
257
258static struct sys_timer qong_timer = {
259 .init = qong_timer_init,
260};
261
Ilya Yanok148854c2009-03-11 03:22:00 +0300262MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
263 /* Maintainer: DENX Software Engineering GmbH */
Uwe Kleine-König97976e22011-02-07 16:35:20 +0100264 .boot_params = MX3x_PHYS_OFFSET + 0x100,
265 .map_io = mx31_map_io,
266 .init_early = imx31_init_early,
267 .init_irq = mx31_init_irq,
268 .timer = &qong_timer,
Uwe Kleine-Könige134fb22011-02-11 10:23:19 +0100269 .init_machine = qong_init,
Ilya Yanok148854c2009-03-11 03:22:00 +0300270MACHINE_END