blob: 69d46162d0f5ba385da868a0ce9240e2b34b06ee [file] [log] [blame]
Liu Gang1418f9e2016-03-23 17:47:19 +08001* Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller
Uwe Kleine-Königbb379ce2015-07-16 21:08:24 +02002
3Required properties:
4- compatible : Should be "fsl,<soc>-gpio"
5 The following <soc>s are known to be supported:
Liu Gang1418f9e2016-03-23 17:47:19 +08006 mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq,
7 ls1021a, ls1043a, ls2080a.
Uwe Kleine-Königbb379ce2015-07-16 21:08:24 +02008- reg : Address and length of the register set for the device
9- interrupts : Should be the port interrupt shared by all 32 pins.
10- #gpio-cells : Should be two. The first cell is the pin number and
11 the second cell is used to specify the gpio polarity:
12 0 = active high
13 1 = active low
14
Li Yangedb70e22015-12-04 16:55:04 -060015Optional properties:
16- little-endian : GPIO registers are used as little endian. If not
17 present registers are used as big endian by default.
18
Liu Gang1418f9e2016-03-23 17:47:19 +080019Example of gpio-controller node for a mpc5125 SoC:
Uwe Kleine-Königbb379ce2015-07-16 21:08:24 +020020
21gpio0: gpio@1100 {
22 compatible = "fsl,mpc5125-gpio";
23 #gpio-cells = <2>;
24 reg = <0x1100 0x080>;
25 interrupts = <78 0x8>;
Uwe Kleine-Königbb379ce2015-07-16 21:08:24 +020026};
Liu Gang1418f9e2016-03-23 17:47:19 +080027
28Example of gpio-controller node for a ls2080a SoC:
29
30gpio0: gpio@2300000 {
31 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
32 reg = <0x0 0x2300000 0x0 0x10000>;
33 interrupts = <0 36 0x4>; /* Level high type */
34 gpio-controller;
35 little-endian;
36 #gpio-cells = <2>;
37 interrupt-controller;
38 #interrupt-cells = <2>;
39};