Ben Dooks | 4b31d8b | 2008-10-21 14:07:00 +0100 | [diff] [blame] | 1 | /* linux/arch/arm/plat-s3c64xx/clock.c |
| 2 | * |
| 3 | * Copyright 2008 Openmoko, Inc. |
| 4 | * Copyright 2008 Simtec Electronics |
| 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * http://armlinux.simtec.co.uk/ |
| 7 | * |
| 8 | * S3C64XX Base clock support |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/ioport.h> |
Ben Dooks | 4b31d8b | 2008-10-21 14:07:00 +0100 | [diff] [blame] | 19 | #include <linux/io.h> |
| 20 | |
| 21 | #include <mach/hardware.h> |
| 22 | #include <mach/map.h> |
| 23 | |
Ben Dooks | 3501c9a | 2010-01-26 10:45:40 +0900 | [diff] [blame^] | 24 | #include <mach/regs-sys.h> |
| 25 | #include <mach/regs-clock.h> |
Ben Dooks | 4b31d8b | 2008-10-21 14:07:00 +0100 | [diff] [blame] | 26 | #include <plat/cpu.h> |
| 27 | #include <plat/devs.h> |
| 28 | #include <plat/clock.h> |
| 29 | |
Werner Almesberger | a03f7da | 2009-03-05 11:43:13 +0800 | [diff] [blame] | 30 | struct clk clk_h2 = { |
| 31 | .name = "hclk2", |
| 32 | .id = -1, |
| 33 | .rate = 0, |
| 34 | }; |
| 35 | |
Ben Dooks | 4b31d8b | 2008-10-21 14:07:00 +0100 | [diff] [blame] | 36 | struct clk clk_27m = { |
| 37 | .name = "clk_27m", |
| 38 | .id = -1, |
| 39 | .rate = 27000000, |
| 40 | }; |
| 41 | |
Ben Dooks | 3627379f | 2008-10-31 16:14:36 +0000 | [diff] [blame] | 42 | static int clk_48m_ctrl(struct clk *clk, int enable) |
| 43 | { |
| 44 | unsigned long flags; |
| 45 | u32 val; |
| 46 | |
| 47 | /* can't rely on clock lock, this register has other usages */ |
| 48 | local_irq_save(flags); |
| 49 | |
| 50 | val = __raw_readl(S3C64XX_OTHERS); |
| 51 | if (enable) |
| 52 | val |= S3C64XX_OTHERS_USBMASK; |
| 53 | else |
| 54 | val &= ~S3C64XX_OTHERS_USBMASK; |
| 55 | |
| 56 | __raw_writel(val, S3C64XX_OTHERS); |
| 57 | local_irq_restore(flags); |
| 58 | |
| 59 | return 0; |
| 60 | } |
| 61 | |
Ben Dooks | 4b31d8b | 2008-10-21 14:07:00 +0100 | [diff] [blame] | 62 | struct clk clk_48m = { |
| 63 | .name = "clk_48m", |
| 64 | .id = -1, |
| 65 | .rate = 48000000, |
Ben Dooks | 3627379f | 2008-10-31 16:14:36 +0000 | [diff] [blame] | 66 | .enable = clk_48m_ctrl, |
Ben Dooks | 4b31d8b | 2008-10-21 14:07:00 +0100 | [diff] [blame] | 67 | }; |
| 68 | |
| 69 | static int inline s3c64xx_gate(void __iomem *reg, |
| 70 | struct clk *clk, |
| 71 | int enable) |
| 72 | { |
| 73 | unsigned int ctrlbit = clk->ctrlbit; |
| 74 | u32 con; |
| 75 | |
| 76 | con = __raw_readl(reg); |
| 77 | |
| 78 | if (enable) |
| 79 | con |= ctrlbit; |
| 80 | else |
| 81 | con &= ~ctrlbit; |
| 82 | |
| 83 | __raw_writel(con, reg); |
| 84 | return 0; |
| 85 | } |
| 86 | |
| 87 | static int s3c64xx_pclk_ctrl(struct clk *clk, int enable) |
| 88 | { |
| 89 | return s3c64xx_gate(S3C_PCLK_GATE, clk, enable); |
| 90 | } |
| 91 | |
| 92 | static int s3c64xx_hclk_ctrl(struct clk *clk, int enable) |
| 93 | { |
| 94 | return s3c64xx_gate(S3C_HCLK_GATE, clk, enable); |
| 95 | } |
| 96 | |
Ben Dooks | cf18acf | 2008-10-21 14:07:02 +0100 | [diff] [blame] | 97 | int s3c64xx_sclk_ctrl(struct clk *clk, int enable) |
Ben Dooks | 4b31d8b | 2008-10-21 14:07:00 +0100 | [diff] [blame] | 98 | { |
| 99 | return s3c64xx_gate(S3C_SCLK_GATE, clk, enable); |
| 100 | } |
| 101 | |
| 102 | static struct clk init_clocks_disable[] = { |
| 103 | { |
| 104 | .name = "nand", |
| 105 | .id = -1, |
| 106 | .parent = &clk_h, |
| 107 | }, { |
| 108 | .name = "adc", |
| 109 | .id = -1, |
| 110 | .parent = &clk_p, |
| 111 | .enable = s3c64xx_pclk_ctrl, |
| 112 | .ctrlbit = S3C_CLKCON_PCLK_TSADC, |
| 113 | }, { |
| 114 | .name = "i2c", |
| 115 | .id = -1, |
| 116 | .parent = &clk_p, |
| 117 | .enable = s3c64xx_pclk_ctrl, |
| 118 | .ctrlbit = S3C_CLKCON_PCLK_IIC, |
| 119 | }, { |
| 120 | .name = "iis", |
| 121 | .id = 0, |
| 122 | .parent = &clk_p, |
| 123 | .enable = s3c64xx_pclk_ctrl, |
| 124 | .ctrlbit = S3C_CLKCON_PCLK_IIS0, |
| 125 | }, { |
| 126 | .name = "iis", |
| 127 | .id = 1, |
| 128 | .parent = &clk_p, |
| 129 | .enable = s3c64xx_pclk_ctrl, |
| 130 | .ctrlbit = S3C_CLKCON_PCLK_IIS1, |
| 131 | }, { |
| 132 | .name = "spi", |
| 133 | .id = 0, |
| 134 | .parent = &clk_p, |
| 135 | .enable = s3c64xx_pclk_ctrl, |
| 136 | .ctrlbit = S3C_CLKCON_PCLK_SPI0, |
| 137 | }, { |
| 138 | .name = "spi", |
| 139 | .id = 1, |
| 140 | .parent = &clk_p, |
| 141 | .enable = s3c64xx_pclk_ctrl, |
| 142 | .ctrlbit = S3C_CLKCON_PCLK_SPI1, |
| 143 | }, { |
Jassi Brar | 87315a8 | 2010-01-18 16:15:08 +0900 | [diff] [blame] | 144 | .name = "spi_48m", |
| 145 | .id = 0, |
| 146 | .parent = &clk_48m, |
| 147 | .enable = s3c64xx_sclk_ctrl, |
| 148 | .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, |
| 149 | }, { |
| 150 | .name = "spi_48m", |
| 151 | .id = 1, |
| 152 | .parent = &clk_48m, |
| 153 | .enable = s3c64xx_sclk_ctrl, |
| 154 | .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, |
| 155 | }, { |
Ben Dooks | 4b31d8b | 2008-10-21 14:07:00 +0100 | [diff] [blame] | 156 | .name = "48m", |
| 157 | .id = 0, |
| 158 | .parent = &clk_48m, |
| 159 | .enable = s3c64xx_sclk_ctrl, |
| 160 | .ctrlbit = S3C_CLKCON_SCLK_MMC0_48, |
| 161 | }, { |
| 162 | .name = "48m", |
| 163 | .id = 1, |
| 164 | .parent = &clk_48m, |
| 165 | .enable = s3c64xx_sclk_ctrl, |
| 166 | .ctrlbit = S3C_CLKCON_SCLK_MMC1_48, |
| 167 | }, { |
| 168 | .name = "48m", |
| 169 | .id = 2, |
| 170 | .parent = &clk_48m, |
| 171 | .enable = s3c64xx_sclk_ctrl, |
| 172 | .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, |
Mark Brown | 8f1ecf1 | 2009-04-28 16:06:24 +0100 | [diff] [blame] | 173 | }, { |
| 174 | .name = "dma0", |
| 175 | .id = -1, |
| 176 | .parent = &clk_h, |
| 177 | .enable = s3c64xx_hclk_ctrl, |
| 178 | .ctrlbit = S3C_CLKCON_HCLK_DMA0, |
| 179 | }, { |
| 180 | .name = "dma1", |
| 181 | .id = -1, |
| 182 | .parent = &clk_h, |
| 183 | .enable = s3c64xx_hclk_ctrl, |
| 184 | .ctrlbit = S3C_CLKCON_HCLK_DMA1, |
Ben Dooks | 4b31d8b | 2008-10-21 14:07:00 +0100 | [diff] [blame] | 185 | }, |
| 186 | }; |
| 187 | |
| 188 | static struct clk init_clocks[] = { |
| 189 | { |
| 190 | .name = "lcd", |
| 191 | .id = -1, |
| 192 | .parent = &clk_h, |
| 193 | .enable = s3c64xx_hclk_ctrl, |
| 194 | .ctrlbit = S3C_CLKCON_HCLK_LCD, |
| 195 | }, { |
| 196 | .name = "gpio", |
| 197 | .id = -1, |
| 198 | .parent = &clk_p, |
| 199 | .enable = s3c64xx_pclk_ctrl, |
| 200 | .ctrlbit = S3C_CLKCON_PCLK_GPIO, |
| 201 | }, { |
| 202 | .name = "usb-host", |
| 203 | .id = -1, |
| 204 | .parent = &clk_h, |
| 205 | .enable = s3c64xx_hclk_ctrl, |
Peter Korsgaard | 386f435 | 2009-06-18 23:54:44 +0200 | [diff] [blame] | 206 | .ctrlbit = S3C_CLKCON_HCLK_UHOST, |
Ben Dooks | 4b31d8b | 2008-10-21 14:07:00 +0100 | [diff] [blame] | 207 | }, { |
| 208 | .name = "hsmmc", |
| 209 | .id = 0, |
| 210 | .parent = &clk_h, |
| 211 | .enable = s3c64xx_hclk_ctrl, |
| 212 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, |
| 213 | }, { |
| 214 | .name = "hsmmc", |
| 215 | .id = 1, |
| 216 | .parent = &clk_h, |
| 217 | .enable = s3c64xx_hclk_ctrl, |
| 218 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, |
| 219 | }, { |
| 220 | .name = "hsmmc", |
| 221 | .id = 2, |
| 222 | .parent = &clk_h, |
| 223 | .enable = s3c64xx_hclk_ctrl, |
| 224 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, |
| 225 | }, { |
| 226 | .name = "timers", |
| 227 | .id = -1, |
| 228 | .parent = &clk_p, |
| 229 | .enable = s3c64xx_pclk_ctrl, |
| 230 | .ctrlbit = S3C_CLKCON_PCLK_PWM, |
| 231 | }, { |
| 232 | .name = "uart", |
| 233 | .id = 0, |
| 234 | .parent = &clk_p, |
| 235 | .enable = s3c64xx_pclk_ctrl, |
| 236 | .ctrlbit = S3C_CLKCON_PCLK_UART0, |
| 237 | }, { |
| 238 | .name = "uart", |
| 239 | .id = 1, |
| 240 | .parent = &clk_p, |
| 241 | .enable = s3c64xx_pclk_ctrl, |
| 242 | .ctrlbit = S3C_CLKCON_PCLK_UART1, |
| 243 | }, { |
| 244 | .name = "uart", |
| 245 | .id = 2, |
| 246 | .parent = &clk_p, |
| 247 | .enable = s3c64xx_pclk_ctrl, |
| 248 | .ctrlbit = S3C_CLKCON_PCLK_UART2, |
| 249 | }, { |
| 250 | .name = "uart", |
| 251 | .id = 3, |
| 252 | .parent = &clk_p, |
| 253 | .enable = s3c64xx_pclk_ctrl, |
| 254 | .ctrlbit = S3C_CLKCON_PCLK_UART3, |
| 255 | }, { |
| 256 | .name = "rtc", |
| 257 | .id = -1, |
| 258 | .parent = &clk_p, |
| 259 | .enable = s3c64xx_pclk_ctrl, |
| 260 | .ctrlbit = S3C_CLKCON_PCLK_RTC, |
| 261 | }, { |
| 262 | .name = "watchdog", |
| 263 | .id = -1, |
| 264 | .parent = &clk_p, |
| 265 | .ctrlbit = S3C_CLKCON_PCLK_WDT, |
| 266 | }, { |
| 267 | .name = "ac97", |
| 268 | .id = -1, |
| 269 | .parent = &clk_p, |
| 270 | .ctrlbit = S3C_CLKCON_PCLK_AC97, |
| 271 | } |
| 272 | }; |
| 273 | |
| 274 | static struct clk *clks[] __initdata = { |
| 275 | &clk_ext, |
| 276 | &clk_epll, |
| 277 | &clk_27m, |
| 278 | &clk_48m, |
Werner Almesberger | a03f7da | 2009-03-05 11:43:13 +0800 | [diff] [blame] | 279 | &clk_h2, |
Ben Dooks | 4b31d8b | 2008-10-21 14:07:00 +0100 | [diff] [blame] | 280 | }; |
| 281 | |
Mark Brown | 789b4ad | 2009-01-26 19:12:01 +0000 | [diff] [blame] | 282 | void __init s3c64xx_register_clocks(void) |
Ben Dooks | 4b31d8b | 2008-10-21 14:07:00 +0100 | [diff] [blame] | 283 | { |
| 284 | struct clk *clkp; |
| 285 | int ret; |
| 286 | int ptr; |
| 287 | |
| 288 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); |
Ben Dooks | 1d9f13c | 2010-01-06 01:21:38 +0900 | [diff] [blame] | 289 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); |
Ben Dooks | 4b31d8b | 2008-10-21 14:07:00 +0100 | [diff] [blame] | 290 | |
| 291 | clkp = init_clocks_disable; |
| 292 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { |
| 293 | |
| 294 | ret = s3c24xx_register_clock(clkp); |
| 295 | if (ret < 0) { |
| 296 | printk(KERN_ERR "Failed to register clock %s (%d)\n", |
| 297 | clkp->name, ret); |
| 298 | } |
| 299 | |
| 300 | (clkp->enable)(clkp, 0); |
| 301 | } |
Ben Dooks | 9d325f2 | 2008-11-21 10:36:05 +0000 | [diff] [blame] | 302 | |
| 303 | s3c_pwmclk_init(); |
Ben Dooks | 4b31d8b | 2008-10-21 14:07:00 +0100 | [diff] [blame] | 304 | } |