blob: da6609d628487b161a531d37145e681c13500965 [file] [log] [blame]
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301/*
Linus Walleij1804edd2010-09-23 09:03:40 +02002 * Copyright (C) 2009 ST-Ericsson SA
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05303 * Copyright (C) 2009 STMicroelectronics
4 *
5 * I2C master mode controller driver, used in Nomadik 8815
6 * and Ux500 platforms.
7 *
8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
9 * Author: Sachin Verma <sachin.verma@st.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2, as
13 * published by the Free Software Foundation.
14 */
15#include <linux/init.h>
16#include <linux/module.h>
Alessandro Rubini23560212012-06-11 22:56:38 +020017#include <linux/amba/bus.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090018#include <linux/slab.h>
srinidhi kasagar3f9900f2010-02-01 19:44:54 +053019#include <linux/interrupt.h>
20#include <linux/i2c.h>
21#include <linux/err.h>
22#include <linux/clk.h>
23#include <linux/io.h>
Rabin Vincentb0e751a2011-05-13 12:30:07 +020024#include <linux/pm_runtime.h>
Lee Jones43fea582012-08-06 11:09:57 +010025#include <linux/of.h>
Patrice Chotard24e9e152013-01-24 09:47:22 +010026#include <linux/pinctrl/consumer.h>
srinidhi kasagar3f9900f2010-02-01 19:44:54 +053027
28#define DRIVER_NAME "nmk-i2c"
29
30/* I2C Controller register offsets */
31#define I2C_CR (0x000)
32#define I2C_SCR (0x004)
33#define I2C_HSMCR (0x008)
34#define I2C_MCR (0x00C)
35#define I2C_TFR (0x010)
36#define I2C_SR (0x014)
37#define I2C_RFR (0x018)
38#define I2C_TFTR (0x01C)
39#define I2C_RFTR (0x020)
40#define I2C_DMAR (0x024)
41#define I2C_BRCR (0x028)
42#define I2C_IMSCR (0x02C)
43#define I2C_RISR (0x030)
44#define I2C_MISR (0x034)
45#define I2C_ICR (0x038)
46
47/* Control registers */
48#define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
49#define I2C_CR_OM (0x3 << 1) /* Operating mode */
50#define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
51#define I2C_CR_SM (0x3 << 4) /* Speed mode */
52#define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
53#define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
54#define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
55#define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
56#define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
57#define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
58#define I2C_CR_LM (0x1 << 12) /* Loopback mode */
59#define I2C_CR_FON (0x3 << 13) /* Filtering on */
60#define I2C_CR_FS (0x3 << 15) /* Force stop enable */
61
62/* Master controller (MCR) register */
63#define I2C_MCR_OP (0x1 << 0) /* Operation */
64#define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +020065#define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
srinidhi kasagar3f9900f2010-02-01 19:44:54 +053066#define I2C_MCR_SB (0x1 << 11) /* Extended address */
67#define I2C_MCR_AM (0x3 << 12) /* Address type */
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +020068#define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
69#define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
srinidhi kasagar3f9900f2010-02-01 19:44:54 +053070
71/* Status register (SR) */
72#define I2C_SR_OP (0x3 << 0) /* Operation */
73#define I2C_SR_STATUS (0x3 << 2) /* controller status */
74#define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
75#define I2C_SR_TYPE (0x3 << 7) /* Receive type */
76#define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
77
78/* Interrupt mask set/clear (IMSCR) bits */
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +020079#define I2C_IT_TXFE (0x1 << 0)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +053080#define I2C_IT_TXFNE (0x1 << 1)
81#define I2C_IT_TXFF (0x1 << 2)
82#define I2C_IT_TXFOVR (0x1 << 3)
83#define I2C_IT_RXFE (0x1 << 4)
84#define I2C_IT_RXFNF (0x1 << 5)
85#define I2C_IT_RXFF (0x1 << 6)
86#define I2C_IT_RFSR (0x1 << 16)
87#define I2C_IT_RFSE (0x1 << 17)
88#define I2C_IT_WTSR (0x1 << 18)
89#define I2C_IT_MTD (0x1 << 19)
90#define I2C_IT_STD (0x1 << 20)
91#define I2C_IT_MAL (0x1 << 24)
92#define I2C_IT_BERR (0x1 << 25)
93#define I2C_IT_MTDWS (0x1 << 28)
94
95#define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
96
97/* some bits in ICR are reserved */
98#define I2C_CLEAR_ALL_INTS 0x131f007f
99
100/* first three msb bits are reserved */
101#define IRQ_MASK(mask) (mask & 0x1fffffff)
102
103/* maximum threshold value */
104#define MAX_I2C_FIFO_THRESHOLD 15
105
Linus Walleij5915dbf2013-11-28 23:12:07 +0100106enum i2c_freq_mode {
107 I2C_FREQ_MODE_STANDARD, /* up to 100 Kb/s */
108 I2C_FREQ_MODE_FAST, /* up to 400 Kb/s */
109 I2C_FREQ_MODE_HIGH_SPEED, /* up to 3.4 Mb/s */
110 I2C_FREQ_MODE_FAST_PLUS, /* up to 1 Mb/s */
111};
112
113/**
Linus Walleij3a205be2013-06-10 00:00:58 +0200114 * struct i2c_vendor_data - per-vendor variations
115 * @has_mtdws: variant has the MTDWS bit
116 * @fifodepth: variant FIFO depth
117 */
118struct i2c_vendor_data {
119 bool has_mtdws;
120 u32 fifodepth;
121};
122
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530123enum i2c_status {
124 I2C_NOP,
125 I2C_ON_GOING,
126 I2C_OK,
127 I2C_ABORT
128};
129
130/* operation */
131enum i2c_operation {
132 I2C_NO_OPERATION = 0xff,
133 I2C_WRITE = 0x00,
134 I2C_READ = 0x01
135};
136
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530137/**
138 * struct i2c_nmk_client - client specific data
139 * @slave_adr: 7-bit slave address
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300140 * @count: no. bytes to be transferred
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530141 * @buffer: client data buffer
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300142 * @xfer_bytes: bytes transferred till now
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530143 * @operation: current I2C operation
144 */
145struct i2c_nmk_client {
146 unsigned short slave_adr;
147 unsigned long count;
148 unsigned char *buffer;
149 unsigned long xfer_bytes;
150 enum i2c_operation operation;
151};
152
153/**
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200154 * struct nmk_i2c_dev - private data structure of the controller.
Linus Walleij3a205be2013-06-10 00:00:58 +0200155 * @vendor: vendor data for this variant.
Alessandro Rubini23560212012-06-11 22:56:38 +0200156 * @adev: parent amba device.
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200157 * @adap: corresponding I2C adapter.
158 * @irq: interrupt line for the controller.
159 * @virtbase: virtual io memory area.
160 * @clk: hardware i2c block clock.
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200161 * @cli: holder of client specific data.
Linus Walleijc33a0042014-02-03 11:27:26 +0100162 * @clk_freq: clock frequency for the operation mode
163 * @tft: Tx FIFO Threshold in bytes
164 * @rft: Rx FIFO Threshold in bytes
165 * @timeout Slave response timeout (ms)
166 * @sm: speed mode
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200167 * @stop: stop condition.
168 * @xfer_complete: acknowledge completion for a I2C message.
169 * @result: controller propogated result.
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530170 */
171struct nmk_i2c_dev {
Linus Walleij3a205be2013-06-10 00:00:58 +0200172 struct i2c_vendor_data *vendor;
Alessandro Rubini23560212012-06-11 22:56:38 +0200173 struct amba_device *adev;
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200174 struct i2c_adapter adap;
175 int irq;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530176 void __iomem *virtbase;
177 struct clk *clk;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530178 struct i2c_nmk_client cli;
Linus Walleijc33a0042014-02-03 11:27:26 +0100179 u32 clk_freq;
180 unsigned char tft;
181 unsigned char rft;
182 int timeout;
183 enum i2c_freq_mode sm;
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200184 int stop;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530185 struct completion xfer_complete;
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200186 int result;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530187};
188
189/* controller's abort causes */
190static const char *abort_causes[] = {
191 "no ack received after address transmission",
192 "no ack received during data phase",
193 "ack received after xmission of master code",
194 "master lost arbitration",
195 "slave restarts",
196 "slave reset",
197 "overflow, maxsize is 2047 bytes",
198};
199
200static inline void i2c_set_bit(void __iomem *reg, u32 mask)
201{
202 writel(readl(reg) | mask, reg);
203}
204
205static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
206{
207 writel(readl(reg) & ~mask, reg);
208}
209
210/**
211 * flush_i2c_fifo() - This function flushes the I2C FIFO
212 * @dev: private data of I2C Driver
213 *
214 * This function flushes the I2C Tx and Rx FIFOs. It returns
215 * 0 on successful flushing of FIFO
216 */
217static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
218{
219#define LOOP_ATTEMPTS 10
220 int i;
221 unsigned long timeout;
222
223 /*
224 * flush the transmit and receive FIFO. The flushing
225 * operation takes several cycles before to be completed.
226 * On the completion, the I2C internal logic clears these
227 * bits, until then no one must access Tx, Rx FIFO and
228 * should poll on these bits waiting for the completion.
229 */
230 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
231
232 for (i = 0; i < LOOP_ATTEMPTS; i++) {
Virupax Sadashivpetimathcd20e4fa2011-05-13 12:29:46 +0200233 timeout = jiffies + dev->adap.timeout;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530234
235 while (!time_after(jiffies, timeout)) {
236 if ((readl(dev->virtbase + I2C_CR) &
237 (I2C_CR_FTX | I2C_CR_FRX)) == 0)
238 return 0;
239 }
240 }
241
Alessandro Rubini23560212012-06-11 22:56:38 +0200242 dev_err(&dev->adev->dev,
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200243 "flushing operation timed out giving up after %d attempts",
244 LOOP_ATTEMPTS);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530245
246 return -ETIMEDOUT;
247}
248
249/**
250 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
251 * @dev: private data of I2C Driver
252 */
253static void disable_all_interrupts(struct nmk_i2c_dev *dev)
254{
255 u32 mask = IRQ_MASK(0);
256 writel(mask, dev->virtbase + I2C_IMSCR);
257}
258
259/**
260 * clear_all_interrupts() - Clear all interrupts of I2C Controller
261 * @dev: private data of I2C Driver
262 */
263static void clear_all_interrupts(struct nmk_i2c_dev *dev)
264{
265 u32 mask;
266 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
267 writel(mask, dev->virtbase + I2C_ICR);
268}
269
270/**
271 * init_hw() - initialize the I2C hardware
272 * @dev: private data of I2C Driver
273 */
274static int init_hw(struct nmk_i2c_dev *dev)
275{
276 int stat;
277
278 stat = flush_i2c_fifo(dev);
279 if (stat)
Jonas Aberga20d2392011-05-13 12:29:02 +0200280 goto exit;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530281
282 /* disable the controller */
283 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
284
285 disable_all_interrupts(dev);
286
287 clear_all_interrupts(dev);
288
289 dev->cli.operation = I2C_NO_OPERATION;
290
Jonas Aberga20d2392011-05-13 12:29:02 +0200291exit:
Jonas Aberga20d2392011-05-13 12:29:02 +0200292 return stat;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530293}
294
295/* enable peripheral, master mode operation */
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200296#define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530297
298/**
299 * load_i2c_mcr_reg() - load the MCR register
300 * @dev: private data of controller
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530301 * @flags: message flags
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530302 */
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530303static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530304{
305 u32 mcr = 0;
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530306 unsigned short slave_adr_3msb_bits;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530307
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530308 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
309
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530310 if (unlikely(flags & I2C_M_TEN)) {
311 /* 10-bit address transaction */
312 mcr |= GEN_MASK(2, I2C_MCR_AM, 12);
313 /*
314 * Get the top 3 bits.
315 * EA10 represents extended address in MCR. This includes
316 * the extension (MSB bits) of the 7 bit address loaded
317 * in A7
318 */
319 slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7;
320
321 mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8);
322 } else {
323 /* 7-bit address transaction */
324 mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
325 }
326
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530327 /* start byte procedure not applied */
328 mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
329
330 /* check the operation, master read/write? */
331 if (dev->cli.operation == I2C_WRITE)
332 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
333 else
334 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
335
336 /* stop or repeated start? */
337 if (dev->stop)
338 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
339 else
340 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
341
342 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
343
344 return mcr;
345}
346
347/**
348 * setup_i2c_controller() - setup the controller
349 * @dev: private data of controller
350 */
351static void setup_i2c_controller(struct nmk_i2c_dev *dev)
352{
353 u32 brcr1, brcr2;
354 u32 i2c_clk, div;
Linus Walleij97730392013-11-28 23:11:45 +0100355 u32 ns;
356 u16 slsu;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530357
358 writel(0x0, dev->virtbase + I2C_CR);
359 writel(0x0, dev->virtbase + I2C_HSMCR);
360 writel(0x0, dev->virtbase + I2C_TFTR);
361 writel(0x0, dev->virtbase + I2C_RFTR);
362 writel(0x0, dev->virtbase + I2C_DMAR);
363
Linus Walleij97730392013-11-28 23:11:45 +0100364 i2c_clk = clk_get_rate(dev->clk);
365
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530366 /*
367 * set the slsu:
368 *
369 * slsu defines the data setup time after SCL clock
Linus Walleij97730392013-11-28 23:11:45 +0100370 * stretching in terms of i2c clk cycles + 1 (zero means
371 * "wait one cycle"), the needed setup time for the three
372 * modes are 250ns, 100ns, 10ns respectively.
373 *
374 * As the time for one cycle T in nanoseconds is
375 * T = (1/f) * 1000000000 =>
376 * slsu = cycles / (1000000000 / f) + 1
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530377 */
Linus Walleij97730392013-11-28 23:11:45 +0100378 ns = DIV_ROUND_UP_ULL(1000000000ULL, i2c_clk);
Linus Walleijc33a0042014-02-03 11:27:26 +0100379 switch (dev->sm) {
Linus Walleij97730392013-11-28 23:11:45 +0100380 case I2C_FREQ_MODE_FAST:
381 case I2C_FREQ_MODE_FAST_PLUS:
382 slsu = DIV_ROUND_UP(100, ns); /* Fast */
383 break;
384 case I2C_FREQ_MODE_HIGH_SPEED:
385 slsu = DIV_ROUND_UP(10, ns); /* High */
386 break;
387 case I2C_FREQ_MODE_STANDARD:
388 default:
389 slsu = DIV_ROUND_UP(250, ns); /* Standard */
390 break;
391 }
392 slsu += 1;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530393
Linus Walleij97730392013-11-28 23:11:45 +0100394 dev_dbg(&dev->adev->dev, "calculated SLSU = %04x\n", slsu);
395 writel(slsu << 16, dev->virtbase + I2C_SCR);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530396
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530397 /*
398 * The spec says, in case of std. mode the divider is
399 * 2 whereas it is 3 for fast and fastplus mode of
400 * operation. TODO - high speed support.
401 */
Linus Walleijc33a0042014-02-03 11:27:26 +0100402 div = (dev->clk_freq > 100000) ? 3 : 2;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530403
404 /*
405 * generate the mask for baud rate counters. The controller
406 * has two baud rate counters. One is used for High speed
407 * operation, and the other is for std, fast mode, fast mode
408 * plus operation. Currently we do not supprt high speed mode
409 * so set brcr1 to 0.
410 */
411 brcr1 = 0 << 16;
Linus Walleijc33a0042014-02-03 11:27:26 +0100412 brcr2 = (i2c_clk/(dev->clk_freq * div)) & 0xffff;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530413
414 /* set the baud rate counter register */
415 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
416
417 /*
418 * set the speed mode. Currently we support
419 * only standard and fast mode of operation
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300420 * TODO - support for fast mode plus (up to 1Mb/s)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530421 * and high speed (up to 3.4 Mb/s)
422 */
Linus Walleijc33a0042014-02-03 11:27:26 +0100423 if (dev->sm > I2C_FREQ_MODE_FAST) {
Alessandro Rubini23560212012-06-11 22:56:38 +0200424 dev_err(&dev->adev->dev,
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200425 "do not support this mode defaulting to std. mode\n");
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530426 brcr2 = i2c_clk/(100000 * 2) & 0xffff;
427 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
428 writel(I2C_FREQ_MODE_STANDARD << 4,
429 dev->virtbase + I2C_CR);
430 }
Linus Walleijc33a0042014-02-03 11:27:26 +0100431 writel(dev->sm << 4, dev->virtbase + I2C_CR);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530432
433 /* set the Tx and Rx FIFO threshold */
Linus Walleijc33a0042014-02-03 11:27:26 +0100434 writel(dev->tft, dev->virtbase + I2C_TFTR);
435 writel(dev->rft, dev->virtbase + I2C_RFTR);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530436}
437
438/**
439 * read_i2c() - Read from I2C client device
440 * @dev: private data of I2C Driver
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530441 * @flags: message flags
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530442 *
443 * This function reads from i2c client device when controller is in
444 * master mode. There is a completion timeout. If there is no transfer
445 * before timeout error is returned.
446 */
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530447static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530448{
Nicholas Mc Guiref87b53a2015-02-08 07:34:43 -0500449 int status = 0;
Wolfram Sang876ae852013-01-24 11:27:46 +0100450 u32 mcr, irq_mask;
Nicholas Mc Guire9bb9fee2015-02-08 07:34:33 -0500451 unsigned long timeout;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530452
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530453 mcr = load_i2c_mcr_reg(dev, flags);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530454 writel(mcr, dev->virtbase + I2C_MCR);
455
456 /* load the current CR value */
457 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
458 dev->virtbase + I2C_CR);
459
460 /* enable the controller */
461 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
462
463 init_completion(&dev->xfer_complete);
464
465 /* enable interrupts by setting the mask */
466 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
467 I2C_IT_MAL | I2C_IT_BERR);
468
Linus Walleij3a205be2013-06-10 00:00:58 +0200469 if (dev->stop || !dev->vendor->has_mtdws)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530470 irq_mask |= I2C_IT_MTD;
471 else
472 irq_mask |= I2C_IT_MTDWS;
473
474 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
475
476 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
477 dev->virtbase + I2C_IMSCR);
478
srinidhi kasagar4b723a42011-08-09 20:17:22 +0200479 timeout = wait_for_completion_timeout(
Virupax Sadashivpetimathcd20e4fa2011-05-13 12:29:46 +0200480 &dev->xfer_complete, dev->adap.timeout);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530481
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530482 if (timeout == 0) {
Virupax Sadashivpetimath0511f642011-05-13 12:30:53 +0200483 /* Controller timed out */
Alessandro Rubini23560212012-06-11 22:56:38 +0200484 dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n",
Virupax Sadashivpetimath4cb3f532011-05-13 12:29:55 +0200485 dev->cli.slave_adr);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530486 status = -ETIMEDOUT;
487 }
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530488 return status;
489}
490
Virupax Sadashivpetimath55355342011-05-13 12:30:34 +0200491static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes)
492{
493 int count;
494
495 for (count = (no_bytes - 2);
496 (count > 0) &&
497 (dev->cli.count != 0);
498 count--) {
499 /* write to the Tx FIFO */
500 writeb(*dev->cli.buffer,
501 dev->virtbase + I2C_TFR);
502 dev->cli.buffer++;
503 dev->cli.count--;
504 dev->cli.xfer_bytes++;
505 }
506
507}
508
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530509/**
510 * write_i2c() - Write data to I2C client.
511 * @dev: private data of I2C Driver
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530512 * @flags: message flags
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530513 *
514 * This function writes data to I2C client
515 */
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530516static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530517{
518 u32 status = 0;
Wolfram Sang876ae852013-01-24 11:27:46 +0100519 u32 mcr, irq_mask;
Nicholas Mc Guire9bb9fee2015-02-08 07:34:33 -0500520 unsigned long timeout;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530521
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530522 mcr = load_i2c_mcr_reg(dev, flags);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530523
524 writel(mcr, dev->virtbase + I2C_MCR);
525
526 /* load the current CR value */
527 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
528 dev->virtbase + I2C_CR);
529
530 /* enable the controller */
531 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
532
533 init_completion(&dev->xfer_complete);
534
535 /* enable interrupts by settings the masks */
Virupax Sadashivpetimath55355342011-05-13 12:30:34 +0200536 irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
537
538 /* Fill the TX FIFO with transmit data */
539 fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD);
540
541 if (dev->cli.count != 0)
542 irq_mask |= I2C_IT_TXFNE;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530543
544 /*
545 * check if we want to transfer a single or multiple bytes, if so
546 * set the MTDWS bit (Master Transaction Done Without Stop)
547 * to start repeated start operation
548 */
Linus Walleij3a205be2013-06-10 00:00:58 +0200549 if (dev->stop || !dev->vendor->has_mtdws)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530550 irq_mask |= I2C_IT_MTD;
551 else
552 irq_mask |= I2C_IT_MTDWS;
553
554 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
555
556 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
557 dev->virtbase + I2C_IMSCR);
558
srinidhi kasagar4b723a42011-08-09 20:17:22 +0200559 timeout = wait_for_completion_timeout(
Virupax Sadashivpetimathcd20e4fa2011-05-13 12:29:46 +0200560 &dev->xfer_complete, dev->adap.timeout);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530561
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530562 if (timeout == 0) {
Virupax Sadashivpetimath0511f642011-05-13 12:30:53 +0200563 /* Controller timed out */
Alessandro Rubini23560212012-06-11 22:56:38 +0200564 dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n",
Virupax Sadashivpetimath4cb3f532011-05-13 12:29:55 +0200565 dev->cli.slave_adr);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530566 status = -ETIMEDOUT;
567 }
568
569 return status;
570}
571
572/**
Linus Walleij82a44132011-05-13 12:31:01 +0200573 * nmk_i2c_xfer_one() - transmit a single I2C message
574 * @dev: device with a message encoded into it
575 * @flags: message flags
576 */
577static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags)
578{
579 int status;
580
581 if (flags & I2C_M_RD) {
582 /* read operation */
583 dev->cli.operation = I2C_READ;
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530584 status = read_i2c(dev, flags);
Linus Walleij82a44132011-05-13 12:31:01 +0200585 } else {
586 /* write operation */
587 dev->cli.operation = I2C_WRITE;
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530588 status = write_i2c(dev, flags);
Linus Walleij82a44132011-05-13 12:31:01 +0200589 }
590
591 if (status || (dev->result)) {
592 u32 i2c_sr;
593 u32 cause;
594
595 i2c_sr = readl(dev->virtbase + I2C_SR);
596 /*
597 * Check if the controller I2C operation status
598 * is set to ABORT(11b).
599 */
600 if (((i2c_sr >> 2) & 0x3) == 0x3) {
601 /* get the abort cause */
602 cause = (i2c_sr >> 4) & 0x7;
Alessandro Rubini23560212012-06-11 22:56:38 +0200603 dev_err(&dev->adev->dev, "%s\n",
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200604 cause >= ARRAY_SIZE(abort_causes) ?
Linus Walleij82a44132011-05-13 12:31:01 +0200605 "unknown reason" :
606 abort_causes[cause]);
607 }
608
609 (void) init_hw(dev);
610
611 status = status ? status : dev->result;
612 }
613
614 return status;
615}
616
617/**
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530618 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
Linus Walleij1804edd2010-09-23 09:03:40 +0200619 * @i2c_adap: Adapter pointer to the controller
620 * @msgs: Pointer to data to be written.
621 * @num_msgs: Number of messages to be executed
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530622 *
623 * This is the function called by the generic kernel i2c_transfer()
624 * or i2c_smbus...() API calls. Note that this code is protected by the
625 * semaphore set in the kernel i2c_transfer() function.
626 *
627 * NOTE:
628 * READ TRANSFER : We impose a restriction of the first message to be the
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200629 * index message for any read transaction.
630 * - a no index is coded as '0',
631 * - 2byte big endian index is coded as '3'
632 * !!! msg[0].buf holds the actual index.
633 * This is compatible with generic messages of smbus emulator
634 * that send a one byte index.
635 * eg. a I2C transation to read 2 bytes from index 0
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530636 * idx = 0;
637 * msg[0].addr = client->addr;
638 * msg[0].flags = 0x0;
639 * msg[0].len = 1;
640 * msg[0].buf = &idx;
641 *
642 * msg[1].addr = client->addr;
643 * msg[1].flags = I2C_M_RD;
644 * msg[1].len = 2;
645 * msg[1].buf = rd_buff
646 * i2c_transfer(adap, msg, 2);
647 *
648 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
649 * If you want to emulate an SMBUS write transaction put the
650 * index as first byte(or first and second) in the payload.
651 * eg. a I2C transation to write 2 bytes from index 1
652 * wr_buff[0] = 0x1;
653 * wr_buff[1] = 0x23;
654 * wr_buff[2] = 0x46;
655 * msg[0].flags = 0x0;
656 * msg[0].len = 3;
657 * msg[0].buf = wr_buff;
658 * i2c_transfer(adap, msg, 1);
659 *
660 * To read or write a block of data (multiple bytes) using SMBUS emulation
661 * please use the i2c_smbus_read_i2c_block_data()
662 * or i2c_smbus_write_i2c_block_data() API
663 */
664static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
665 struct i2c_msg msgs[], int num_msgs)
666{
Ulf Hanssone46d39752014-02-17 16:20:41 +0100667 int status = 0;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530668 int i;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530669 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
Virupax Sadashivpetimathebd10e02011-05-13 12:30:23 +0200670 int j;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530671
Alessandro Rubini23560212012-06-11 22:56:38 +0200672 pm_runtime_get_sync(&dev->adev->dev);
Jonas Aberga20d2392011-05-13 12:29:02 +0200673
Linus Walleij82a44132011-05-13 12:31:01 +0200674 /* Attempt three times to send the message queue */
Virupax Sadashivpetimathebd10e02011-05-13 12:30:23 +0200675 for (j = 0; j < 3; j++) {
676 /* setup the i2c controller */
677 setup_i2c_controller(dev);
Jonas Aberga20d2392011-05-13 12:29:02 +0200678
Virupax Sadashivpetimathebd10e02011-05-13 12:30:23 +0200679 for (i = 0; i < num_msgs; i++) {
Virupax Sadashivpetimathebd10e02011-05-13 12:30:23 +0200680 dev->cli.slave_adr = msgs[i].addr;
681 dev->cli.buffer = msgs[i].buf;
682 dev->cli.count = msgs[i].len;
683 dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
684 dev->result = 0;
685
Linus Walleij82a44132011-05-13 12:31:01 +0200686 status = nmk_i2c_xfer_one(dev, msgs[i].flags);
687 if (status != 0)
Virupax Sadashivpetimathebd10e02011-05-13 12:30:23 +0200688 break;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530689 }
Virupax Sadashivpetimathebd10e02011-05-13 12:30:23 +0200690 if (status == 0)
691 break;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530692 }
Jonas Aberga20d2392011-05-13 12:29:02 +0200693
Alessandro Rubini23560212012-06-11 22:56:38 +0200694 pm_runtime_put_sync(&dev->adev->dev);
Jonas Aberga20d2392011-05-13 12:29:02 +0200695
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530696 /* return the no. messages processed */
697 if (status)
698 return status;
699 else
700 return num_msgs;
701}
702
703/**
704 * disable_interrupts() - disable the interrupts
705 * @dev: private data of controller
Linus Walleij1804edd2010-09-23 09:03:40 +0200706 * @irq: interrupt number
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530707 */
708static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
709{
710 irq = IRQ_MASK(irq);
711 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
712 dev->virtbase + I2C_IMSCR);
713 return 0;
714}
715
716/**
717 * i2c_irq_handler() - interrupt routine
718 * @irq: interrupt number
719 * @arg: data passed to the handler
720 *
721 * This is the interrupt handler for the i2c driver. Currently
722 * it handles the major interrupts like Rx & Tx FIFO management
723 * interrupts, master transaction interrupts, arbitration and
724 * bus error interrupts. The rest of the interrupts are treated as
725 * unhandled.
726 */
727static irqreturn_t i2c_irq_handler(int irq, void *arg)
728{
729 struct nmk_i2c_dev *dev = arg;
730 u32 tft, rft;
731 u32 count;
Wolfram Sang876ae852013-01-24 11:27:46 +0100732 u32 misr, src;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530733
734 /* load Tx FIFO and Rx FIFO threshold values */
735 tft = readl(dev->virtbase + I2C_TFTR);
736 rft = readl(dev->virtbase + I2C_RFTR);
737
738 /* read interrupt status register */
739 misr = readl(dev->virtbase + I2C_MISR);
740
741 src = __ffs(misr);
742 switch ((1 << src)) {
743
744 /* Transmit FIFO nearly empty interrupt */
745 case I2C_IT_TXFNE:
746 {
747 if (dev->cli.operation == I2C_READ) {
748 /*
749 * in read operation why do we care for writing?
750 * so disable the Transmit FIFO interrupt
751 */
752 disable_interrupts(dev, I2C_IT_TXFNE);
753 } else {
Virupax Sadashivpetimath55355342011-05-13 12:30:34 +0200754 fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530755 /*
756 * if done, close the transfer by disabling the
757 * corresponding TXFNE interrupt
758 */
759 if (dev->cli.count == 0)
760 disable_interrupts(dev, I2C_IT_TXFNE);
761 }
762 }
763 break;
764
765 /*
766 * Rx FIFO nearly full interrupt.
767 * This is set when the numer of entries in Rx FIFO is
768 * greater or equal than the threshold value programmed
769 * in RFT
770 */
771 case I2C_IT_RXFNF:
772 for (count = rft; count > 0; count--) {
773 /* Read the Rx FIFO */
774 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
775 dev->cli.buffer++;
776 }
777 dev->cli.count -= rft;
778 dev->cli.xfer_bytes += rft;
779 break;
780
781 /* Rx FIFO full */
782 case I2C_IT_RXFF:
783 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
784 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
785 dev->cli.buffer++;
786 }
787 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
788 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
789 break;
790
791 /* Master Transaction Done with/without stop */
792 case I2C_IT_MTD:
793 case I2C_IT_MTDWS:
794 if (dev->cli.operation == I2C_READ) {
Rabin Vincent1df3ab12010-04-27 10:31:08 +0530795 while (!(readl(dev->virtbase + I2C_RISR)
796 & I2C_IT_RXFE)) {
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530797 if (dev->cli.count == 0)
798 break;
799 *dev->cli.buffer =
800 readb(dev->virtbase + I2C_RFR);
801 dev->cli.buffer++;
802 dev->cli.count--;
803 dev->cli.xfer_bytes++;
804 }
805 }
806
Virupax Sadashivpetimathb5e890f2011-05-13 12:30:42 +0200807 disable_all_interrupts(dev);
808 clear_all_interrupts(dev);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530809
810 if (dev->cli.count) {
Virupax Sadashivpetimath99381be2011-05-13 12:29:28 +0200811 dev->result = -EIO;
Alessandro Rubini23560212012-06-11 22:56:38 +0200812 dev_err(&dev->adev->dev,
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +0200813 "%lu bytes still remain to be xfered\n",
814 dev->cli.count);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530815 (void) init_hw(dev);
816 }
817 complete(&dev->xfer_complete);
818
819 break;
820
821 /* Master Arbitration lost interrupt */
822 case I2C_IT_MAL:
Virupax Sadashivpetimath99381be2011-05-13 12:29:28 +0200823 dev->result = -EIO;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530824 (void) init_hw(dev);
825
826 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
827 complete(&dev->xfer_complete);
828
829 break;
830
831 /*
832 * Bus Error interrupt.
833 * This happens when an unexpected start/stop condition occurs
834 * during the transaction.
835 */
836 case I2C_IT_BERR:
Virupax Sadashivpetimath99381be2011-05-13 12:29:28 +0200837 dev->result = -EIO;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530838 /* get the status */
839 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
840 (void) init_hw(dev);
841
842 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
843 complete(&dev->xfer_complete);
844
845 break;
846
847 /*
848 * Tx FIFO overrun interrupt.
849 * This is set when a write operation in Tx FIFO is performed and
850 * the Tx FIFO is full.
851 */
852 case I2C_IT_TXFOVR:
Virupax Sadashivpetimath99381be2011-05-13 12:29:28 +0200853 dev->result = -EIO;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530854 (void) init_hw(dev);
855
Alessandro Rubini23560212012-06-11 22:56:38 +0200856 dev_err(&dev->adev->dev, "Tx Fifo Over run\n");
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530857 complete(&dev->xfer_complete);
858
859 break;
860
861 /* unhandled interrupts by this driver - TODO*/
862 case I2C_IT_TXFE:
863 case I2C_IT_TXFF:
864 case I2C_IT_RXFE:
865 case I2C_IT_RFSR:
866 case I2C_IT_RFSE:
867 case I2C_IT_WTSR:
868 case I2C_IT_STD:
Alessandro Rubini23560212012-06-11 22:56:38 +0200869 dev_err(&dev->adev->dev, "unhandled Interrupt\n");
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530870 break;
871 default:
Alessandro Rubini23560212012-06-11 22:56:38 +0200872 dev_err(&dev->adev->dev, "spurious Interrupt..\n");
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530873 break;
874 }
875
876 return IRQ_HANDLED;
877}
878
Ulf Hanssonbce9f8d2014-02-17 16:20:53 +0100879#ifdef CONFIG_PM_SLEEP
880static int nmk_i2c_suspend_late(struct device *dev)
Jonas Aberga20d2392011-05-13 12:29:02 +0200881{
Ulf Hansson92199822014-04-10 15:59:36 +0200882 int ret;
Patrice Chotard24e9e152013-01-24 09:47:22 +0100883
Ulf Hansson92199822014-04-10 15:59:36 +0200884 ret = pm_runtime_force_suspend(dev);
885 if (ret)
886 return ret;
887
888 pinctrl_pm_select_sleep_state(dev);
Rabin Vincentb0e751a2011-05-13 12:30:07 +0200889 return 0;
890}
891
Ulf Hanssonbce9f8d2014-02-17 16:20:53 +0100892static int nmk_i2c_resume_early(struct device *dev)
Rabin Vincentb0e751a2011-05-13 12:30:07 +0200893{
Ulf Hansson92199822014-04-10 15:59:36 +0200894 return pm_runtime_force_resume(dev);
Jonas Aberga20d2392011-05-13 12:29:02 +0200895}
Jonas Aberga20d2392011-05-13 12:29:02 +0200896#endif
897
Ulf Hanssone46d39752014-02-17 16:20:41 +0100898#ifdef CONFIG_PM
899static int nmk_i2c_runtime_suspend(struct device *dev)
900{
901 struct amba_device *adev = to_amba_device(dev);
902 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
903
904 clk_disable_unprepare(nmk_i2c->clk);
905 pinctrl_pm_select_idle_state(dev);
906 return 0;
907}
908
909static int nmk_i2c_runtime_resume(struct device *dev)
910{
911 struct amba_device *adev = to_amba_device(dev);
912 struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
913 int ret;
914
915 ret = clk_prepare_enable(nmk_i2c->clk);
916 if (ret) {
917 dev_err(dev, "can't prepare_enable clock\n");
918 return ret;
919 }
920
921 pinctrl_pm_select_default_state(dev);
922
923 ret = init_hw(nmk_i2c);
924 if (ret) {
925 clk_disable_unprepare(nmk_i2c->clk);
926 pinctrl_pm_select_idle_state(dev);
927 }
928
929 return ret;
930}
931#endif
932
Rabin Vincentb0e751a2011-05-13 12:30:07 +0200933static const struct dev_pm_ops nmk_i2c_pm = {
Ulf Hanssonbce9f8d2014-02-17 16:20:53 +0100934 SET_LATE_SYSTEM_SLEEP_PM_OPS(nmk_i2c_suspend_late, nmk_i2c_resume_early)
Rafael J. Wysocki6ed23b82014-12-04 00:34:11 +0100935 SET_RUNTIME_PM_OPS(nmk_i2c_runtime_suspend,
Ulf Hanssone46d39752014-02-17 16:20:41 +0100936 nmk_i2c_runtime_resume,
937 NULL)
Rabin Vincentb0e751a2011-05-13 12:30:07 +0200938};
939
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530940static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
941{
Virupax Sadashivpetimath51a0c8d2012-06-25 17:56:07 +0530942 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530943}
944
945static const struct i2c_algorithm nmk_i2c_algo = {
946 .master_xfer = nmk_i2c_xfer,
947 .functionality = nmk_i2c_functionality
948};
949
Lee Jones43fea582012-08-06 11:09:57 +0100950static void nmk_i2c_of_probe(struct device_node *np,
Linus Walleijc33a0042014-02-03 11:27:26 +0100951 struct nmk_i2c_dev *nmk)
Lee Jones43fea582012-08-06 11:09:57 +0100952{
Linus Walleijc33a0042014-02-03 11:27:26 +0100953 /* Default to 100 kHz if no frequency is given in the node */
954 if (of_property_read_u32(np, "clock-frequency", &nmk->clk_freq))
955 nmk->clk_freq = 100000;
Lee Jones43fea582012-08-06 11:09:57 +0100956
957 /* This driver only supports 'standard' and 'fast' modes of operation. */
Linus Walleijc33a0042014-02-03 11:27:26 +0100958 if (nmk->clk_freq <= 100000)
959 nmk->sm = I2C_FREQ_MODE_STANDARD;
Lee Jones43fea582012-08-06 11:09:57 +0100960 else
Linus Walleijc33a0042014-02-03 11:27:26 +0100961 nmk->sm = I2C_FREQ_MODE_FAST;
962 nmk->tft = 1; /* Tx FIFO threshold */
963 nmk->rft = 8; /* Rx FIFO threshold */
964 nmk->timeout = 200; /* Slave response timeout(ms) */
Lee Jones43fea582012-08-06 11:09:57 +0100965}
966
Alessandro Rubini23560212012-06-11 22:56:38 +0200967static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530968{
969 int ret = 0;
Lee Jones43fea582012-08-06 11:09:57 +0100970 struct device_node *np = adev->dev.of_node;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530971 struct nmk_i2c_dev *dev;
972 struct i2c_adapter *adap;
Linus Walleij3a205be2013-06-10 00:00:58 +0200973 struct i2c_vendor_data *vendor = id->data;
974 u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530975
Ulf Hansson9b2b98a2014-02-18 23:35:44 +0100976 dev = devm_kzalloc(&adev->dev, sizeof(struct nmk_i2c_dev), GFP_KERNEL);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530977 if (!dev) {
Alessandro Rubini23560212012-06-11 22:56:38 +0200978 dev_err(&adev->dev, "cannot allocate memory\n");
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530979 ret = -ENOMEM;
980 goto err_no_mem;
981 }
Linus Walleij3a205be2013-06-10 00:00:58 +0200982 dev->vendor = vendor;
Alessandro Rubini23560212012-06-11 22:56:38 +0200983 dev->adev = adev;
Linus Walleijc33a0042014-02-03 11:27:26 +0100984 nmk_i2c_of_probe(np, dev);
985
986 if (dev->tft > max_fifo_threshold) {
987 dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n",
988 dev->tft, max_fifo_threshold);
989 dev->tft = max_fifo_threshold;
990 }
991
992 if (dev->rft > max_fifo_threshold) {
993 dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n",
994 dev->rft, max_fifo_threshold);
995 dev->rft = max_fifo_threshold;
996 }
997
Alessandro Rubini23560212012-06-11 22:56:38 +0200998 amba_set_drvdata(adev, dev);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +0530999
Ulf Hansson9b2b98a2014-02-18 23:35:44 +01001000 dev->virtbase = devm_ioremap(&adev->dev, adev->res.start,
1001 resource_size(&adev->res));
Ulf Hansson37e5eb02014-04-10 16:19:29 +02001002 if (!dev->virtbase) {
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301003 ret = -ENOMEM;
Ulf Hansson9b2b98a2014-02-18 23:35:44 +01001004 goto err_no_mem;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301005 }
1006
Alessandro Rubini23560212012-06-11 22:56:38 +02001007 dev->irq = adev->irq[0];
Ulf Hansson9b2b98a2014-02-18 23:35:44 +01001008 ret = devm_request_irq(&adev->dev, dev->irq, i2c_irq_handler, 0,
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301009 DRIVER_NAME, dev);
1010 if (ret) {
Alessandro Rubini23560212012-06-11 22:56:38 +02001011 dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq);
Ulf Hansson9b2b98a2014-02-18 23:35:44 +01001012 goto err_no_mem;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301013 }
1014
Alessandro Rubini23560212012-06-11 22:56:38 +02001015 pm_suspend_ignore_children(&adev->dev, true);
Rabin Vincentb0e751a2011-05-13 12:30:07 +02001016
Ulf Hansson9b2b98a2014-02-18 23:35:44 +01001017 dev->clk = devm_clk_get(&adev->dev, NULL);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301018 if (IS_ERR(dev->clk)) {
Alessandro Rubini23560212012-06-11 22:56:38 +02001019 dev_err(&adev->dev, "could not get i2c clock\n");
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301020 ret = PTR_ERR(dev->clk);
Ulf Hansson9b2b98a2014-02-18 23:35:44 +01001021 goto err_no_mem;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301022 }
1023
Ulf Hanssone46d39752014-02-17 16:20:41 +01001024 ret = clk_prepare_enable(dev->clk);
1025 if (ret) {
1026 dev_err(&adev->dev, "can't prepare_enable clock\n");
1027 goto err_no_mem;
1028 }
1029
1030 init_hw(dev);
1031
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301032 adap = &dev->adap;
Lee Jones43fea582012-08-06 11:09:57 +01001033 adap->dev.of_node = np;
Alessandro Rubini23560212012-06-11 22:56:38 +02001034 adap->dev.parent = &adev->dev;
Wolfram Sang19181d72014-07-10 13:46:28 +02001035 adap->owner = THIS_MODULE;
1036 adap->class = I2C_CLASS_DEPRECATED;
1037 adap->algo = &nmk_i2c_algo;
1038 adap->timeout = msecs_to_jiffies(dev->timeout);
Linus Walleij6d779a42010-11-30 16:59:29 +01001039 snprintf(adap->name, sizeof(adap->name),
Linus Walleijd15b8572013-06-15 22:38:14 +02001040 "Nomadik I2C at %pR", &adev->res);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301041
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301042 i2c_set_adapdata(adap, dev);
1043
Alessandro Rubini23560212012-06-11 22:56:38 +02001044 dev_info(&adev->dev,
Jonas Aaberg8abf6fbb2011-10-20 18:23:01 +02001045 "initialize %s on virtual base %p\n",
1046 adap->name, dev->virtbase);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301047
Linus Walleijd15b8572013-06-15 22:38:14 +02001048 ret = i2c_add_adapter(adap);
Wolfram Sangea734402016-08-09 13:36:17 +02001049 if (ret)
Ulf Hanssone46d39752014-02-17 16:20:41 +01001050 goto err_no_adap;
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301051
Alessandro Rubini23560212012-06-11 22:56:38 +02001052 pm_runtime_put(&adev->dev);
1053
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301054 return 0;
1055
Ulf Hanssone46d39752014-02-17 16:20:41 +01001056 err_no_adap:
1057 clk_disable_unprepare(dev->clk);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301058 err_no_mem:
1059
1060 return ret;
1061}
1062
Alessandro Rubini23560212012-06-11 22:56:38 +02001063static int nmk_i2c_remove(struct amba_device *adev)
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301064{
Alessandro Rubini23560212012-06-11 22:56:38 +02001065 struct resource *res = &adev->res;
1066 struct nmk_i2c_dev *dev = amba_get_drvdata(adev);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301067
1068 i2c_del_adapter(&dev->adap);
1069 flush_i2c_fifo(dev);
1070 disable_all_interrupts(dev);
1071 clear_all_interrupts(dev);
1072 /* disable the controller */
1073 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
Ulf Hanssone46d39752014-02-17 16:20:41 +01001074 clk_disable_unprepare(dev->clk);
Rabin Vincenta1c27672010-04-27 10:31:07 +05301075 if (res)
1076 release_mem_region(res->start, resource_size(res));
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301077
1078 return 0;
1079}
1080
Linus Walleij3a205be2013-06-10 00:00:58 +02001081static struct i2c_vendor_data vendor_stn8815 = {
1082 .has_mtdws = false,
1083 .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */
1084};
1085
1086static struct i2c_vendor_data vendor_db8500 = {
1087 .has_mtdws = true,
1088 .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */
1089};
1090
Alessandro Rubini23560212012-06-11 22:56:38 +02001091static struct amba_id nmk_i2c_ids[] = {
1092 {
1093 .id = 0x00180024,
1094 .mask = 0x00ffffff,
Linus Walleij3a205be2013-06-10 00:00:58 +02001095 .data = &vendor_stn8815,
Alessandro Rubini23560212012-06-11 22:56:38 +02001096 },
1097 {
1098 .id = 0x00380024,
1099 .mask = 0x00ffffff,
Linus Walleij3a205be2013-06-10 00:00:58 +02001100 .data = &vendor_db8500,
Alessandro Rubini23560212012-06-11 22:56:38 +02001101 },
1102 {},
1103};
1104
1105MODULE_DEVICE_TABLE(amba, nmk_i2c_ids);
1106
1107static struct amba_driver nmk_i2c_driver = {
1108 .drv = {
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301109 .owner = THIS_MODULE,
1110 .name = DRIVER_NAME,
Rabin Vincentb0e751a2011-05-13 12:30:07 +02001111 .pm = &nmk_i2c_pm,
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301112 },
Alessandro Rubini23560212012-06-11 22:56:38 +02001113 .id_table = nmk_i2c_ids,
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301114 .probe = nmk_i2c_probe,
Alessandro Rubini23560212012-06-11 22:56:38 +02001115 .remove = nmk_i2c_remove,
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301116};
1117
1118static int __init nmk_i2c_init(void)
1119{
Alessandro Rubini23560212012-06-11 22:56:38 +02001120 return amba_driver_register(&nmk_i2c_driver);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301121}
1122
1123static void __exit nmk_i2c_exit(void)
1124{
Alessandro Rubini23560212012-06-11 22:56:38 +02001125 amba_driver_unregister(&nmk_i2c_driver);
srinidhi kasagar3f9900f2010-02-01 19:44:54 +05301126}
1127
1128subsys_initcall(nmk_i2c_init);
1129module_exit(nmk_i2c_exit);
1130
1131MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
1132MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
1133MODULE_LICENSE("GPL");