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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2003-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 * Copyright 2003 Benjamin Herrenschmidt
10 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040012 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
Linus Torvalds1da177e2005-04-16 15:20:36 -070029 *
Jeff Garzik953d1132005-08-26 19:46:24 -040030 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070035 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/init.h>
41#include <linux/blkdev.h>
42#include <linux/delay.h>
43#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050044#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
46#include <linux/libata.h>
47
48#define DRV_NAME "sata_sil"
49#define DRV_VERSION "0.9"
50
51enum {
Tejun Heoe4deec62005-08-23 07:27:25 +090052 SIL_FLAG_MOD15WRITE = (1 << 30),
53
Linus Torvalds1da177e2005-04-16 15:20:36 -070054 sil_3112 = 0,
Tejun Heoe4deec62005-08-23 07:27:25 +090055 sil_3112_m15w = 1,
56 sil_3114 = 2,
Linus Torvalds1da177e2005-04-16 15:20:36 -070057
58 SIL_FIFO_R0 = 0x40,
59 SIL_FIFO_W0 = 0x41,
60 SIL_FIFO_R1 = 0x44,
61 SIL_FIFO_W1 = 0x45,
62 SIL_FIFO_R2 = 0x240,
63 SIL_FIFO_W2 = 0x241,
64 SIL_FIFO_R3 = 0x244,
65 SIL_FIFO_W3 = 0x245,
66
67 SIL_SYSCFG = 0x48,
68 SIL_MASK_IDE0_INT = (1 << 22),
69 SIL_MASK_IDE1_INT = (1 << 23),
70 SIL_MASK_IDE2_INT = (1 << 24),
71 SIL_MASK_IDE3_INT = (1 << 25),
72 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
73 SIL_MASK_4PORT = SIL_MASK_2PORT |
74 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
75
76 SIL_IDE2_BMDMA = 0x200,
77
78 SIL_INTR_STEERING = (1 << 1),
79 SIL_QUIRK_MOD15WRITE = (1 << 0),
80 SIL_QUIRK_UDMA5MAX = (1 << 1),
81};
82
83static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
84static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
85static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
86static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
87static void sil_post_set_mode (struct ata_port *ap);
88
Jeff Garzik374b1872005-08-30 05:42:52 -040089
Jeff Garzik3b7d6972005-11-10 11:04:11 -050090static const struct pci_device_id sil_pci_tbl[] = {
Tejun Heoe4deec62005-08-23 07:27:25 +090091 { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
92 { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
Linus Torvalds1da177e2005-04-16 15:20:36 -070093 { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
94 { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
Tejun Heoe4deec62005-08-23 07:27:25 +090095 { 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
96 { 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
97 { 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
Linus Torvalds1da177e2005-04-16 15:20:36 -070098 { } /* terminate list */
99};
100
101
102/* TODO firmware versions should be added - eric */
103static const struct sil_drivelist {
104 const char * product;
105 unsigned int quirk;
106} sil_blacklist [] = {
107 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
108 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
109 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
110 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
111 { "ST380013AS", SIL_QUIRK_MOD15WRITE },
112 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
113 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
114 { "ST3160023AS", SIL_QUIRK_MOD15WRITE },
115 { "ST3120026AS", SIL_QUIRK_MOD15WRITE },
116 { "ST3200822AS", SIL_QUIRK_MOD15WRITE },
117 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
118 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
119 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
120 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
121 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
122 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
123 { }
124};
125
126static struct pci_driver sil_pci_driver = {
127 .name = DRV_NAME,
128 .id_table = sil_pci_tbl,
129 .probe = sil_init_one,
130 .remove = ata_pci_remove_one,
131};
132
Jeff Garzik193515d2005-11-07 00:59:37 -0500133static struct scsi_host_template sil_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134 .module = THIS_MODULE,
135 .name = DRV_NAME,
136 .ioctl = ata_scsi_ioctl,
137 .queuecommand = ata_scsi_queuecmd,
Tejun Heo35daeb82006-02-10 15:10:48 +0900138 .eh_timed_out = ata_scsi_timed_out,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139 .eh_strategy_handler = ata_scsi_error,
140 .can_queue = ATA_DEF_QUEUE,
141 .this_id = ATA_SHT_THIS_ID,
142 .sg_tablesize = LIBATA_MAX_PRD,
143 .max_sectors = ATA_MAX_SECTORS,
144 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
145 .emulated = ATA_SHT_EMULATED,
146 .use_clustering = ATA_SHT_USE_CLUSTERING,
147 .proc_name = DRV_NAME,
148 .dma_boundary = ATA_DMA_BOUNDARY,
149 .slave_configure = ata_scsi_slave_config,
150 .bios_param = ata_std_bios_param,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151};
152
Jeff Garzik057ace52005-10-22 14:27:05 -0400153static const struct ata_port_operations sil_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154 .port_disable = ata_port_disable,
155 .dev_config = sil_dev_config,
156 .tf_load = ata_tf_load,
157 .tf_read = ata_tf_read,
158 .check_status = ata_check_status,
159 .exec_command = ata_exec_command,
160 .dev_select = ata_std_dev_select,
161 .phy_reset = sata_phy_reset,
162 .post_set_mode = sil_post_set_mode,
163 .bmdma_setup = ata_bmdma_setup,
164 .bmdma_start = ata_bmdma_start,
165 .bmdma_stop = ata_bmdma_stop,
166 .bmdma_status = ata_bmdma_status,
167 .qc_prep = ata_qc_prep,
168 .qc_issue = ata_qc_issue_prot,
169 .eng_timeout = ata_eng_timeout,
170 .irq_handler = ata_interrupt,
171 .irq_clear = ata_bmdma_irq_clear,
172 .scr_read = sil_scr_read,
173 .scr_write = sil_scr_write,
174 .port_start = ata_port_start,
175 .port_stop = ata_port_stop,
Jeff Garzik374b1872005-08-30 05:42:52 -0400176 .host_stop = ata_pci_host_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177};
178
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100179static const struct ata_port_info sil_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180 /* sil_3112 */
181 {
182 .sht = &sil_sht,
183 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
184 ATA_FLAG_SRST | ATA_FLAG_MMIO,
185 .pio_mask = 0x1f, /* pio0-4 */
186 .mwdma_mask = 0x07, /* mwdma0-2 */
187 .udma_mask = 0x3f, /* udma0-5 */
188 .port_ops = &sil_ops,
Tejun Heoe4deec62005-08-23 07:27:25 +0900189 }, /* sil_3112_15w - keep it sync'd w/ sil_3112 */
190 {
191 .sht = &sil_sht,
192 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
193 ATA_FLAG_SRST | ATA_FLAG_MMIO |
194 SIL_FLAG_MOD15WRITE,
195 .pio_mask = 0x1f, /* pio0-4 */
196 .mwdma_mask = 0x07, /* mwdma0-2 */
197 .udma_mask = 0x3f, /* udma0-5 */
198 .port_ops = &sil_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199 }, /* sil_3114 */
200 {
201 .sht = &sil_sht,
202 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
203 ATA_FLAG_SRST | ATA_FLAG_MMIO,
204 .pio_mask = 0x1f, /* pio0-4 */
205 .mwdma_mask = 0x07, /* mwdma0-2 */
206 .udma_mask = 0x3f, /* udma0-5 */
207 .port_ops = &sil_ops,
208 },
209};
210
211/* per-port register offsets */
212/* TODO: we can probably calculate rather than use a table */
213static const struct {
214 unsigned long tf; /* ATA taskfile register block */
215 unsigned long ctl; /* ATA control/altstatus register block */
216 unsigned long bmdma; /* DMA register block */
217 unsigned long scr; /* SATA control register block */
218 unsigned long sien; /* SATA Interrupt Enable register */
219 unsigned long xfer_mode;/* data transfer mode register */
220} sil_port[] = {
221 /* port 0 ... */
222 { 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
223 { 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
224 { 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
225 { 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
226 /* ... port 3 */
227};
228
229MODULE_AUTHOR("Jeff Garzik");
230MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
231MODULE_LICENSE("GPL");
232MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
233MODULE_VERSION(DRV_VERSION);
234
Jeff Garzik51e9f2f2006-01-27 16:50:27 -0500235static int slow_down = 0;
236module_param(slow_down, int, 0444);
237MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
238
Jeff Garzik374b1872005-08-30 05:42:52 -0400239
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
241{
242 u8 cache_line = 0;
243 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
244 return cache_line;
245}
246
247static void sil_post_set_mode (struct ata_port *ap)
248{
249 struct ata_host_set *host_set = ap->host_set;
250 struct ata_device *dev;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400251 void __iomem *addr =
252 host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 u32 tmp, dev_mode[2];
254 unsigned int i;
255
256 for (i = 0; i < 2; i++) {
257 dev = &ap->device[i];
258 if (!ata_dev_present(dev))
259 dev_mode[i] = 0; /* PIO0/1/2 */
260 else if (dev->flags & ATA_DFLAG_PIO)
261 dev_mode[i] = 1; /* PIO3/4 */
262 else
263 dev_mode[i] = 3; /* UDMA */
264 /* value 2 indicates MDMA */
265 }
266
267 tmp = readl(addr);
268 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
269 tmp |= dev_mode[0];
270 tmp |= (dev_mode[1] << 4);
271 writel(tmp, addr);
272 readl(addr); /* flush */
273}
274
275static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
276{
277 unsigned long offset = ap->ioaddr.scr_addr;
278
279 switch (sc_reg) {
280 case SCR_STATUS:
281 return offset + 4;
282 case SCR_ERROR:
283 return offset + 8;
284 case SCR_CONTROL:
285 return offset;
286 default:
287 /* do nothing */
288 break;
289 }
290
291 return 0;
292}
293
294static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
295{
Al Viro9aa36e82005-10-21 06:46:02 +0100296 void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297 if (mmio)
298 return readl(mmio);
299 return 0xffffffffU;
300}
301
302static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
303{
Al Viro9aa36e82005-10-21 06:46:02 +0100304 void *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305 if (mmio)
306 writel(val, mmio);
307}
308
309/**
310 * sil_dev_config - Apply device/host-specific errata fixups
311 * @ap: Port containing device to be examined
312 * @dev: Device to be examined
313 *
314 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
315 * device is known to be present, this function is called.
316 * We apply two errata fixups which are specific to Silicon Image,
317 * a Seagate and a Maxtor fixup.
318 *
319 * For certain Seagate devices, we must limit the maximum sectors
320 * to under 8K.
321 *
322 * For certain Maxtor devices, we must not program the drive
323 * beyond udma5.
324 *
325 * Both fixups are unfairly pessimistic. As soon as I get more
326 * information on these errata, I will create a more exhaustive
327 * list, and apply the fixups to only the specific
328 * devices/hosts/firmwares that need it.
329 *
330 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
331 * The Maxtor quirk is in the blacklist, but I'm keeping the original
332 * pessimistic fix for the following reasons...
333 * - There seems to be less info on it, only one device gleaned off the
334 * Windows driver, maybe only one is affected. More info would be greatly
335 * appreciated.
336 * - But then again UDMA5 is hardly anything to complain about
337 */
338static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
339{
340 unsigned int n, quirks = 0;
341 unsigned char model_num[40];
342 const char *s;
343 unsigned int len;
344
345 ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
346 sizeof(model_num));
347 s = &model_num[0];
348 len = strnlen(s, sizeof(model_num));
349
350 /* ATAPI specifies that empty space is blank-filled; remove blanks */
351 while ((len > 0) && (s[len - 1] == ' '))
352 len--;
353
Jeff Garzik8a60a072005-07-31 13:13:24 -0400354 for (n = 0; sil_blacklist[n].product; n++)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355 if (!memcmp(sil_blacklist[n].product, s,
356 strlen(sil_blacklist[n].product))) {
357 quirks = sil_blacklist[n].quirk;
358 break;
359 }
Jeff Garzik8a60a072005-07-31 13:13:24 -0400360
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361 /* limit requests to 15 sectors */
Jeff Garzik51e9f2f2006-01-27 16:50:27 -0500362 if (slow_down ||
363 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
364 (quirks & SIL_QUIRK_MOD15WRITE))) {
365 printk(KERN_INFO "ata%u(%u): applying Seagate errata fix (mod15write workaround)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366 ap->id, dev->devno);
367 ap->host->max_sectors = 15;
368 ap->host->hostt->max_sectors = 15;
369 dev->flags |= ATA_DFLAG_LOCK_SECTORS;
370 return;
371 }
372
373 /* limit to udma5 */
374 if (quirks & SIL_QUIRK_UDMA5MAX) {
375 printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
376 ap->id, dev->devno, s);
377 ap->udma_mask &= ATA_UDMA5;
378 return;
379 }
380}
381
382static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
383{
384 static int printed_version;
385 struct ata_probe_ent *probe_ent = NULL;
386 unsigned long base;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400387 void __iomem *mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388 int rc;
389 unsigned int i;
390 int pci_dev_busy = 0;
391 u32 tmp, irq_mask;
392 u8 cls;
393
394 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -0500395 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396
397 /*
398 * If this driver happens to only be useful on Apple's K2, then
399 * we should check that here as it has a normal Serverworks ID
400 */
401 rc = pci_enable_device(pdev);
402 if (rc)
403 return rc;
404
405 rc = pci_request_regions(pdev, DRV_NAME);
406 if (rc) {
407 pci_dev_busy = 1;
408 goto err_out;
409 }
410
411 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
412 if (rc)
413 goto err_out_regions;
414 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
415 if (rc)
416 goto err_out_regions;
417
418 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
419 if (probe_ent == NULL) {
420 rc = -ENOMEM;
421 goto err_out_regions;
422 }
423
424 memset(probe_ent, 0, sizeof(*probe_ent));
425 INIT_LIST_HEAD(&probe_ent->node);
426 probe_ent->dev = pci_dev_to_dev(pdev);
427 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
428 probe_ent->sht = sil_port_info[ent->driver_data].sht;
429 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
430 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
431 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
432 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
433 probe_ent->irq = pdev->irq;
434 probe_ent->irq_flags = SA_SHIRQ;
435 probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
436
Jeff Garzik374b1872005-08-30 05:42:52 -0400437 mmio_base = pci_iomap(pdev, 5, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438 if (mmio_base == NULL) {
439 rc = -ENOMEM;
440 goto err_out_free_ent;
441 }
442
443 probe_ent->mmio_base = mmio_base;
444
445 base = (unsigned long) mmio_base;
446
447 for (i = 0; i < probe_ent->n_ports; i++) {
448 probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
449 probe_ent->port[i].altstatus_addr =
450 probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
451 probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
452 probe_ent->port[i].scr_addr = base + sil_port[i].scr;
453 ata_std_ports(&probe_ent->port[i]);
454 }
455
456 /* Initialize FIFO PCI bus arbitration */
457 cls = sil_get_device_cache_line(pdev);
458 if (cls) {
459 cls >>= 3;
460 cls++; /* cls = (line_size/8)+1 */
461 writeb(cls, mmio_base + SIL_FIFO_R0);
462 writeb(cls, mmio_base + SIL_FIFO_W0);
463 writeb(cls, mmio_base + SIL_FIFO_R1);
Jens Axboee1dd23a2005-06-08 13:02:25 +0200464 writeb(cls, mmio_base + SIL_FIFO_W1);
465 if (ent->driver_data == sil_3114) {
466 writeb(cls, mmio_base + SIL_FIFO_R2);
467 writeb(cls, mmio_base + SIL_FIFO_W2);
468 writeb(cls, mmio_base + SIL_FIFO_R3);
469 writeb(cls, mmio_base + SIL_FIFO_W3);
470 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700471 } else
Jeff Garzika9524a72005-10-30 14:39:11 -0500472 dev_printk(KERN_WARNING, &pdev->dev,
473 "cache line size not set. Driver may not function\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474
475 if (ent->driver_data == sil_3114) {
476 irq_mask = SIL_MASK_4PORT;
477
478 /* flip the magic "make 4 ports work" bit */
479 tmp = readl(mmio_base + SIL_IDE2_BMDMA);
480 if ((tmp & SIL_INTR_STEERING) == 0)
481 writel(tmp | SIL_INTR_STEERING,
482 mmio_base + SIL_IDE2_BMDMA);
483
484 } else {
485 irq_mask = SIL_MASK_2PORT;
486 }
487
488 /* make sure IDE0/1/2/3 interrupts are not masked */
489 tmp = readl(mmio_base + SIL_SYSCFG);
490 if (tmp & irq_mask) {
491 tmp &= ~irq_mask;
492 writel(tmp, mmio_base + SIL_SYSCFG);
493 readl(mmio_base + SIL_SYSCFG); /* flush */
494 }
495
496 /* mask all SATA phy-related interrupts */
497 /* TODO: unmask bit 6 (SError N bit) for hotplug */
498 for (i = 0; i < probe_ent->n_ports; i++)
499 writel(0, mmio_base + sil_port[i].sien);
500
501 pci_set_master(pdev);
502
503 /* FIXME: check ata_device_add return value */
504 ata_device_add(probe_ent);
505 kfree(probe_ent);
506
507 return 0;
508
509err_out_free_ent:
510 kfree(probe_ent);
511err_out_regions:
512 pci_release_regions(pdev);
513err_out:
514 if (!pci_dev_busy)
515 pci_disable_device(pdev);
516 return rc;
517}
518
519static int __init sil_init(void)
520{
521 return pci_module_init(&sil_pci_driver);
522}
523
524static void __exit sil_exit(void)
525{
526 pci_unregister_driver(&sil_pci_driver);
527}
528
529
530module_init(sil_init);
531module_exit(sil_exit);