Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source for the r8a7790 SoC |
| 3 | * |
Sergei Shtylyov | d8913c6 | 2014-02-20 02:20:43 +0300 | [diff] [blame] | 4 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2014 Cogent Embedded Inc. |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 6 | * |
| 7 | * This file is licensed under the terms of the GNU General Public License |
| 8 | * version 2. This program is licensed "as is" without any warranty of any |
| 9 | * kind, whether express or implied. |
| 10 | */ |
| 11 | |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 12 | #include <dt-bindings/clock/r8a7790-clock.h> |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 16 | / { |
| 17 | compatible = "renesas,r8a7790"; |
| 18 | interrupt-parent = <&gic>; |
Takashi Yoshii | 8585deb | 2013-03-29 16:49:17 +0900 | [diff] [blame] | 19 | #address-cells = <2>; |
| 20 | #size-cells = <2>; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 21 | |
Wolfram Sang | 6b1d7c6 | 2014-02-16 10:40:58 +0100 | [diff] [blame] | 22 | aliases { |
| 23 | i2c0 = &i2c0; |
| 24 | i2c1 = &i2c1; |
| 25 | i2c2 = &i2c2; |
| 26 | i2c3 = &i2c3; |
Geert Uytterhoeven | fad6d45 | 2014-02-25 11:30:13 +0100 | [diff] [blame] | 27 | spi0 = &qspi; |
Geert Uytterhoeven | ae8a614 | 2014-02-25 11:30:15 +0100 | [diff] [blame] | 28 | spi1 = &msiof0; |
| 29 | spi2 = &msiof1; |
| 30 | spi3 = &msiof2; |
| 31 | spi4 = &msiof3; |
Wolfram Sang | 6b1d7c6 | 2014-02-16 10:40:58 +0100 | [diff] [blame] | 32 | }; |
| 33 | |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 34 | cpus { |
| 35 | #address-cells = <1>; |
| 36 | #size-cells = <0>; |
| 37 | |
| 38 | cpu0: cpu@0 { |
| 39 | device_type = "cpu"; |
| 40 | compatible = "arm,cortex-a15"; |
| 41 | reg = <0>; |
| 42 | clock-frequency = <1300000000>; |
| 43 | }; |
Magnus Damm | c1f9597 | 2013-08-29 08:22:17 +0900 | [diff] [blame] | 44 | |
| 45 | cpu1: cpu@1 { |
| 46 | device_type = "cpu"; |
| 47 | compatible = "arm,cortex-a15"; |
| 48 | reg = <1>; |
| 49 | clock-frequency = <1300000000>; |
| 50 | }; |
| 51 | |
| 52 | cpu2: cpu@2 { |
| 53 | device_type = "cpu"; |
| 54 | compatible = "arm,cortex-a15"; |
| 55 | reg = <2>; |
| 56 | clock-frequency = <1300000000>; |
| 57 | }; |
| 58 | |
| 59 | cpu3: cpu@3 { |
| 60 | device_type = "cpu"; |
| 61 | compatible = "arm,cortex-a15"; |
| 62 | reg = <3>; |
| 63 | clock-frequency = <1300000000>; |
| 64 | }; |
Magnus Damm | 2007e74 | 2013-09-15 00:28:58 +0900 | [diff] [blame] | 65 | |
| 66 | cpu4: cpu@4 { |
| 67 | device_type = "cpu"; |
| 68 | compatible = "arm,cortex-a7"; |
| 69 | reg = <0x100>; |
| 70 | clock-frequency = <780000000>; |
| 71 | }; |
| 72 | |
| 73 | cpu5: cpu@5 { |
| 74 | device_type = "cpu"; |
| 75 | compatible = "arm,cortex-a7"; |
| 76 | reg = <0x101>; |
| 77 | clock-frequency = <780000000>; |
| 78 | }; |
| 79 | |
| 80 | cpu6: cpu@6 { |
| 81 | device_type = "cpu"; |
| 82 | compatible = "arm,cortex-a7"; |
| 83 | reg = <0x102>; |
| 84 | clock-frequency = <780000000>; |
| 85 | }; |
| 86 | |
| 87 | cpu7: cpu@7 { |
| 88 | device_type = "cpu"; |
| 89 | compatible = "arm,cortex-a7"; |
| 90 | reg = <0x103>; |
| 91 | clock-frequency = <780000000>; |
| 92 | }; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 93 | }; |
| 94 | |
| 95 | gic: interrupt-controller@f1001000 { |
| 96 | compatible = "arm,cortex-a15-gic"; |
| 97 | #interrupt-cells = <3>; |
| 98 | #address-cells = <0>; |
| 99 | interrupt-controller; |
Takashi Yoshii | 8585deb | 2013-03-29 16:49:17 +0900 | [diff] [blame] | 100 | reg = <0 0xf1001000 0 0x1000>, |
| 101 | <0 0xf1002000 0 0x1000>, |
| 102 | <0 0xf1004000 0 0x2000>, |
| 103 | <0 0xf1006000 0 0x2000>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 104 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 105 | }; |
| 106 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 107 | gpio0: gpio@e6050000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 108 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 109 | reg = <0 0xe6050000 0 0x50>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 110 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 111 | #gpio-cells = <2>; |
| 112 | gpio-controller; |
| 113 | gpio-ranges = <&pfc 0 0 32>; |
| 114 | #interrupt-cells = <2>; |
| 115 | interrupt-controller; |
| 116 | }; |
| 117 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 118 | gpio1: gpio@e6051000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 119 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 120 | reg = <0 0xe6051000 0 0x50>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 121 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 122 | #gpio-cells = <2>; |
| 123 | gpio-controller; |
| 124 | gpio-ranges = <&pfc 0 32 32>; |
| 125 | #interrupt-cells = <2>; |
| 126 | interrupt-controller; |
| 127 | }; |
| 128 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 129 | gpio2: gpio@e6052000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 130 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 131 | reg = <0 0xe6052000 0 0x50>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 132 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 133 | #gpio-cells = <2>; |
| 134 | gpio-controller; |
| 135 | gpio-ranges = <&pfc 0 64 32>; |
| 136 | #interrupt-cells = <2>; |
| 137 | interrupt-controller; |
| 138 | }; |
| 139 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 140 | gpio3: gpio@e6053000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 141 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 142 | reg = <0 0xe6053000 0 0x50>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 143 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 144 | #gpio-cells = <2>; |
| 145 | gpio-controller; |
| 146 | gpio-ranges = <&pfc 0 96 32>; |
| 147 | #interrupt-cells = <2>; |
| 148 | interrupt-controller; |
| 149 | }; |
| 150 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 151 | gpio4: gpio@e6054000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 152 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 153 | reg = <0 0xe6054000 0 0x50>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 154 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 155 | #gpio-cells = <2>; |
| 156 | gpio-controller; |
| 157 | gpio-ranges = <&pfc 0 128 32>; |
| 158 | #interrupt-cells = <2>; |
| 159 | interrupt-controller; |
| 160 | }; |
| 161 | |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 162 | gpio5: gpio@e6055000 { |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 163 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
Magnus Damm | 23de227 | 2013-11-21 14:19:29 +0900 | [diff] [blame] | 164 | reg = <0 0xe6055000 0 0x50>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 165 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | f98e10c | 2013-05-10 15:51:14 +0200 | [diff] [blame] | 166 | #gpio-cells = <2>; |
| 167 | gpio-controller; |
| 168 | gpio-ranges = <&pfc 0 160 32>; |
| 169 | #interrupt-cells = <2>; |
| 170 | interrupt-controller; |
| 171 | }; |
| 172 | |
Magnus Damm | 03e2f56 | 2013-11-20 16:59:30 +0900 | [diff] [blame] | 173 | thermal@e61f0000 { |
| 174 | compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; |
| 175 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; |
Magnus Damm | 03e2f56 | 2013-11-20 16:59:30 +0900 | [diff] [blame] | 176 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
Geert Uytterhoeven | d3a439d | 2014-01-07 19:57:14 +0100 | [diff] [blame] | 177 | clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; |
Magnus Damm | 03e2f56 | 2013-11-20 16:59:30 +0900 | [diff] [blame] | 178 | }; |
| 179 | |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 180 | timer { |
| 181 | compatible = "arm,armv7-timer"; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 182 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 183 | <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 184 | <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 185 | <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 186 | }; |
Magnus Damm | 8f5ec0a | 2013-03-28 00:49:54 +0900 | [diff] [blame] | 187 | |
| 188 | irqc0: interrupt-controller@e61c0000 { |
Magnus Damm | 220fc35 | 2013-11-20 09:07:40 +0900 | [diff] [blame] | 189 | compatible = "renesas,irqc-r8a7790", "renesas,irqc"; |
Magnus Damm | 8f5ec0a | 2013-03-28 00:49:54 +0900 | [diff] [blame] | 190 | #interrupt-cells = <2>; |
| 191 | interrupt-controller; |
Takashi Yoshii | 8585deb | 2013-03-29 16:49:17 +0900 | [diff] [blame] | 192 | reg = <0 0xe61c0000 0 0x200>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 193 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
| 194 | <0 1 IRQ_TYPE_LEVEL_HIGH>, |
| 195 | <0 2 IRQ_TYPE_LEVEL_HIGH>, |
| 196 | <0 3 IRQ_TYPE_LEVEL_HIGH>; |
Magnus Damm | 8f5ec0a | 2013-03-28 00:49:54 +0900 | [diff] [blame] | 197 | }; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 198 | |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 199 | i2c0: i2c@e6508000 { |
| 200 | #address-cells = <1>; |
| 201 | #size-cells = <0>; |
| 202 | compatible = "renesas,i2c-r8a7790"; |
| 203 | reg = <0 0xe6508000 0 0x40>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 204 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; |
Ben Dooks | 2450bad | 2014-01-20 11:44:21 +0000 | [diff] [blame] | 205 | clocks = <&mstp9_clks R8A7790_CLK_I2C0>; |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 206 | status = "disabled"; |
| 207 | }; |
| 208 | |
| 209 | i2c1: i2c@e6518000 { |
| 210 | #address-cells = <1>; |
| 211 | #size-cells = <0>; |
| 212 | compatible = "renesas,i2c-r8a7790"; |
| 213 | reg = <0 0xe6518000 0 0x40>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 214 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; |
Ben Dooks | 2450bad | 2014-01-20 11:44:21 +0000 | [diff] [blame] | 215 | clocks = <&mstp9_clks R8A7790_CLK_I2C1>; |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 216 | status = "disabled"; |
| 217 | }; |
| 218 | |
| 219 | i2c2: i2c@e6530000 { |
| 220 | #address-cells = <1>; |
| 221 | #size-cells = <0>; |
| 222 | compatible = "renesas,i2c-r8a7790"; |
| 223 | reg = <0 0xe6530000 0 0x40>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 224 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; |
Ben Dooks | 2450bad | 2014-01-20 11:44:21 +0000 | [diff] [blame] | 225 | clocks = <&mstp9_clks R8A7790_CLK_I2C2>; |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 226 | status = "disabled"; |
| 227 | }; |
| 228 | |
| 229 | i2c3: i2c@e6540000 { |
| 230 | #address-cells = <1>; |
| 231 | #size-cells = <0>; |
| 232 | compatible = "renesas,i2c-r8a7790"; |
| 233 | reg = <0 0xe6540000 0 0x40>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 234 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; |
Ben Dooks | 2450bad | 2014-01-20 11:44:21 +0000 | [diff] [blame] | 235 | clocks = <&mstp9_clks R8A7790_CLK_I2C3>; |
Guennadi Liakhovetski | edd2b9f | 2013-09-26 19:20:58 +0200 | [diff] [blame] | 236 | status = "disabled"; |
| 237 | }; |
| 238 | |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 239 | mmcif0: mmcif@ee200000 { |
Magnus Damm | 063e8560 | 2013-11-20 09:05:53 +0900 | [diff] [blame] | 240 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 241 | reg = <0 0xee200000 0 0x80>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 242 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 243 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 244 | reg-io-width = <4>; |
| 245 | status = "disabled"; |
| 246 | }; |
| 247 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 248 | mmcif1: mmc@ee220000 { |
Magnus Damm | 063e8560 | 2013-11-20 09:05:53 +0900 | [diff] [blame] | 249 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 250 | reg = <0 0xee220000 0 0x80>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 251 | interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 252 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 253 | reg-io-width = <4>; |
| 254 | status = "disabled"; |
| 255 | }; |
| 256 | |
Laurent Pinchart | 9694c77 | 2013-05-09 15:05:57 +0200 | [diff] [blame] | 257 | pfc: pfc@e6060000 { |
| 258 | compatible = "renesas,pfc-r8a7790"; |
| 259 | reg = <0 0xe6060000 0 0x250>; |
| 260 | }; |
Olof Johansson | 55689bf | 2013-08-14 00:24:05 -0700 | [diff] [blame] | 261 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 262 | sdhi0: sd@ee100000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 263 | compatible = "renesas,sdhi-r8a7790"; |
Ben Dooks | d721a15 | 2013-12-16 12:38:48 +0000 | [diff] [blame] | 264 | reg = <0 0xee100000 0 0x200>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 265 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 266 | clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 267 | cap-sd-highspeed; |
| 268 | status = "disabled"; |
| 269 | }; |
| 270 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 271 | sdhi1: sd@ee120000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 272 | compatible = "renesas,sdhi-r8a7790"; |
Ben Dooks | d721a15 | 2013-12-16 12:38:48 +0000 | [diff] [blame] | 273 | reg = <0 0xee120000 0 0x200>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 274 | interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 275 | clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 276 | cap-sd-highspeed; |
| 277 | status = "disabled"; |
| 278 | }; |
| 279 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 280 | sdhi2: sd@ee140000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 281 | compatible = "renesas,sdhi-r8a7790"; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 282 | reg = <0 0xee140000 0 0x100>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 283 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 284 | clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 285 | cap-sd-highspeed; |
| 286 | status = "disabled"; |
| 287 | }; |
| 288 | |
Kuninori Morimoto | b718aa4 | 2013-10-21 19:36:13 -0700 | [diff] [blame] | 289 | sdhi3: sd@ee160000 { |
Guennadi Liakhovetski | df1d058 | 2013-08-29 17:14:49 +0200 | [diff] [blame] | 290 | compatible = "renesas,sdhi-r8a7790"; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 291 | reg = <0 0xee160000 0 0x100>; |
Laurent Pinchart | 5f75e73 | 2013-11-19 03:18:25 +0100 | [diff] [blame] | 292 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 72197ca | 2013-12-11 15:05:15 +0100 | [diff] [blame] | 293 | clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; |
Guennadi Liakhovetski | 8c9b1aa | 2013-07-08 17:54:46 +0200 | [diff] [blame] | 294 | cap-sd-highspeed; |
| 295 | status = "disabled"; |
| 296 | }; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 297 | |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 298 | scifa0: serial@e6c40000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 299 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 300 | reg = <0 0xe6c40000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 301 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 302 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; |
| 303 | clock-names = "sci_ick"; |
| 304 | status = "disabled"; |
| 305 | }; |
| 306 | |
| 307 | scifa1: serial@e6c50000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 308 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 309 | reg = <0 0xe6c50000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 310 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 311 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; |
| 312 | clock-names = "sci_ick"; |
| 313 | status = "disabled"; |
| 314 | }; |
| 315 | |
| 316 | scifa2: serial@e6c60000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 317 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 318 | reg = <0 0xe6c60000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 319 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 320 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; |
| 321 | clock-names = "sci_ick"; |
| 322 | status = "disabled"; |
| 323 | }; |
| 324 | |
| 325 | scifb0: serial@e6c20000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 326 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 327 | reg = <0 0xe6c20000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 328 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 329 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; |
| 330 | clock-names = "sci_ick"; |
| 331 | status = "disabled"; |
| 332 | }; |
| 333 | |
| 334 | scifb1: serial@e6c30000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 335 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 336 | reg = <0 0xe6c30000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 337 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 338 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; |
| 339 | clock-names = "sci_ick"; |
| 340 | status = "disabled"; |
| 341 | }; |
| 342 | |
| 343 | scifb2: serial@e6ce0000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 344 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 345 | reg = <0 0xe6ce0000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 346 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 347 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; |
| 348 | clock-names = "sci_ick"; |
| 349 | status = "disabled"; |
| 350 | }; |
| 351 | |
| 352 | scif0: serial@e6e60000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 353 | compatible = "renesas,scif-r8a7790", "renesas,scif"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 354 | reg = <0 0xe6e60000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 355 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 356 | clocks = <&mstp7_clks R8A7790_CLK_SCIF0>; |
| 357 | clock-names = "sci_ick"; |
| 358 | status = "disabled"; |
| 359 | }; |
| 360 | |
| 361 | scif1: serial@e6e68000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 362 | compatible = "renesas,scif-r8a7790", "renesas,scif"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 363 | reg = <0 0xe6e68000 0 64>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 364 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 365 | clocks = <&mstp7_clks R8A7790_CLK_SCIF1>; |
| 366 | clock-names = "sci_ick"; |
| 367 | status = "disabled"; |
| 368 | }; |
| 369 | |
| 370 | hscif0: serial@e62c0000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 371 | compatible = "renesas,hscif-r8a7790", "renesas,hscif"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 372 | reg = <0 0xe62c0000 0 96>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 373 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 374 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>; |
| 375 | clock-names = "sci_ick"; |
| 376 | status = "disabled"; |
| 377 | }; |
| 378 | |
| 379 | hscif1: serial@e62c8000 { |
Laurent Pinchart | 59d2b51 | 2014-01-21 13:48:38 +0100 | [diff] [blame] | 380 | compatible = "renesas,hscif-r8a7790", "renesas,hscif"; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 381 | reg = <0 0xe62c8000 0 96>; |
Laurent Pinchart | 1f4c745 | 2014-01-21 13:48:39 +0100 | [diff] [blame] | 382 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; |
Laurent Pinchart | 597af20 | 2013-10-29 16:23:12 +0100 | [diff] [blame] | 383 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>; |
| 384 | clock-names = "sci_ick"; |
| 385 | status = "disabled"; |
| 386 | }; |
| 387 | |
Sergei Shtylyov | d8913c6 | 2014-02-20 02:20:43 +0300 | [diff] [blame] | 388 | ether: ethernet@ee700000 { |
| 389 | compatible = "renesas,ether-r8a7790"; |
| 390 | reg = <0 0xee700000 0 0x400>; |
| 391 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; |
| 392 | clocks = <&mstp8_clks R8A7790_CLK_ETHER>; |
| 393 | phy-mode = "rmii"; |
| 394 | #address-cells = <1>; |
| 395 | #size-cells = <0>; |
| 396 | status = "disabled"; |
| 397 | }; |
| 398 | |
Valentine Barshak | cde630f | 2014-01-14 21:05:30 +0400 | [diff] [blame] | 399 | sata0: sata@ee300000 { |
| 400 | compatible = "renesas,sata-r8a7790"; |
| 401 | reg = <0 0xee300000 0 0x2000>; |
Valentine Barshak | cde630f | 2014-01-14 21:05:30 +0400 | [diff] [blame] | 402 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; |
| 403 | clocks = <&mstp8_clks R8A7790_CLK_SATA0>; |
| 404 | status = "disabled"; |
| 405 | }; |
| 406 | |
| 407 | sata1: sata@ee500000 { |
| 408 | compatible = "renesas,sata-r8a7790"; |
| 409 | reg = <0 0xee500000 0 0x2000>; |
Valentine Barshak | cde630f | 2014-01-14 21:05:30 +0400 | [diff] [blame] | 410 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
| 411 | clocks = <&mstp8_clks R8A7790_CLK_SATA1>; |
| 412 | status = "disabled"; |
| 413 | }; |
| 414 | |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 415 | clocks { |
| 416 | #address-cells = <2>; |
| 417 | #size-cells = <2>; |
| 418 | ranges; |
| 419 | |
| 420 | /* External root clock */ |
| 421 | extal_clk: extal_clk { |
| 422 | compatible = "fixed-clock"; |
| 423 | #clock-cells = <0>; |
| 424 | /* This value must be overriden by the board. */ |
| 425 | clock-frequency = <0>; |
| 426 | clock-output-names = "extal"; |
| 427 | }; |
| 428 | |
Kuninori Morimoto | c7c2ec3 | 2014-01-13 18:25:39 -0800 | [diff] [blame] | 429 | /* |
| 430 | * The external audio clocks are configured as 0 Hz fixed frequency clocks by |
| 431 | * default. Boards that provide audio clocks should override them. |
| 432 | */ |
| 433 | audio_clk_a: audio_clk_a { |
| 434 | compatible = "fixed-clock"; |
| 435 | #clock-cells = <0>; |
| 436 | clock-frequency = <0>; |
| 437 | clock-output-names = "audio_clk_a"; |
| 438 | }; |
| 439 | audio_clk_b: audio_clk_b { |
| 440 | compatible = "fixed-clock"; |
| 441 | #clock-cells = <0>; |
| 442 | clock-frequency = <0>; |
| 443 | clock-output-names = "audio_clk_b"; |
| 444 | }; |
| 445 | audio_clk_c: audio_clk_c { |
| 446 | compatible = "fixed-clock"; |
| 447 | #clock-cells = <0>; |
| 448 | clock-frequency = <0>; |
| 449 | clock-output-names = "audio_clk_c"; |
| 450 | }; |
| 451 | |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 452 | /* Special CPG clocks */ |
| 453 | cpg_clocks: cpg_clocks@e6150000 { |
| 454 | compatible = "renesas,r8a7790-cpg-clocks", |
| 455 | "renesas,rcar-gen2-cpg-clocks"; |
| 456 | reg = <0 0xe6150000 0 0x1000>; |
| 457 | clocks = <&extal_clk>; |
| 458 | #clock-cells = <1>; |
| 459 | clock-output-names = "main", "pll0", "pll1", "pll3", |
| 460 | "lb", "qspi", "sdh", "sd0", "sd1", |
| 461 | "z"; |
| 462 | }; |
| 463 | |
| 464 | /* Variable factor clocks */ |
| 465 | sd2_clk: sd2_clk@e6150078 { |
| 466 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 467 | reg = <0 0xe6150078 0 4>; |
| 468 | clocks = <&pll1_div2_clk>; |
| 469 | #clock-cells = <0>; |
| 470 | clock-output-names = "sd2"; |
| 471 | }; |
| 472 | sd3_clk: sd3_clk@e615007c { |
| 473 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 474 | reg = <0 0xe615007c 0 4>; |
| 475 | clocks = <&pll1_div2_clk>; |
| 476 | #clock-cells = <0>; |
| 477 | clock-output-names = "sd3"; |
| 478 | }; |
| 479 | mmc0_clk: mmc0_clk@e6150240 { |
| 480 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 481 | reg = <0 0xe6150240 0 4>; |
| 482 | clocks = <&pll1_div2_clk>; |
| 483 | #clock-cells = <0>; |
| 484 | clock-output-names = "mmc0"; |
| 485 | }; |
| 486 | mmc1_clk: mmc1_clk@e6150244 { |
| 487 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 488 | reg = <0 0xe6150244 0 4>; |
| 489 | clocks = <&pll1_div2_clk>; |
| 490 | #clock-cells = <0>; |
| 491 | clock-output-names = "mmc1"; |
| 492 | }; |
| 493 | ssp_clk: ssp_clk@e6150248 { |
| 494 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 495 | reg = <0 0xe6150248 0 4>; |
| 496 | clocks = <&pll1_div2_clk>; |
| 497 | #clock-cells = <0>; |
| 498 | clock-output-names = "ssp"; |
| 499 | }; |
| 500 | ssprs_clk: ssprs_clk@e615024c { |
| 501 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| 502 | reg = <0 0xe615024c 0 4>; |
| 503 | clocks = <&pll1_div2_clk>; |
| 504 | #clock-cells = <0>; |
| 505 | clock-output-names = "ssprs"; |
| 506 | }; |
| 507 | |
| 508 | /* Fixed factor clocks */ |
| 509 | pll1_div2_clk: pll1_div2_clk { |
| 510 | compatible = "fixed-factor-clock"; |
| 511 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 512 | #clock-cells = <0>; |
| 513 | clock-div = <2>; |
| 514 | clock-mult = <1>; |
| 515 | clock-output-names = "pll1_div2"; |
| 516 | }; |
| 517 | z2_clk: z2_clk { |
| 518 | compatible = "fixed-factor-clock"; |
| 519 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 520 | #clock-cells = <0>; |
| 521 | clock-div = <2>; |
| 522 | clock-mult = <1>; |
| 523 | clock-output-names = "z2"; |
| 524 | }; |
| 525 | zg_clk: zg_clk { |
| 526 | compatible = "fixed-factor-clock"; |
| 527 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 528 | #clock-cells = <0>; |
| 529 | clock-div = <3>; |
| 530 | clock-mult = <1>; |
| 531 | clock-output-names = "zg"; |
| 532 | }; |
| 533 | zx_clk: zx_clk { |
| 534 | compatible = "fixed-factor-clock"; |
| 535 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 536 | #clock-cells = <0>; |
| 537 | clock-div = <3>; |
| 538 | clock-mult = <1>; |
| 539 | clock-output-names = "zx"; |
| 540 | }; |
| 541 | zs_clk: zs_clk { |
| 542 | compatible = "fixed-factor-clock"; |
| 543 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 544 | #clock-cells = <0>; |
| 545 | clock-div = <6>; |
| 546 | clock-mult = <1>; |
| 547 | clock-output-names = "zs"; |
| 548 | }; |
| 549 | hp_clk: hp_clk { |
| 550 | compatible = "fixed-factor-clock"; |
| 551 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 552 | #clock-cells = <0>; |
| 553 | clock-div = <12>; |
| 554 | clock-mult = <1>; |
| 555 | clock-output-names = "hp"; |
| 556 | }; |
| 557 | i_clk: i_clk { |
| 558 | compatible = "fixed-factor-clock"; |
| 559 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 560 | #clock-cells = <0>; |
| 561 | clock-div = <2>; |
| 562 | clock-mult = <1>; |
| 563 | clock-output-names = "i"; |
| 564 | }; |
| 565 | b_clk: b_clk { |
| 566 | compatible = "fixed-factor-clock"; |
| 567 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 568 | #clock-cells = <0>; |
| 569 | clock-div = <12>; |
| 570 | clock-mult = <1>; |
| 571 | clock-output-names = "b"; |
| 572 | }; |
| 573 | p_clk: p_clk { |
| 574 | compatible = "fixed-factor-clock"; |
| 575 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 576 | #clock-cells = <0>; |
| 577 | clock-div = <24>; |
| 578 | clock-mult = <1>; |
| 579 | clock-output-names = "p"; |
| 580 | }; |
| 581 | cl_clk: cl_clk { |
| 582 | compatible = "fixed-factor-clock"; |
| 583 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 584 | #clock-cells = <0>; |
| 585 | clock-div = <48>; |
| 586 | clock-mult = <1>; |
| 587 | clock-output-names = "cl"; |
| 588 | }; |
| 589 | m2_clk: m2_clk { |
| 590 | compatible = "fixed-factor-clock"; |
| 591 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 592 | #clock-cells = <0>; |
| 593 | clock-div = <8>; |
| 594 | clock-mult = <1>; |
| 595 | clock-output-names = "m2"; |
| 596 | }; |
| 597 | imp_clk: imp_clk { |
| 598 | compatible = "fixed-factor-clock"; |
| 599 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 600 | #clock-cells = <0>; |
| 601 | clock-div = <4>; |
| 602 | clock-mult = <1>; |
| 603 | clock-output-names = "imp"; |
| 604 | }; |
| 605 | rclk_clk: rclk_clk { |
| 606 | compatible = "fixed-factor-clock"; |
| 607 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 608 | #clock-cells = <0>; |
| 609 | clock-div = <(48 * 1024)>; |
| 610 | clock-mult = <1>; |
| 611 | clock-output-names = "rclk"; |
| 612 | }; |
| 613 | oscclk_clk: oscclk_clk { |
| 614 | compatible = "fixed-factor-clock"; |
| 615 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; |
| 616 | #clock-cells = <0>; |
| 617 | clock-div = <(12 * 1024)>; |
| 618 | clock-mult = <1>; |
| 619 | clock-output-names = "oscclk"; |
| 620 | }; |
| 621 | zb3_clk: zb3_clk { |
| 622 | compatible = "fixed-factor-clock"; |
| 623 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; |
| 624 | #clock-cells = <0>; |
| 625 | clock-div = <4>; |
| 626 | clock-mult = <1>; |
| 627 | clock-output-names = "zb3"; |
| 628 | }; |
| 629 | zb3d2_clk: zb3d2_clk { |
| 630 | compatible = "fixed-factor-clock"; |
| 631 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; |
| 632 | #clock-cells = <0>; |
| 633 | clock-div = <8>; |
| 634 | clock-mult = <1>; |
| 635 | clock-output-names = "zb3d2"; |
| 636 | }; |
| 637 | ddr_clk: ddr_clk { |
| 638 | compatible = "fixed-factor-clock"; |
| 639 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; |
| 640 | #clock-cells = <0>; |
| 641 | clock-div = <8>; |
| 642 | clock-mult = <1>; |
| 643 | clock-output-names = "ddr"; |
| 644 | }; |
| 645 | mp_clk: mp_clk { |
| 646 | compatible = "fixed-factor-clock"; |
| 647 | clocks = <&pll1_div2_clk>; |
| 648 | #clock-cells = <0>; |
| 649 | clock-div = <15>; |
| 650 | clock-mult = <1>; |
| 651 | clock-output-names = "mp"; |
| 652 | }; |
| 653 | cp_clk: cp_clk { |
| 654 | compatible = "fixed-factor-clock"; |
| 655 | clocks = <&extal_clk>; |
| 656 | #clock-cells = <0>; |
| 657 | clock-div = <2>; |
| 658 | clock-mult = <1>; |
| 659 | clock-output-names = "cp"; |
| 660 | }; |
| 661 | |
| 662 | /* Gate clocks */ |
Laurent Pinchart | 9d90951 | 2013-12-19 16:51:01 +0100 | [diff] [blame] | 663 | mstp0_clks: mstp0_clks@e6150130 { |
| 664 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 665 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; |
| 666 | clocks = <&mp_clk>; |
| 667 | #clock-cells = <1>; |
| 668 | renesas,clock-indices = <R8A7790_CLK_MSIOF0>; |
| 669 | clock-output-names = "msiof0"; |
| 670 | }; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 671 | mstp1_clks: mstp1_clks@e6150134 { |
| 672 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 673 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; |
| 674 | clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, |
| 675 | <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, |
| 676 | <&zs_clk>; |
| 677 | #clock-cells = <1>; |
| 678 | renesas,clock-indices = < |
| 679 | R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 |
| 680 | R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 |
| 681 | R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY |
| 682 | >; |
| 683 | clock-output-names = |
| 684 | "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", |
| 685 | "vsp1-du0", "vsp1-rt", "vsp1-sy"; |
| 686 | }; |
| 687 | mstp2_clks: mstp2_clks@e6150138 { |
| 688 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 689 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; |
| 690 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, |
Laurent Pinchart | 9d90951 | 2013-12-19 16:51:01 +0100 | [diff] [blame] | 691 | <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 692 | #clock-cells = <1>; |
| 693 | renesas,clock-indices = < |
| 694 | R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 |
Laurent Pinchart | 9d90951 | 2013-12-19 16:51:01 +0100 | [diff] [blame] | 695 | R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 |
| 696 | R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 697 | >; |
| 698 | clock-output-names = |
Laurent Pinchart | 9d90951 | 2013-12-19 16:51:01 +0100 | [diff] [blame] | 699 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
| 700 | "scifb1", "msiof1", "msiof3", "scifb2"; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 701 | }; |
| 702 | mstp3_clks: mstp3_clks@e615013c { |
| 703 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 704 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; |
| 705 | clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, |
| 706 | <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, |
| 707 | <&mmc0_clk>, <&rclk_clk>; |
| 708 | #clock-cells = <1>; |
| 709 | renesas,clock-indices = < |
| 710 | R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 |
| 711 | R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 |
| 712 | R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1 |
| 713 | >; |
| 714 | clock-output-names = |
| 715 | "tpu0", "mmcif1", "sdhi3", "sdhi2", |
| 716 | "sdhi1", "sdhi0", "mmcif0", "cmt1"; |
| 717 | }; |
| 718 | mstp5_clks: mstp5_clks@e6150144 { |
| 719 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 720 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; |
| 721 | clocks = <&extal_clk>, <&p_clk>; |
| 722 | #clock-cells = <1>; |
| 723 | renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; |
| 724 | clock-output-names = "thermal", "pwm"; |
| 725 | }; |
| 726 | mstp7_clks: mstp7_clks@e615014c { |
| 727 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 728 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; |
| 729 | clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, |
| 730 | <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, |
| 731 | <&zx_clk>; |
| 732 | #clock-cells = <1>; |
| 733 | renesas,clock-indices = < |
| 734 | R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 |
| 735 | R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 |
| 736 | R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 |
| 737 | R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 |
| 738 | >; |
| 739 | clock-output-names = |
| 740 | "ehci", "hsusb", "hscif1", "hscif0", "scif1", |
| 741 | "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; |
| 742 | }; |
| 743 | mstp8_clks: mstp8_clks@e6150990 { |
| 744 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 745 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; |
Laurent Pinchart | bccccc3 | 2014-01-07 09:22:55 +0100 | [diff] [blame] | 746 | clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, |
| 747 | <&zs_clk>, <&zs_clk>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 748 | #clock-cells = <1>; |
Laurent Pinchart | 3f2beaa | 2014-01-07 09:22:53 +0100 | [diff] [blame] | 749 | renesas,clock-indices = < |
| 750 | R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1 |
Laurent Pinchart | bccccc3 | 2014-01-07 09:22:55 +0100 | [diff] [blame] | 751 | R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1 |
| 752 | R8A7790_CLK_SATA0 |
Laurent Pinchart | 3f2beaa | 2014-01-07 09:22:53 +0100 | [diff] [blame] | 753 | >; |
Laurent Pinchart | bccccc3 | 2014-01-07 09:22:55 +0100 | [diff] [blame] | 754 | clock-output-names = |
| 755 | "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0"; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 756 | }; |
| 757 | mstp9_clks: mstp9_clks@e6150994 { |
| 758 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| 759 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; |
Laurent Pinchart | 91b56ca | 2013-12-19 16:51:03 +0100 | [diff] [blame] | 760 | clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, |
Laurent Pinchart | 3672b05 | 2014-04-01 13:02:17 +0200 | [diff] [blame^] | 761 | <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 762 | #clock-cells = <1>; |
| 763 | renesas,clock-indices = < |
Laurent Pinchart | 91b56ca | 2013-12-19 16:51:03 +0100 | [diff] [blame] | 764 | R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD |
| 765 | R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 |
| 766 | R8A7790_CLK_I2C0 |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 767 | >; |
Laurent Pinchart | 91b56ca | 2013-12-19 16:51:03 +0100 | [diff] [blame] | 768 | clock-output-names = |
| 769 | "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0"; |
Laurent Pinchart | 22a1f59 | 2013-12-11 15:05:14 +0100 | [diff] [blame] | 770 | }; |
| 771 | }; |
Geert Uytterhoeven | 7053e13 | 2014-02-10 11:47:29 +0100 | [diff] [blame] | 772 | |
Geert Uytterhoeven | fad6d45 | 2014-02-25 11:30:13 +0100 | [diff] [blame] | 773 | qspi: spi@e6b10000 { |
Geert Uytterhoeven | 7053e13 | 2014-02-10 11:47:29 +0100 | [diff] [blame] | 774 | compatible = "renesas,qspi-r8a7790", "renesas,qspi"; |
| 775 | reg = <0 0xe6b10000 0 0x2c>; |
Geert Uytterhoeven | 7053e13 | 2014-02-10 11:47:29 +0100 | [diff] [blame] | 776 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
| 777 | clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; |
| 778 | num-cs = <1>; |
| 779 | #address-cells = <1>; |
| 780 | #size-cells = <0>; |
| 781 | status = "disabled"; |
| 782 | }; |
Geert Uytterhoeven | ae8a614 | 2014-02-25 11:30:15 +0100 | [diff] [blame] | 783 | |
| 784 | msiof0: spi@e6e20000 { |
| 785 | compatible = "renesas,msiof-r8a7790"; |
| 786 | reg = <0 0xe6e20000 0 0x0064>; |
| 787 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; |
| 788 | clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; |
| 789 | #address-cells = <1>; |
| 790 | #size-cells = <0>; |
| 791 | status = "disabled"; |
| 792 | }; |
| 793 | |
| 794 | msiof1: spi@e6e10000 { |
| 795 | compatible = "renesas,msiof-r8a7790"; |
| 796 | reg = <0 0xe6e10000 0 0x0064>; |
| 797 | interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; |
| 798 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; |
| 799 | #address-cells = <1>; |
| 800 | #size-cells = <0>; |
| 801 | status = "disabled"; |
| 802 | }; |
| 803 | |
| 804 | msiof2: spi@e6e00000 { |
| 805 | compatible = "renesas,msiof-r8a7790"; |
| 806 | reg = <0 0xe6e00000 0 0x0064>; |
| 807 | interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; |
| 808 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; |
| 809 | #address-cells = <1>; |
| 810 | #size-cells = <0>; |
| 811 | status = "disabled"; |
| 812 | }; |
| 813 | |
| 814 | msiof3: spi@e6c90000 { |
| 815 | compatible = "renesas,msiof-r8a7790"; |
| 816 | reg = <0 0xe6c90000 0 0x0064>; |
| 817 | interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; |
| 818 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; |
| 819 | #address-cells = <1>; |
| 820 | #size-cells = <0>; |
| 821 | status = "disabled"; |
| 822 | }; |
Magnus Damm | 0468b2d | 2013-03-28 00:49:34 +0900 | [diff] [blame] | 823 | }; |