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Matthijs Kooijman5b9974b2013-04-22 14:00:19 -07001Platform DesignWare HS OTG USB 2.0 controller
2-----------------------------------------------------
3
4Required properties:
Stephen Warren831eae62013-11-26 18:58:01 -07005- compatible : One of:
6 - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
Kever Yang36750292014-08-08 11:55:56 +08007 - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
8 - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
9 - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
Stephen Warren831eae62013-11-26 18:58:01 -070010 - snps,dwc2: A generic DWC2 USB controller with default parameters.
Matthijs Kooijman5b9974b2013-04-22 14:00:19 -070011- reg : Should contain 1 register range (address and length)
12- interrupts : Should contain 1 interrupt
Matt Porter65b4eb92013-12-19 09:23:03 -050013- clocks: clock provider specifier
14- clock-names: shall be "otg"
15Refer to clk/clock-bindings.txt for generic clock consumer properties
16
17Optional properties:
18- phys: phy provider specifier
Matt Porter9d4bde52014-04-24 13:12:56 -040019- phy-names: shall be "usb2-phy"
Matt Porter65b4eb92013-12-19 09:23:03 -050020Refer to phy/phy-bindings.txt for generic phy consumer properties
Matthijs Kooijman5b9974b2013-04-22 14:00:19 -070021
22Example:
23
24 usb@101c0000 {
25 compatible = "ralink,rt3050-usb, snps,dwc2";
26 reg = <0x101c0000 40000>;
27 interrupts = <18>;
Matt Porter65b4eb92013-12-19 09:23:03 -050028 clocks = <&usb_otg_ahb_clk>;
29 clock-names = "otg";
30 phys = <&usbphy>;
31 phy-names = "usb2-phy";
Matthijs Kooijman5b9974b2013-04-22 14:00:19 -070032 };