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gerrit-public.fairphone.software / kernel / msm-4.19 / 370c3bd05cf02afabea9cd3f2de66202d6b516dc / . / arch / powerpc / boot / dts / lite5200.dts
blob: de30b3f9eb264b60582a9836c873dd2a555c2d5d [file] [log] [blame]
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]1/*
2 * Lite5200 board Device Tree Source
3 *
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]4 * Copyright 2006-2007 Secret Lab Technologies Ltd.
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]5 * Grant Likely <grant.likely@secretlab.ca>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]13/dts-v1/;
14
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]15/ {
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]16 model = "fsl,lite5200";
Marian Balakowicz5b5820d2007-11-15 22:40:21 +1100[diff] [blame]17 compatible = "fsl,lite5200";
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]18 #address-cells = <1>;
19 #size-cells = <1>;
Grant Likelyb8842452009-02-03 12:30:26 -0700[diff] [blame]20 interrupt-parent = <&mpc5200_pic>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]21
22 cpus {
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 PowerPC,5200@0 {
27 device_type = "cpu";
28 reg = <0>;
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]29 d-cache-line-size = <32>;
30 i-cache-line-size = <32>;
31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]33 timebase-frequency = <0>; // from bootloader
34 bus-frequency = <0>; // from bootloader
35 clock-frequency = <0>; // from bootloader
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]36 };
37 };
38
39 memory {
40 device_type = "memory";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]41 reg = <0x00000000 0x04000000>; // 64MB
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]42 };
43
44 soc5200@f0000000 {
Paul Gortmaker58a5be32008-01-26 07:33:20 +1100[diff] [blame]45 #address-cells = <1>;
46 #size-cells = <1>;
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]47 compatible = "fsl,mpc5200-immr";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]48 ranges = <0 0xf0000000 0x0000c000>;
49 reg = <0xf0000000 0x00000100>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]50 bus-frequency = <0>; // from bootloader
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]51 system-frequency = <0>; // from bootloader
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]52
53 cdm@200 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]54 compatible = "fsl,mpc5200-cdm";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]55 reg = <0x200 0x38>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]56 };
57
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]58 mpc5200_pic: interrupt-controller@500 {
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]59 // 5200 interrupts are encoded into two levels;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]60 interrupt-controller;
61 #interrupt-cells = <3>;
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]62 compatible = "fsl,mpc5200-pic";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]63 reg = <0x500 0x80>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]64 };
65
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]66 timer@600 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +1000[diff] [blame]67 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]68 reg = <0x600 0x10>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]69 interrupts = <1 9 0>;
Marian Balakowiczd24bc312007-10-19 04:44:24 +1000[diff] [blame]70 fsl,has-wdt;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]71 };
72
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]73 timer@610 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +1000[diff] [blame]74 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]77 };
78
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]79 timer@620 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +1000[diff] [blame]80 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]81 reg = <0x620 0x10>;
82 interrupts = <1 11 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]83 };
84
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]85 timer@630 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +1000[diff] [blame]86 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]87 reg = <0x630 0x10>;
88 interrupts = <1 12 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]89 };
90
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]91 timer@640 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +1000[diff] [blame]92 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]93 reg = <0x640 0x10>;
94 interrupts = <1 13 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]95 };
96
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]97 timer@650 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +1000[diff] [blame]98 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]99 reg = <0x650 0x10>;
100 interrupts = <1 14 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]101 };
102
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]103 timer@660 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +1000[diff] [blame]104 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]105 reg = <0x660 0x10>;
106 interrupts = <1 15 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]107 };
108
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]109 timer@670 { // General Purpose Timer
Marian Balakowiczd24bc312007-10-19 04:44:24 +1000[diff] [blame]110 compatible = "fsl,mpc5200-gpt";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]111 reg = <0x670 0x10>;
112 interrupts = <1 16 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]113 };
114
115 rtc@800 { // Real time clock
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]116 compatible = "fsl,mpc5200-rtc";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]117 reg = <0x800 0x100>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]118 interrupts = <1 5 0 1 6 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]119 };
120
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]121 can@900 {
122 compatible = "fsl,mpc5200-mscan";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]123 interrupts = <2 17 0>;
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]124 reg = <0x900 0x80>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]125 };
126
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]127 can@980 {
128 compatible = "fsl,mpc5200-mscan";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]129 interrupts = <2 18 0>;
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]130 reg = <0x980 0x80>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]131 };
132
133 gpio@b00 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]134 compatible = "fsl,mpc5200-gpio";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]135 reg = <0xb00 0x40>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]136 interrupts = <1 7 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]137 };
138
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]139 gpio@c00 {
140 compatible = "fsl,mpc5200-gpio-wkup";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]141 reg = <0xc00 0x40>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]142 interrupts = <1 8 0 0 3 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]143 };
144
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]145 spi@f00 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]146 compatible = "fsl,mpc5200-spi";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]147 reg = <0xf00 0x20>;
148 interrupts = <2 13 0 2 14 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]149 };
150
151 usb@1000 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]152 compatible = "fsl,mpc5200-ohci","ohci-be";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]153 reg = <0x1000 0xff>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]154 interrupts = <2 6 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]155 };
156
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]157 dma-controller@1200 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]158 compatible = "fsl,mpc5200-bestcomm";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]159 reg = <0x1200 0x80>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]160 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
161 3 4 0 3 5 0 3 6 0 3 7 0
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]162 3 8 0 3 9 0 3 10 0 3 11 0
163 3 12 0 3 13 0 3 14 0 3 15 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]164 };
165
166 xlb@1f00 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]167 compatible = "fsl,mpc5200-xlb";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]168 reg = <0x1f00 0x100>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]169 };
170
171 serial@2000 { // PSC1
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]172 compatible = "fsl,mpc5200-psc-uart";
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]173 cell-index = <0>;
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]174 reg = <0x2000 0x100>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]175 interrupts = <2 1 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]176 };
177
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]178 // PSC2 in ac97 mode example
179 //ac97@2200 { // PSC2
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]180 // compatible = "fsl,mpc5200-psc-ac97";
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]181 // cell-index = <1>;
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]182 // reg = <0x2200 0x100>;
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]183 // interrupts = <2 2 0>;
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]184 //};
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]185
186 // PSC3 in CODEC mode example
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]187 //i2s@2400 { // PSC3
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]188 // compatible = "fsl,mpc5200-psc-i2s";
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]189 // cell-index = <2>;
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]190 // reg = <0x2400 0x100>;
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]191 // interrupts = <2 3 0>;
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]192 //};
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]193
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]194 // PSC4 in uart mode example
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]195 //serial@2600 { // PSC4
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]196 // compatible = "fsl,mpc5200-psc-uart";
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]197 // cell-index = <3>;
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]198 // reg = <0x2600 0x100>;
199 // interrupts = <2 11 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]200 //};
201
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]202 // PSC5 in uart mode example
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]203 //serial@2800 { // PSC5
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]204 // compatible = "fsl,mpc5200-psc-uart";
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]205 // cell-index = <4>;
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]206 // reg = <0x2800 0x100>;
207 // interrupts = <2 12 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]208 //};
209
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]210 // PSC6 in spi mode example
211 //spi@2c00 { // PSC6
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]212 // compatible = "fsl,mpc5200-psc-spi";
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]213 // cell-index = <5>;
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]214 // reg = <0x2c00 0x100>;
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]215 // interrupts = <2 4 0>;
Grant Likely05cbbc62007-02-12 13:36:54 -0700[diff] [blame]216 //};
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]217
218 ethernet@3000 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]219 compatible = "fsl,mpc5200-fec";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]220 reg = <0x3000 0x400>;
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]221 local-mac-address = [ 00 00 00 00 00 00 ];
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]222 interrupts = <2 5 0>;
René Bürgel8d813942008-04-03 19:58:37 +1100[diff] [blame]223 phy-handle = <&phy0>;
224 };
225
226 mdio@3000 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "fsl,mpc5200-mdio";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]230 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
René Bürgel8d813942008-04-03 19:58:37 +1100[diff] [blame]231 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
René Bürgel8d813942008-04-03 19:58:37 +1100[diff] [blame]232
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]233 phy0: ethernet-phy@1 {
René Bürgel8d813942008-04-03 19:58:37 +1100[diff] [blame]234 reg = <1>;
235 };
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]236 };
237
238 ata@3a00 {
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]239 compatible = "fsl,mpc5200-ata";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]240 reg = <0x3a00 0x100>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]241 interrupts = <2 7 0>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]242 };
243
244 i2c@3d00 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]245 #address-cells = <1>;
246 #size-cells = <0>;
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]247 compatible = "fsl,mpc5200-i2c","fsl-i2c";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]248 reg = <0x3d00 0x40>;
249 interrupts = <2 15 0>;
Domen Puncer5cae84c2007-05-07 01:38:49 +1000[diff] [blame]250 fsl5200-clocking;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]251 };
252
253 i2c@3d40 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]254 #address-cells = <1>;
255 #size-cells = <0>;
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]256 compatible = "fsl,mpc5200-i2c","fsl-i2c";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]257 reg = <0x3d40 0x40>;
258 interrupts = <2 16 0>;
Domen Puncer5cae84c2007-05-07 01:38:49 +1000[diff] [blame]259 fsl5200-clocking;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]260 };
261 sram@8000 {
Grant Likelyb8842452009-02-03 12:30:26 -0700[diff] [blame]262 compatible = "fsl,mpc5200-sram";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]263 reg = <0x8000 0x4000>;
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]264 };
265 };
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]266
267 pci@f0000d00 {
268 #interrupt-cells = <1>;
269 #size-cells = <2>;
270 #address-cells = <3>;
271 device_type = "pci";
Grant Likely24ce6bc2008-01-24 22:25:31 -0700[diff] [blame]272 compatible = "fsl,mpc5200-pci";
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]273 reg = <0xf0000d00 0x100>;
274 interrupt-map-mask = <0xf800 0 0 7>;
275 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
276 0xc000 0 0 2 &mpc5200_pic 0 0 3
277 0xc000 0 0 3 &mpc5200_pic 0 0 3
278 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]279 clock-frequency = <0>; // From boot loader
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]280 interrupts = <2 8 0 2 9 0 2 10 0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]281 bus-range = <0 0>;
Grant Likelya2884f32008-04-29 07:19:07 -0600[diff] [blame]282 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
283 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
284 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]285 };
Grant Likelyc6d4d652006-11-27 14:16:29 -0700[diff] [blame]286};