Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2012 Linaro Ltd. |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
| 13 | #include <linux/clk.h> |
Shawn Guo | 3cb7825 | 2013-03-29 13:36:05 +0800 | [diff] [blame^] | 14 | #include <linux/clk/mxs.h> |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 15 | #include <linux/clkdev.h> |
Shawn Guo | 633ef4c | 2013-03-25 14:53:08 +0800 | [diff] [blame] | 16 | #include <linux/clocksource.h> |
Shawn Guo | 44ffb78 | 2012-08-06 22:00:45 +0800 | [diff] [blame] | 17 | #include <linux/can/platform/flexcan.h> |
Shawn Guo | 2c7c2c1 | 2012-07-13 14:15:34 +0800 | [diff] [blame] | 18 | #include <linux/delay.h> |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 19 | #include <linux/err.h> |
Shawn Guo | 2c7c2c1 | 2012-07-13 14:15:34 +0800 | [diff] [blame] | 20 | #include <linux/gpio.h> |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 21 | #include <linux/init.h> |
Shawn Guo | 6a8e95b | 2013-03-25 21:34:51 +0800 | [diff] [blame] | 22 | #include <linux/irqchip.h> |
| 23 | #include <linux/irqchip/mxs.h> |
Shawn Guo | 3143bbb | 2012-07-07 23:12:03 +0800 | [diff] [blame] | 24 | #include <linux/micrel_phy.h> |
Shawn Guo | ab2815c | 2012-06-25 21:21:46 +0800 | [diff] [blame] | 25 | #include <linux/mxsfb.h> |
Shawn Guo | 974a9af | 2013-03-29 09:45:31 +0800 | [diff] [blame] | 26 | #include <linux/of_address.h> |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 27 | #include <linux/of_platform.h> |
Shawn Guo | 3143bbb | 2012-07-07 23:12:03 +0800 | [diff] [blame] | 28 | #include <linux/phy.h> |
Shawn Guo | 2c7c2c1 | 2012-07-13 14:15:34 +0800 | [diff] [blame] | 29 | #include <linux/pinctrl/consumer.h> |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 30 | #include <asm/mach/arch.h> |
Shawn Guo | 1f62956 | 2013-03-29 13:07:34 +0800 | [diff] [blame] | 31 | #include <asm/mach/map.h> |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 32 | #include <asm/mach/time.h> |
Shawn Guo | 974a9af | 2013-03-29 09:45:31 +0800 | [diff] [blame] | 33 | #include <asm/system_misc.h> |
Dong Aisheng | e317317 | 2012-08-01 11:20:16 +0800 | [diff] [blame] | 34 | #include <mach/digctl.h> |
Shawn Guo | 2c7c2c1 | 2012-07-13 14:15:34 +0800 | [diff] [blame] | 35 | #include <mach/mxs.h> |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 36 | |
Shawn Guo | ab2815c | 2012-06-25 21:21:46 +0800 | [diff] [blame] | 37 | static struct fb_videomode mx23evk_video_modes[] = { |
| 38 | { |
| 39 | .name = "Samsung-LMS430HF02", |
| 40 | .refresh = 60, |
| 41 | .xres = 480, |
| 42 | .yres = 272, |
| 43 | .pixclock = 108096, /* picosecond (9.2 MHz) */ |
| 44 | .left_margin = 15, |
| 45 | .right_margin = 8, |
| 46 | .upper_margin = 12, |
| 47 | .lower_margin = 4, |
| 48 | .hsync_len = 1, |
| 49 | .vsync_len = 1, |
Shawn Guo | ab2815c | 2012-06-25 21:21:46 +0800 | [diff] [blame] | 50 | }, |
| 51 | }; |
| 52 | |
| 53 | static struct fb_videomode mx28evk_video_modes[] = { |
| 54 | { |
| 55 | .name = "Seiko-43WVF1G", |
| 56 | .refresh = 60, |
| 57 | .xres = 800, |
| 58 | .yres = 480, |
| 59 | .pixclock = 29851, /* picosecond (33.5 MHz) */ |
| 60 | .left_margin = 89, |
| 61 | .right_margin = 164, |
| 62 | .upper_margin = 23, |
| 63 | .lower_margin = 10, |
| 64 | .hsync_len = 10, |
| 65 | .vsync_len = 10, |
Shawn Guo | ab2815c | 2012-06-25 21:21:46 +0800 | [diff] [blame] | 66 | }, |
| 67 | }; |
| 68 | |
Marek Vasut | 8fa62e1 | 2012-07-07 21:21:38 +0800 | [diff] [blame] | 69 | static struct fb_videomode m28evk_video_modes[] = { |
| 70 | { |
| 71 | .name = "Ampire AM-800480R2TMQW-T01H", |
| 72 | .refresh = 60, |
| 73 | .xres = 800, |
| 74 | .yres = 480, |
| 75 | .pixclock = 30066, /* picosecond (33.26 MHz) */ |
| 76 | .left_margin = 0, |
| 77 | .right_margin = 256, |
| 78 | .upper_margin = 0, |
| 79 | .lower_margin = 45, |
| 80 | .hsync_len = 1, |
| 81 | .vsync_len = 1, |
Marek Vasut | 8fa62e1 | 2012-07-07 21:21:38 +0800 | [diff] [blame] | 82 | }, |
| 83 | }; |
| 84 | |
Lauri Hintsala | d8bb823 | 2012-07-10 10:08:08 +0300 | [diff] [blame] | 85 | static struct fb_videomode apx4devkit_video_modes[] = { |
| 86 | { |
| 87 | .name = "HannStar PJ70112A", |
| 88 | .refresh = 60, |
| 89 | .xres = 800, |
| 90 | .yres = 480, |
| 91 | .pixclock = 33333, /* picosecond (30.00 MHz) */ |
| 92 | .left_margin = 88, |
| 93 | .right_margin = 40, |
| 94 | .upper_margin = 32, |
| 95 | .lower_margin = 13, |
| 96 | .hsync_len = 48, |
| 97 | .vsync_len = 3, |
Marek Vasut | 6a15075 | 2013-03-18 19:24:02 +0100 | [diff] [blame] | 98 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
Lauri Hintsala | d8bb823 | 2012-07-10 10:08:08 +0300 | [diff] [blame] | 99 | }, |
| 100 | }; |
| 101 | |
Gwenhael Goavec-Merou | a4dabca | 2012-11-02 19:01:48 +0100 | [diff] [blame] | 102 | static struct fb_videomode apf28dev_video_modes[] = { |
| 103 | { |
| 104 | .name = "LW700", |
| 105 | .refresh = 60, |
| 106 | .xres = 800, |
| 107 | .yres = 480, |
| 108 | .pixclock = 30303, /* picosecond */ |
| 109 | .left_margin = 96, |
| 110 | .right_margin = 96, /* at least 3 & 1 */ |
| 111 | .upper_margin = 0x14, |
| 112 | .lower_margin = 0x15, |
| 113 | .hsync_len = 64, |
| 114 | .vsync_len = 4, |
Marek Vasut | 6a15075 | 2013-03-18 19:24:02 +0100 | [diff] [blame] | 115 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
Gwenhael Goavec-Merou | a4dabca | 2012-11-02 19:01:48 +0100 | [diff] [blame] | 116 | }, |
| 117 | }; |
| 118 | |
Maxime Ripard | 1fe4274 | 2013-01-25 09:54:07 +0100 | [diff] [blame] | 119 | static struct fb_videomode cfa10049_video_modes[] = { |
| 120 | { |
| 121 | .name = "Himax HX8357-B", |
| 122 | .refresh = 60, |
| 123 | .xres = 320, |
| 124 | .yres = 480, |
| 125 | .pixclock = 108506, /* picosecond (9.216 MHz) */ |
| 126 | .left_margin = 2, |
| 127 | .right_margin = 2, |
| 128 | .upper_margin = 2, |
| 129 | .lower_margin = 2, |
| 130 | .hsync_len = 15, |
| 131 | .vsync_len = 15, |
Maxime Ripard | 1fe4274 | 2013-01-25 09:54:07 +0100 | [diff] [blame] | 132 | }, |
| 133 | }; |
| 134 | |
Shawn Guo | ab2815c | 2012-06-25 21:21:46 +0800 | [diff] [blame] | 135 | static struct mxsfb_platform_data mxsfb_pdata __initdata; |
| 136 | |
Shawn Guo | 44ffb78 | 2012-08-06 22:00:45 +0800 | [diff] [blame] | 137 | /* |
| 138 | * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers |
| 139 | */ |
| 140 | #define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13) |
| 141 | |
| 142 | static int flexcan0_en, flexcan1_en; |
| 143 | |
| 144 | static void mx28evk_flexcan_switch(void) |
| 145 | { |
| 146 | if (flexcan0_en || flexcan1_en) |
| 147 | gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1); |
| 148 | else |
| 149 | gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0); |
| 150 | } |
| 151 | |
| 152 | static void mx28evk_flexcan0_switch(int enable) |
| 153 | { |
| 154 | flexcan0_en = enable; |
| 155 | mx28evk_flexcan_switch(); |
| 156 | } |
| 157 | |
| 158 | static void mx28evk_flexcan1_switch(int enable) |
| 159 | { |
| 160 | flexcan1_en = enable; |
| 161 | mx28evk_flexcan_switch(); |
| 162 | } |
| 163 | |
| 164 | static struct flexcan_platform_data flexcan_pdata[2]; |
| 165 | |
Shawn Guo | ab2815c | 2012-06-25 21:21:46 +0800 | [diff] [blame] | 166 | static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { |
| 167 | OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata), |
| 168 | OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata), |
Shawn Guo | 44ffb78 | 2012-08-06 22:00:45 +0800 | [diff] [blame] | 169 | OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]), |
| 170 | OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]), |
Shawn Guo | ab2815c | 2012-06-25 21:21:46 +0800 | [diff] [blame] | 171 | { /* sentinel */ } |
| 172 | }; |
| 173 | |
Shawn Guo | 2954ff3 | 2012-05-04 21:33:42 +0800 | [diff] [blame] | 174 | static void __init imx23_timer_init(void) |
| 175 | { |
| 176 | mx23_clocks_init(); |
Shawn Guo | 633ef4c | 2013-03-25 14:53:08 +0800 | [diff] [blame] | 177 | clocksource_of_init(); |
Shawn Guo | 2954ff3 | 2012-05-04 21:33:42 +0800 | [diff] [blame] | 178 | } |
| 179 | |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 180 | static void __init imx28_timer_init(void) |
| 181 | { |
| 182 | mx28_clocks_init(); |
Shawn Guo | 633ef4c | 2013-03-25 14:53:08 +0800 | [diff] [blame] | 183 | clocksource_of_init(); |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 184 | } |
| 185 | |
Shawn Guo | 1bff2d7 | 2013-03-29 13:27:55 +0800 | [diff] [blame] | 186 | #define OCOTP_WORD_OFFSET 0x20 |
| 187 | #define OCOTP_WORD_COUNT 0x20 |
| 188 | |
| 189 | #define BM_OCOTP_CTRL_BUSY (1 << 8) |
| 190 | #define BM_OCOTP_CTRL_ERROR (1 << 9) |
| 191 | #define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12) |
| 192 | |
| 193 | static DEFINE_MUTEX(ocotp_mutex); |
| 194 | static u32 ocotp_words[OCOTP_WORD_COUNT]; |
| 195 | |
| 196 | static const u32 *mxs_get_ocotp(void) |
| 197 | { |
| 198 | struct device_node *np; |
| 199 | void __iomem *ocotp_base; |
| 200 | int timeout = 0x400; |
| 201 | size_t i; |
| 202 | static int once; |
| 203 | |
| 204 | if (once) |
| 205 | return ocotp_words; |
| 206 | |
| 207 | np = of_find_compatible_node(NULL, NULL, "fsl,ocotp"); |
| 208 | ocotp_base = of_iomap(np, 0); |
| 209 | WARN_ON(!ocotp_base); |
| 210 | |
| 211 | mutex_lock(&ocotp_mutex); |
| 212 | |
| 213 | /* |
| 214 | * clk_enable(hbus_clk) for ocotp can be skipped |
| 215 | * as it must be on when system is running. |
| 216 | */ |
| 217 | |
| 218 | /* try to clear ERROR bit */ |
| 219 | __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base); |
| 220 | |
| 221 | /* check both BUSY and ERROR cleared */ |
| 222 | while ((__raw_readl(ocotp_base) & |
| 223 | (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout) |
| 224 | cpu_relax(); |
| 225 | |
| 226 | if (unlikely(!timeout)) |
| 227 | goto error_unlock; |
| 228 | |
| 229 | /* open OCOTP banks for read */ |
| 230 | __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); |
| 231 | |
| 232 | /* approximately wait 32 hclk cycles */ |
| 233 | udelay(1); |
| 234 | |
| 235 | /* poll BUSY bit becoming cleared */ |
| 236 | timeout = 0x400; |
| 237 | while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout) |
| 238 | cpu_relax(); |
| 239 | |
| 240 | if (unlikely(!timeout)) |
| 241 | goto error_unlock; |
| 242 | |
| 243 | for (i = 0; i < OCOTP_WORD_COUNT; i++) |
| 244 | ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET + |
| 245 | i * 0x10); |
| 246 | |
| 247 | /* close banks for power saving */ |
| 248 | __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base); |
| 249 | |
| 250 | once = 1; |
| 251 | |
| 252 | mutex_unlock(&ocotp_mutex); |
| 253 | |
| 254 | return ocotp_words; |
| 255 | |
| 256 | error_unlock: |
| 257 | mutex_unlock(&ocotp_mutex); |
| 258 | pr_err("%s: timeout in reading OCOTP\n", __func__); |
| 259 | return NULL; |
| 260 | } |
| 261 | |
Shawn Guo | 5653acc | 2012-06-19 22:38:14 +0800 | [diff] [blame] | 262 | enum mac_oui { |
| 263 | OUI_FSL, |
| 264 | OUI_DENX, |
Maxime Ripard | 8eec4b3 | 2012-10-07 10:36:28 +0800 | [diff] [blame] | 265 | OUI_CRYSTALFONTZ, |
Shawn Guo | 5653acc | 2012-06-19 22:38:14 +0800 | [diff] [blame] | 266 | }; |
| 267 | |
| 268 | static void __init update_fec_mac_prop(enum mac_oui oui) |
| 269 | { |
| 270 | struct device_node *np, *from = NULL; |
Shawn Guo | fa7c865 | 2012-07-13 14:13:55 +0800 | [diff] [blame] | 271 | struct property *newmac; |
Shawn Guo | 5653acc | 2012-06-19 22:38:14 +0800 | [diff] [blame] | 272 | const u32 *ocotp = mxs_get_ocotp(); |
| 273 | u8 *macaddr; |
| 274 | u32 val; |
| 275 | int i; |
| 276 | |
| 277 | for (i = 0; i < 2; i++) { |
| 278 | np = of_find_compatible_node(from, NULL, "fsl,imx28-fec"); |
| 279 | if (!np) |
| 280 | return; |
Marek Vasut | 16d4770 | 2012-09-25 13:32:18 +0200 | [diff] [blame] | 281 | |
Shawn Guo | 5653acc | 2012-06-19 22:38:14 +0800 | [diff] [blame] | 282 | from = np; |
| 283 | |
Marek Vasut | 16d4770 | 2012-09-25 13:32:18 +0200 | [diff] [blame] | 284 | if (of_get_property(np, "local-mac-address", NULL)) |
| 285 | continue; |
| 286 | |
Shawn Guo | 5653acc | 2012-06-19 22:38:14 +0800 | [diff] [blame] | 287 | newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL); |
| 288 | if (!newmac) |
| 289 | return; |
| 290 | newmac->value = newmac + 1; |
| 291 | newmac->length = 6; |
| 292 | |
| 293 | newmac->name = kstrdup("local-mac-address", GFP_KERNEL); |
| 294 | if (!newmac->name) { |
| 295 | kfree(newmac); |
| 296 | return; |
| 297 | } |
| 298 | |
| 299 | /* |
| 300 | * OCOTP only stores the last 4 octets for each mac address, |
| 301 | * so hard-code OUI here. |
| 302 | */ |
| 303 | macaddr = newmac->value; |
| 304 | switch (oui) { |
| 305 | case OUI_FSL: |
| 306 | macaddr[0] = 0x00; |
| 307 | macaddr[1] = 0x04; |
| 308 | macaddr[2] = 0x9f; |
| 309 | break; |
| 310 | case OUI_DENX: |
| 311 | macaddr[0] = 0xc0; |
| 312 | macaddr[1] = 0xe5; |
| 313 | macaddr[2] = 0x4e; |
| 314 | break; |
Maxime Ripard | 8eec4b3 | 2012-10-07 10:36:28 +0800 | [diff] [blame] | 315 | case OUI_CRYSTALFONTZ: |
| 316 | macaddr[0] = 0x58; |
| 317 | macaddr[1] = 0xb9; |
| 318 | macaddr[2] = 0xe1; |
| 319 | break; |
Shawn Guo | 5653acc | 2012-06-19 22:38:14 +0800 | [diff] [blame] | 320 | } |
| 321 | val = ocotp[i]; |
| 322 | macaddr[3] = (val >> 16) & 0xff; |
| 323 | macaddr[4] = (val >> 8) & 0xff; |
| 324 | macaddr[5] = (val >> 0) & 0xff; |
| 325 | |
Nathan Fontenot | 79d1c71 | 2012-10-02 16:58:46 +0000 | [diff] [blame] | 326 | of_update_property(np, newmac); |
Shawn Guo | 5653acc | 2012-06-19 22:38:14 +0800 | [diff] [blame] | 327 | } |
| 328 | } |
| 329 | |
Shawn Guo | ab2815c | 2012-06-25 21:21:46 +0800 | [diff] [blame] | 330 | static void __init imx23_evk_init(void) |
| 331 | { |
| 332 | mxsfb_pdata.mode_list = mx23evk_video_modes; |
| 333 | mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes); |
| 334 | mxsfb_pdata.default_bpp = 32; |
| 335 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; |
Marek Vasut | 6a15075 | 2013-03-18 19:24:02 +0100 | [diff] [blame] | 336 | mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT | |
| 337 | MXSFB_SYNC_DOTCLK_FAILING_ACT; |
Shawn Guo | ab2815c | 2012-06-25 21:21:46 +0800 | [diff] [blame] | 338 | } |
| 339 | |
Marek Vasut | 8fa62e1 | 2012-07-07 21:21:38 +0800 | [diff] [blame] | 340 | static inline void enable_clk_enet_out(void) |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 341 | { |
Marek Vasut | 8fa62e1 | 2012-07-07 21:21:38 +0800 | [diff] [blame] | 342 | struct clk *clk = clk_get_sys("enet_out", NULL); |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 343 | |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 344 | if (!IS_ERR(clk)) |
| 345 | clk_prepare_enable(clk); |
Marek Vasut | 8fa62e1 | 2012-07-07 21:21:38 +0800 | [diff] [blame] | 346 | } |
Shawn Guo | 5653acc | 2012-06-19 22:38:14 +0800 | [diff] [blame] | 347 | |
Marek Vasut | 8fa62e1 | 2012-07-07 21:21:38 +0800 | [diff] [blame] | 348 | static void __init imx28_evk_init(void) |
| 349 | { |
| 350 | enable_clk_enet_out(); |
Shawn Guo | 5653acc | 2012-06-19 22:38:14 +0800 | [diff] [blame] | 351 | update_fec_mac_prop(OUI_FSL); |
Shawn Guo | ab2815c | 2012-06-25 21:21:46 +0800 | [diff] [blame] | 352 | |
| 353 | mxsfb_pdata.mode_list = mx28evk_video_modes; |
| 354 | mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes); |
| 355 | mxsfb_pdata.default_bpp = 32; |
| 356 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; |
Marek Vasut | 6a15075 | 2013-03-18 19:24:02 +0100 | [diff] [blame] | 357 | mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT | |
| 358 | MXSFB_SYNC_DOTCLK_FAILING_ACT; |
Dong Aisheng | e317317 | 2012-08-01 11:20:16 +0800 | [diff] [blame] | 359 | |
| 360 | mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 361 | } |
| 362 | |
Shawn Guo | 44ffb78 | 2012-08-06 22:00:45 +0800 | [diff] [blame] | 363 | static void __init imx28_evk_post_init(void) |
| 364 | { |
| 365 | if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, |
| 366 | "flexcan-switch")) { |
| 367 | flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch; |
| 368 | flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch; |
| 369 | } |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 370 | } |
| 371 | |
Marek Vasut | 8fa62e1 | 2012-07-07 21:21:38 +0800 | [diff] [blame] | 372 | static void __init m28evk_init(void) |
| 373 | { |
Marek Vasut | 8fa62e1 | 2012-07-07 21:21:38 +0800 | [diff] [blame] | 374 | mxsfb_pdata.mode_list = m28evk_video_modes; |
| 375 | mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes); |
| 376 | mxsfb_pdata.default_bpp = 16; |
| 377 | mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; |
Marek Vasut | 6a15075 | 2013-03-18 19:24:02 +0100 | [diff] [blame] | 378 | mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT; |
Marek Vasut | 8fa62e1 | 2012-07-07 21:21:38 +0800 | [diff] [blame] | 379 | } |
| 380 | |
Marek Vasut | 160d5f2 | 2012-11-18 22:08:29 +0100 | [diff] [blame] | 381 | static void __init sc_sps1_init(void) |
| 382 | { |
| 383 | enable_clk_enet_out(); |
| 384 | } |
| 385 | |
Shawn Guo | 3143bbb | 2012-07-07 23:12:03 +0800 | [diff] [blame] | 386 | static int apx4devkit_phy_fixup(struct phy_device *phy) |
| 387 | { |
| 388 | phy->dev_flags |= MICREL_PHY_50MHZ_CLK; |
| 389 | return 0; |
| 390 | } |
| 391 | |
| 392 | static void __init apx4devkit_init(void) |
| 393 | { |
| 394 | enable_clk_enet_out(); |
| 395 | |
| 396 | if (IS_BUILTIN(CONFIG_PHYLIB)) |
Marek Vasut | 510d573 | 2012-09-23 16:58:50 +0000 | [diff] [blame] | 397 | phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK, |
Shawn Guo | 3143bbb | 2012-07-07 23:12:03 +0800 | [diff] [blame] | 398 | apx4devkit_phy_fixup); |
Lauri Hintsala | d8bb823 | 2012-07-10 10:08:08 +0300 | [diff] [blame] | 399 | |
| 400 | mxsfb_pdata.mode_list = apx4devkit_video_modes; |
| 401 | mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes); |
| 402 | mxsfb_pdata.default_bpp = 32; |
| 403 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; |
Marek Vasut | 6a15075 | 2013-03-18 19:24:02 +0100 | [diff] [blame] | 404 | mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT | |
| 405 | MXSFB_SYNC_DOTCLK_FAILING_ACT; |
Shawn Guo | 3143bbb | 2012-07-07 23:12:03 +0800 | [diff] [blame] | 406 | } |
| 407 | |
Shawn Guo | 2c7c2c1 | 2012-07-13 14:15:34 +0800 | [diff] [blame] | 408 | #define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0) |
| 409 | #define ENET0_MDIO__GPIO_4_1 MXS_GPIO_NR(4, 1) |
| 410 | #define ENET0_RX_EN__GPIO_4_2 MXS_GPIO_NR(4, 2) |
| 411 | #define ENET0_RXD0__GPIO_4_3 MXS_GPIO_NR(4, 3) |
| 412 | #define ENET0_RXD1__GPIO_4_4 MXS_GPIO_NR(4, 4) |
| 413 | #define ENET0_TX_EN__GPIO_4_6 MXS_GPIO_NR(4, 6) |
| 414 | #define ENET0_TXD0__GPIO_4_7 MXS_GPIO_NR(4, 7) |
| 415 | #define ENET0_TXD1__GPIO_4_8 MXS_GPIO_NR(4, 8) |
| 416 | #define ENET_CLK__GPIO_4_16 MXS_GPIO_NR(4, 16) |
| 417 | |
| 418 | #define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29) |
| 419 | #define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13) |
| 420 | #define TX28_FEC_nINT MXS_GPIO_NR(4, 5) |
| 421 | |
| 422 | static const struct gpio tx28_gpios[] __initconst = { |
| 423 | { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" }, |
| 424 | { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" }, |
| 425 | { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" }, |
| 426 | { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" }, |
| 427 | { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" }, |
| 428 | { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" }, |
| 429 | { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" }, |
| 430 | { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" }, |
| 431 | { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" }, |
| 432 | { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" }, |
| 433 | { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" }, |
| 434 | { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" }, |
| 435 | }; |
| 436 | |
| 437 | static void __init tx28_post_init(void) |
| 438 | { |
| 439 | struct device_node *np; |
| 440 | struct platform_device *pdev; |
| 441 | struct pinctrl *pctl; |
| 442 | int ret; |
| 443 | |
| 444 | enable_clk_enet_out(); |
| 445 | |
| 446 | np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec"); |
| 447 | pdev = of_find_device_by_node(np); |
| 448 | if (!pdev) { |
| 449 | pr_err("%s: failed to find fec device\n", __func__); |
| 450 | return; |
| 451 | } |
| 452 | |
| 453 | pctl = pinctrl_get_select(&pdev->dev, "gpio_mode"); |
| 454 | if (IS_ERR(pctl)) { |
| 455 | pr_err("%s: failed to get pinctrl state\n", __func__); |
| 456 | return; |
| 457 | } |
| 458 | |
| 459 | ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios)); |
| 460 | if (ret) { |
| 461 | pr_err("%s: failed to request gpios: %d\n", __func__, ret); |
| 462 | return; |
| 463 | } |
| 464 | |
| 465 | /* Power up fec phy */ |
| 466 | gpio_set_value(TX28_FEC_PHY_POWER, 1); |
| 467 | msleep(26); /* 25ms according to data sheet */ |
| 468 | |
| 469 | /* Mode strap pins */ |
| 470 | gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1); |
| 471 | gpio_set_value(ENET0_RXD0__GPIO_4_3, 1); |
| 472 | gpio_set_value(ENET0_RXD1__GPIO_4_4, 1); |
| 473 | |
| 474 | udelay(100); /* minimum assertion time for nRST */ |
| 475 | |
| 476 | /* Deasserting FEC PHY RESET */ |
| 477 | gpio_set_value(TX28_FEC_PHY_RESET, 1); |
| 478 | |
| 479 | pinctrl_put(pctl); |
| 480 | } |
| 481 | |
Maxime Ripard | 8eec4b3 | 2012-10-07 10:36:28 +0800 | [diff] [blame] | 482 | static void __init cfa10049_init(void) |
| 483 | { |
| 484 | enable_clk_enet_out(); |
| 485 | update_fec_mac_prop(OUI_CRYSTALFONTZ); |
Maxime Ripard | 4a38a85 | 2013-03-05 16:13:35 +0100 | [diff] [blame] | 486 | |
| 487 | mxsfb_pdata.mode_list = cfa10049_video_modes; |
| 488 | mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes); |
| 489 | mxsfb_pdata.default_bpp = 32; |
| 490 | mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; |
Marek Vasut | 6a15075 | 2013-03-18 19:24:02 +0100 | [diff] [blame] | 491 | mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT; |
Maxime Ripard | 8eec4b3 | 2012-10-07 10:36:28 +0800 | [diff] [blame] | 492 | } |
| 493 | |
Maxime Ripard | e0f7d90 | 2013-01-26 13:40:37 +0800 | [diff] [blame] | 494 | static void __init cfa10037_init(void) |
| 495 | { |
| 496 | enable_clk_enet_out(); |
| 497 | update_fec_mac_prop(OUI_CRYSTALFONTZ); |
| 498 | } |
| 499 | |
Julien Boibessot | a957fdc | 2012-10-18 11:50:26 +0200 | [diff] [blame] | 500 | static void __init apf28_init(void) |
| 501 | { |
| 502 | enable_clk_enet_out(); |
Gwenhael Goavec-Merou | a4dabca | 2012-11-02 19:01:48 +0100 | [diff] [blame] | 503 | |
| 504 | mxsfb_pdata.mode_list = apf28dev_video_modes; |
| 505 | mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes); |
| 506 | mxsfb_pdata.default_bpp = 16; |
| 507 | mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT; |
Marek Vasut | 6a15075 | 2013-03-18 19:24:02 +0100 | [diff] [blame] | 508 | mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT | |
| 509 | MXSFB_SYNC_DOTCLK_FAILING_ACT; |
Julien Boibessot | a957fdc | 2012-10-18 11:50:26 +0200 | [diff] [blame] | 510 | } |
| 511 | |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 512 | static void __init mxs_machine_init(void) |
| 513 | { |
| 514 | if (of_machine_is_compatible("fsl,imx28-evk")) |
| 515 | imx28_evk_init(); |
Shawn Guo | ab2815c | 2012-06-25 21:21:46 +0800 | [diff] [blame] | 516 | else if (of_machine_is_compatible("fsl,imx23-evk")) |
| 517 | imx23_evk_init(); |
Marek Vasut | 8fa62e1 | 2012-07-07 21:21:38 +0800 | [diff] [blame] | 518 | else if (of_machine_is_compatible("denx,m28evk")) |
| 519 | m28evk_init(); |
Shawn Guo | 3143bbb | 2012-07-07 23:12:03 +0800 | [diff] [blame] | 520 | else if (of_machine_is_compatible("bluegiga,apx4devkit")) |
| 521 | apx4devkit_init(); |
Maxime Ripard | e0f7d90 | 2013-01-26 13:40:37 +0800 | [diff] [blame] | 522 | else if (of_machine_is_compatible("crystalfontz,cfa10037")) |
| 523 | cfa10037_init(); |
Maxime Ripard | 8eec4b3 | 2012-10-07 10:36:28 +0800 | [diff] [blame] | 524 | else if (of_machine_is_compatible("crystalfontz,cfa10049")) |
| 525 | cfa10049_init(); |
Julien Boibessot | a957fdc | 2012-10-18 11:50:26 +0200 | [diff] [blame] | 526 | else if (of_machine_is_compatible("armadeus,imx28-apf28")) |
| 527 | apf28_init(); |
Marek Vasut | 160d5f2 | 2012-11-18 22:08:29 +0100 | [diff] [blame] | 528 | else if (of_machine_is_compatible("schulercontrol,imx28-sps1")) |
| 529 | sc_sps1_init(); |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 530 | |
| 531 | of_platform_populate(NULL, of_default_bus_match_table, |
Shawn Guo | ab2815c | 2012-06-25 21:21:46 +0800 | [diff] [blame] | 532 | mxs_auxdata_lookup, NULL); |
Shawn Guo | 2c7c2c1 | 2012-07-13 14:15:34 +0800 | [diff] [blame] | 533 | |
| 534 | if (of_machine_is_compatible("karo,tx28")) |
| 535 | tx28_post_init(); |
Shawn Guo | 44ffb78 | 2012-08-06 22:00:45 +0800 | [diff] [blame] | 536 | |
| 537 | if (of_machine_is_compatible("fsl,imx28-evk")) |
| 538 | imx28_evk_post_init(); |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 539 | } |
| 540 | |
Shawn Guo | 974a9af | 2013-03-29 09:45:31 +0800 | [diff] [blame] | 541 | #define MX23_CLKCTRL_RESET_OFFSET 0x120 |
| 542 | #define MX28_CLKCTRL_RESET_OFFSET 0x1e0 |
| 543 | #define MXS_CLKCTRL_RESET_CHIP (1 << 1) |
| 544 | |
| 545 | /* |
| 546 | * Reset the system. It is called by machine_restart(). |
| 547 | */ |
| 548 | static void mxs_restart(char mode, const char *cmd) |
| 549 | { |
| 550 | struct device_node *np; |
| 551 | void __iomem *reset_addr; |
| 552 | |
| 553 | np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl"); |
| 554 | reset_addr = of_iomap(np, 0); |
| 555 | if (!reset_addr) |
| 556 | goto soft; |
| 557 | |
| 558 | if (of_device_is_compatible(np, "fsl,imx23-clkctrl")) |
| 559 | reset_addr += MX23_CLKCTRL_RESET_OFFSET; |
| 560 | else |
| 561 | reset_addr += MX28_CLKCTRL_RESET_OFFSET; |
| 562 | |
| 563 | /* reset the chip */ |
| 564 | __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr); |
| 565 | |
| 566 | pr_err("Failed to assert the chip reset\n"); |
| 567 | |
| 568 | /* Delay to allow the serial port to show the message */ |
| 569 | mdelay(50); |
| 570 | |
| 571 | soft: |
| 572 | /* We'll take a jump through zero as a poor second */ |
| 573 | soft_restart(0); |
| 574 | } |
| 575 | |
Shawn Guo | 2954ff3 | 2012-05-04 21:33:42 +0800 | [diff] [blame] | 576 | static const char *imx23_dt_compat[] __initdata = { |
Shawn Guo | 2954ff3 | 2012-05-04 21:33:42 +0800 | [diff] [blame] | 577 | "fsl,imx23", |
| 578 | NULL, |
| 579 | }; |
| 580 | |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 581 | static const char *imx28_dt_compat[] __initdata = { |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 582 | "fsl,imx28", |
| 583 | NULL, |
| 584 | }; |
| 585 | |
Shawn Guo | 2954ff3 | 2012-05-04 21:33:42 +0800 | [diff] [blame] | 586 | DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)") |
Shawn Guo | 1f62956 | 2013-03-29 13:07:34 +0800 | [diff] [blame] | 587 | .map_io = debug_ll_io_init, |
Shawn Guo | 6a8e95b | 2013-03-25 21:34:51 +0800 | [diff] [blame] | 588 | .init_irq = irqchip_init, |
Shawn Guo | 4e0a1b8 | 2012-08-20 10:14:56 +0800 | [diff] [blame] | 589 | .handle_irq = icoll_handle_irq, |
Stephen Warren | 6bb27d7 | 2012-11-08 12:40:59 -0700 | [diff] [blame] | 590 | .init_time = imx23_timer_init, |
Shawn Guo | 2954ff3 | 2012-05-04 21:33:42 +0800 | [diff] [blame] | 591 | .init_machine = mxs_machine_init, |
| 592 | .dt_compat = imx23_dt_compat, |
| 593 | .restart = mxs_restart, |
| 594 | MACHINE_END |
| 595 | |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 596 | DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)") |
Shawn Guo | 1f62956 | 2013-03-29 13:07:34 +0800 | [diff] [blame] | 597 | .map_io = debug_ll_io_init, |
Shawn Guo | 6a8e95b | 2013-03-25 21:34:51 +0800 | [diff] [blame] | 598 | .init_irq = irqchip_init, |
Shawn Guo | 4e0a1b8 | 2012-08-20 10:14:56 +0800 | [diff] [blame] | 599 | .handle_irq = icoll_handle_irq, |
Stephen Warren | 6bb27d7 | 2012-11-08 12:40:59 -0700 | [diff] [blame] | 600 | .init_time = imx28_timer_init, |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 601 | .init_machine = mxs_machine_init, |
| 602 | .dt_compat = imx28_dt_compat, |
| 603 | .restart = mxs_restart, |
| 604 | MACHINE_END |