Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright(c) 2007 Yuri Tikhonov <yur@emcraft.com> |
| 3 | * Copyright(c) 2009 Intel Corporation |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the Free |
| 7 | * Software Foundation; either version 2 of the License, or (at your option) |
| 8 | * any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program; if not, write to the Free Software Foundation, Inc., 59 |
| 17 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 18 | * |
| 19 | * The full GNU General Public License is included in this distribution in the |
| 20 | * file called COPYING. |
| 21 | */ |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/interrupt.h> |
Paul Gortmaker | 4bb33cc | 2011-05-27 14:41:48 -0400 | [diff] [blame] | 24 | #include <linux/module.h> |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 25 | #include <linux/dma-mapping.h> |
| 26 | #include <linux/raid/pq.h> |
| 27 | #include <linux/async_tx.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 28 | #include <linux/gfp.h> |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 29 | |
| 30 | /** |
Dan Williams | 030b077 | 2009-10-19 18:09:32 -0700 | [diff] [blame] | 31 | * pq_scribble_page - space to hold throwaway P or Q buffer for |
| 32 | * synchronous gen_syndrome |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 33 | */ |
Dan Williams | 030b077 | 2009-10-19 18:09:32 -0700 | [diff] [blame] | 34 | static struct page *pq_scribble_page; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 35 | |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 36 | /* the struct page *blocks[] parameter passed to async_gen_syndrome() |
| 37 | * and async_syndrome_val() contains the 'P' destination address at |
| 38 | * blocks[disks-2] and the 'Q' destination address at blocks[disks-1] |
| 39 | * |
| 40 | * note: these are macros as they are used as lvalues |
| 41 | */ |
| 42 | #define P(b, d) (b[d-2]) |
| 43 | #define Q(b, d) (b[d-1]) |
| 44 | |
| 45 | /** |
| 46 | * do_async_gen_syndrome - asynchronously calculate P and/or Q |
| 47 | */ |
| 48 | static __async_inline struct dma_async_tx_descriptor * |
Dan Williams | 7476bd7 | 2013-10-18 19:35:29 +0200 | [diff] [blame] | 49 | do_async_gen_syndrome(struct dma_chan *chan, |
| 50 | const unsigned char *scfs, int disks, |
| 51 | struct dmaengine_unmap_data *unmap, |
| 52 | enum dma_ctrl_flags dma_flags, |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 53 | struct async_submit_ctl *submit) |
| 54 | { |
| 55 | struct dma_async_tx_descriptor *tx = NULL; |
| 56 | struct dma_device *dma = chan->device; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 57 | enum async_tx_flags flags_orig = submit->flags; |
| 58 | dma_async_tx_callback cb_fn_orig = submit->cb_fn; |
| 59 | dma_async_tx_callback cb_param_orig = submit->cb_param; |
| 60 | int src_cnt = disks - 2; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 61 | unsigned short pq_src_cnt; |
| 62 | dma_addr_t dma_dest[2]; |
| 63 | int src_off = 0; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 64 | |
Dan Williams | 7476bd7 | 2013-10-18 19:35:29 +0200 | [diff] [blame] | 65 | if (submit->flags & ASYNC_TX_FENCE) |
| 66 | dma_flags |= DMA_PREP_FENCE; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 67 | |
| 68 | while (src_cnt > 0) { |
| 69 | submit->flags = flags_orig; |
| 70 | pq_src_cnt = min(src_cnt, dma_maxpq(dma, dma_flags)); |
| 71 | /* if we are submitting additional pqs, leave the chain open, |
| 72 | * clear the callback parameters, and leave the destination |
| 73 | * buffers mapped |
| 74 | */ |
| 75 | if (src_cnt > pq_src_cnt) { |
| 76 | submit->flags &= ~ASYNC_TX_ACK; |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 77 | submit->flags |= ASYNC_TX_FENCE; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 78 | submit->cb_fn = NULL; |
| 79 | submit->cb_param = NULL; |
| 80 | } else { |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 81 | submit->cb_fn = cb_fn_orig; |
| 82 | submit->cb_param = cb_param_orig; |
| 83 | if (cb_fn_orig) |
| 84 | dma_flags |= DMA_PREP_INTERRUPT; |
| 85 | } |
| 86 | |
Dan Williams | 7476bd7 | 2013-10-18 19:35:29 +0200 | [diff] [blame] | 87 | /* Drivers force forward progress in case they can not provide |
| 88 | * a descriptor |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 89 | */ |
| 90 | for (;;) { |
Dan Williams | 7476bd7 | 2013-10-18 19:35:29 +0200 | [diff] [blame] | 91 | dma_dest[0] = unmap->addr[disks - 2]; |
| 92 | dma_dest[1] = unmap->addr[disks - 1]; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 93 | tx = dma->device_prep_dma_pq(chan, dma_dest, |
Dan Williams | 7476bd7 | 2013-10-18 19:35:29 +0200 | [diff] [blame] | 94 | &unmap->addr[src_off], |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 95 | pq_src_cnt, |
Dan Williams | 7476bd7 | 2013-10-18 19:35:29 +0200 | [diff] [blame] | 96 | &scfs[src_off], unmap->len, |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 97 | dma_flags); |
| 98 | if (likely(tx)) |
| 99 | break; |
| 100 | async_tx_quiesce(&submit->depend_tx); |
| 101 | dma_async_issue_pending(chan); |
| 102 | } |
| 103 | |
Dan Williams | 7476bd7 | 2013-10-18 19:35:29 +0200 | [diff] [blame] | 104 | dma_set_unmap(tx, unmap); |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 105 | async_tx_submit(chan, tx, submit); |
| 106 | submit->depend_tx = tx; |
| 107 | |
| 108 | /* drop completed sources */ |
| 109 | src_cnt -= pq_src_cnt; |
| 110 | src_off += pq_src_cnt; |
| 111 | |
| 112 | dma_flags |= DMA_PREP_CONTINUE; |
| 113 | } |
| 114 | |
| 115 | return tx; |
| 116 | } |
| 117 | |
| 118 | /** |
| 119 | * do_sync_gen_syndrome - synchronously calculate a raid6 syndrome |
| 120 | */ |
| 121 | static void |
| 122 | do_sync_gen_syndrome(struct page **blocks, unsigned int offset, int disks, |
| 123 | size_t len, struct async_submit_ctl *submit) |
| 124 | { |
| 125 | void **srcs; |
| 126 | int i; |
Markus Stockhausen | 584acdd | 2014-12-15 12:57:05 +1100 | [diff] [blame] | 127 | int start = -1, stop = disks - 3; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 128 | |
| 129 | if (submit->scribble) |
| 130 | srcs = submit->scribble; |
| 131 | else |
| 132 | srcs = (void **) blocks; |
| 133 | |
| 134 | for (i = 0; i < disks; i++) { |
NeilBrown | 5dd33c9 | 2009-10-16 16:40:25 +1100 | [diff] [blame] | 135 | if (blocks[i] == NULL) { |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 136 | BUG_ON(i > disks - 3); /* P or Q can't be zero */ |
NeilBrown | 5dd33c9 | 2009-10-16 16:40:25 +1100 | [diff] [blame] | 137 | srcs[i] = (void*)raid6_empty_zero_page; |
Markus Stockhausen | 584acdd | 2014-12-15 12:57:05 +1100 | [diff] [blame] | 138 | } else { |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 139 | srcs[i] = page_address(blocks[i]) + offset; |
Markus Stockhausen | 584acdd | 2014-12-15 12:57:05 +1100 | [diff] [blame] | 140 | if (i < disks - 2) { |
| 141 | stop = i; |
| 142 | if (start == -1) |
| 143 | start = i; |
| 144 | } |
| 145 | } |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 146 | } |
Markus Stockhausen | 584acdd | 2014-12-15 12:57:05 +1100 | [diff] [blame] | 147 | if (submit->flags & ASYNC_TX_PQ_XOR_DST) { |
| 148 | BUG_ON(!raid6_call.xor_syndrome); |
| 149 | if (start >= 0) |
| 150 | raid6_call.xor_syndrome(disks, start, stop, len, srcs); |
| 151 | } else |
| 152 | raid6_call.gen_syndrome(disks, len, srcs); |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 153 | async_tx_sync_epilog(submit); |
| 154 | } |
| 155 | |
| 156 | /** |
| 157 | * async_gen_syndrome - asynchronously calculate a raid6 syndrome |
| 158 | * @blocks: source blocks from idx 0..disks-3, P @ disks-2 and Q @ disks-1 |
| 159 | * @offset: common offset into each block (src and dest) to start transaction |
| 160 | * @disks: number of blocks (including missing P or Q, see below) |
| 161 | * @len: length of operation in bytes |
| 162 | * @submit: submission/completion modifiers |
| 163 | * |
| 164 | * General note: This routine assumes a field of GF(2^8) with a |
| 165 | * primitive polynomial of 0x11d and a generator of {02}. |
| 166 | * |
| 167 | * 'disks' note: callers can optionally omit either P or Q (but not |
| 168 | * both) from the calculation by setting blocks[disks-2] or |
| 169 | * blocks[disks-1] to NULL. When P or Q is omitted 'len' must be <= |
| 170 | * PAGE_SIZE as a temporary buffer of this size is used in the |
| 171 | * synchronous path. 'disks' always accounts for both destination |
Dan Williams | 5676470 | 2009-10-19 18:09:32 -0700 | [diff] [blame] | 172 | * buffers. If any source buffers (blocks[i] where i < disks - 2) are |
| 173 | * set to NULL those buffers will be replaced with the raid6_zero_page |
| 174 | * in the synchronous path and omitted in the hardware-asynchronous |
| 175 | * path. |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 176 | */ |
| 177 | struct dma_async_tx_descriptor * |
| 178 | async_gen_syndrome(struct page **blocks, unsigned int offset, int disks, |
| 179 | size_t len, struct async_submit_ctl *submit) |
| 180 | { |
| 181 | int src_cnt = disks - 2; |
| 182 | struct dma_chan *chan = async_tx_find_channel(submit, DMA_PQ, |
| 183 | &P(blocks, disks), 2, |
| 184 | blocks, src_cnt, len); |
| 185 | struct dma_device *device = chan ? chan->device : NULL; |
Dan Williams | 7476bd7 | 2013-10-18 19:35:29 +0200 | [diff] [blame] | 186 | struct dmaengine_unmap_data *unmap = NULL; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 187 | |
| 188 | BUG_ON(disks > 255 || !(P(blocks, disks) || Q(blocks, disks))); |
| 189 | |
Dan Williams | 7476bd7 | 2013-10-18 19:35:29 +0200 | [diff] [blame] | 190 | if (device) |
NeilBrown | b02bab6 | 2016-01-07 11:02:34 +1100 | [diff] [blame] | 191 | unmap = dmaengine_get_unmap_data(device->dev, disks, GFP_NOWAIT); |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 192 | |
Markus Stockhausen | 584acdd | 2014-12-15 12:57:05 +1100 | [diff] [blame] | 193 | /* XORing P/Q is only implemented in software */ |
| 194 | if (unmap && !(submit->flags & ASYNC_TX_PQ_XOR_DST) && |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 195 | (src_cnt <= dma_maxpq(device, 0) || |
Dan Williams | 83544ae | 2009-09-08 17:42:53 -0700 | [diff] [blame] | 196 | dma_maxpq(device, DMA_PREP_CONTINUE) > 0) && |
| 197 | is_dma_pq_aligned(device, offset, 0, len)) { |
Dan Williams | 7476bd7 | 2013-10-18 19:35:29 +0200 | [diff] [blame] | 198 | struct dma_async_tx_descriptor *tx; |
| 199 | enum dma_ctrl_flags dma_flags = 0; |
| 200 | unsigned char coefs[src_cnt]; |
| 201 | int i, j; |
| 202 | |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 203 | /* run the p+q asynchronously */ |
| 204 | pr_debug("%s: (async) disks: %d len: %zu\n", |
| 205 | __func__, disks, len); |
Dan Williams | 7476bd7 | 2013-10-18 19:35:29 +0200 | [diff] [blame] | 206 | |
| 207 | /* convert source addresses being careful to collapse 'empty' |
| 208 | * sources and update the coefficients accordingly |
| 209 | */ |
| 210 | unmap->len = len; |
| 211 | for (i = 0, j = 0; i < src_cnt; i++) { |
| 212 | if (blocks[i] == NULL) |
| 213 | continue; |
| 214 | unmap->addr[j] = dma_map_page(device->dev, blocks[i], offset, |
| 215 | len, DMA_TO_DEVICE); |
| 216 | coefs[j] = raid6_gfexp[i]; |
| 217 | unmap->to_cnt++; |
| 218 | j++; |
| 219 | } |
| 220 | |
| 221 | /* |
| 222 | * DMAs use destinations as sources, |
| 223 | * so use BIDIRECTIONAL mapping |
| 224 | */ |
| 225 | unmap->bidi_cnt++; |
| 226 | if (P(blocks, disks)) |
| 227 | unmap->addr[j++] = dma_map_page(device->dev, P(blocks, disks), |
| 228 | offset, len, DMA_BIDIRECTIONAL); |
| 229 | else { |
| 230 | unmap->addr[j++] = 0; |
| 231 | dma_flags |= DMA_PREP_PQ_DISABLE_P; |
| 232 | } |
| 233 | |
| 234 | unmap->bidi_cnt++; |
| 235 | if (Q(blocks, disks)) |
| 236 | unmap->addr[j++] = dma_map_page(device->dev, Q(blocks, disks), |
| 237 | offset, len, DMA_BIDIRECTIONAL); |
| 238 | else { |
| 239 | unmap->addr[j++] = 0; |
| 240 | dma_flags |= DMA_PREP_PQ_DISABLE_Q; |
| 241 | } |
| 242 | |
| 243 | tx = do_async_gen_syndrome(chan, coefs, j, unmap, dma_flags, submit); |
| 244 | dmaengine_unmap_put(unmap); |
| 245 | return tx; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 246 | } |
| 247 | |
Dan Williams | 7476bd7 | 2013-10-18 19:35:29 +0200 | [diff] [blame] | 248 | dmaengine_unmap_put(unmap); |
| 249 | |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 250 | /* run the pq synchronously */ |
| 251 | pr_debug("%s: (sync) disks: %d len: %zu\n", __func__, disks, len); |
| 252 | |
| 253 | /* wait for any prerequisite operations */ |
| 254 | async_tx_quiesce(&submit->depend_tx); |
| 255 | |
| 256 | if (!P(blocks, disks)) { |
Dan Williams | 030b077 | 2009-10-19 18:09:32 -0700 | [diff] [blame] | 257 | P(blocks, disks) = pq_scribble_page; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 258 | BUG_ON(len + offset > PAGE_SIZE); |
| 259 | } |
| 260 | if (!Q(blocks, disks)) { |
Dan Williams | 030b077 | 2009-10-19 18:09:32 -0700 | [diff] [blame] | 261 | Q(blocks, disks) = pq_scribble_page; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 262 | BUG_ON(len + offset > PAGE_SIZE); |
| 263 | } |
| 264 | do_sync_gen_syndrome(blocks, offset, disks, len, submit); |
| 265 | |
| 266 | return NULL; |
| 267 | } |
| 268 | EXPORT_SYMBOL_GPL(async_gen_syndrome); |
| 269 | |
Dan Williams | 7b3cc2b | 2009-11-19 17:10:37 -0700 | [diff] [blame] | 270 | static inline struct dma_chan * |
| 271 | pq_val_chan(struct async_submit_ctl *submit, struct page **blocks, int disks, size_t len) |
| 272 | { |
| 273 | #ifdef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA |
| 274 | return NULL; |
| 275 | #endif |
| 276 | return async_tx_find_channel(submit, DMA_PQ_VAL, NULL, 0, blocks, |
| 277 | disks, len); |
| 278 | } |
| 279 | |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 280 | /** |
| 281 | * async_syndrome_val - asynchronously validate a raid6 syndrome |
| 282 | * @blocks: source blocks from idx 0..disks-3, P @ disks-2 and Q @ disks-1 |
| 283 | * @offset: common offset into each block (src and dest) to start transaction |
| 284 | * @disks: number of blocks (including missing P or Q, see below) |
| 285 | * @len: length of operation in bytes |
| 286 | * @pqres: on val failure SUM_CHECK_P_RESULT and/or SUM_CHECK_Q_RESULT are set |
| 287 | * @spare: temporary result buffer for the synchronous case |
| 288 | * @submit: submission / completion modifiers |
| 289 | * |
| 290 | * The same notes from async_gen_syndrome apply to the 'blocks', |
| 291 | * and 'disks' parameters of this routine. The synchronous path |
| 292 | * requires a temporary result buffer and submit->scribble to be |
| 293 | * specified. |
| 294 | */ |
| 295 | struct dma_async_tx_descriptor * |
| 296 | async_syndrome_val(struct page **blocks, unsigned int offset, int disks, |
| 297 | size_t len, enum sum_check_flags *pqres, struct page *spare, |
| 298 | struct async_submit_ctl *submit) |
| 299 | { |
Dan Williams | 7b3cc2b | 2009-11-19 17:10:37 -0700 | [diff] [blame] | 300 | struct dma_chan *chan = pq_val_chan(submit, blocks, disks, len); |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 301 | struct dma_device *device = chan ? chan->device : NULL; |
| 302 | struct dma_async_tx_descriptor *tx; |
NeilBrown | b2141e6 | 2009-10-16 16:40:34 +1100 | [diff] [blame] | 303 | unsigned char coefs[disks-2]; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 304 | enum dma_ctrl_flags dma_flags = submit->cb_fn ? DMA_PREP_INTERRUPT : 0; |
Dan Williams | 1786b94 | 2013-10-18 19:35:30 +0200 | [diff] [blame] | 305 | struct dmaengine_unmap_data *unmap = NULL; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 306 | |
| 307 | BUG_ON(disks < 4); |
| 308 | |
Dan Williams | 1786b94 | 2013-10-18 19:35:30 +0200 | [diff] [blame] | 309 | if (device) |
NeilBrown | b02bab6 | 2016-01-07 11:02:34 +1100 | [diff] [blame] | 310 | unmap = dmaengine_get_unmap_data(device->dev, disks, GFP_NOWAIT); |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 311 | |
Dan Williams | 1786b94 | 2013-10-18 19:35:30 +0200 | [diff] [blame] | 312 | if (unmap && disks <= dma_maxpq(device, 0) && |
Dan Williams | 83544ae | 2009-09-08 17:42:53 -0700 | [diff] [blame] | 313 | is_dma_pq_aligned(device, offset, 0, len)) { |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 314 | struct device *dev = device->dev; |
Dan Williams | 1786b94 | 2013-10-18 19:35:30 +0200 | [diff] [blame] | 315 | dma_addr_t pq[2]; |
| 316 | int i, j = 0, src_cnt = 0; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 317 | |
| 318 | pr_debug("%s: (async) disks: %d len: %zu\n", |
| 319 | __func__, disks, len); |
Dan Williams | 1786b94 | 2013-10-18 19:35:30 +0200 | [diff] [blame] | 320 | |
| 321 | unmap->len = len; |
| 322 | for (i = 0; i < disks-2; i++) |
| 323 | if (likely(blocks[i])) { |
| 324 | unmap->addr[j] = dma_map_page(dev, blocks[i], |
| 325 | offset, len, |
| 326 | DMA_TO_DEVICE); |
| 327 | coefs[j] = raid6_gfexp[i]; |
| 328 | unmap->to_cnt++; |
| 329 | src_cnt++; |
| 330 | j++; |
| 331 | } |
| 332 | |
| 333 | if (!P(blocks, disks)) { |
| 334 | pq[0] = 0; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 335 | dma_flags |= DMA_PREP_PQ_DISABLE_P; |
Dan Williams | 1786b94 | 2013-10-18 19:35:30 +0200 | [diff] [blame] | 336 | } else { |
Dan Williams | 5676470 | 2009-10-19 18:09:32 -0700 | [diff] [blame] | 337 | pq[0] = dma_map_page(dev, P(blocks, disks), |
NeilBrown | b2141e6 | 2009-10-16 16:40:34 +1100 | [diff] [blame] | 338 | offset, len, |
| 339 | DMA_TO_DEVICE); |
Dan Williams | 1786b94 | 2013-10-18 19:35:30 +0200 | [diff] [blame] | 340 | unmap->addr[j++] = pq[0]; |
| 341 | unmap->to_cnt++; |
| 342 | } |
| 343 | if (!Q(blocks, disks)) { |
| 344 | pq[1] = 0; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 345 | dma_flags |= DMA_PREP_PQ_DISABLE_Q; |
Dan Williams | 1786b94 | 2013-10-18 19:35:30 +0200 | [diff] [blame] | 346 | } else { |
Dan Williams | 5676470 | 2009-10-19 18:09:32 -0700 | [diff] [blame] | 347 | pq[1] = dma_map_page(dev, Q(blocks, disks), |
NeilBrown | b2141e6 | 2009-10-16 16:40:34 +1100 | [diff] [blame] | 348 | offset, len, |
| 349 | DMA_TO_DEVICE); |
Dan Williams | 1786b94 | 2013-10-18 19:35:30 +0200 | [diff] [blame] | 350 | unmap->addr[j++] = pq[1]; |
| 351 | unmap->to_cnt++; |
| 352 | } |
NeilBrown | b2141e6 | 2009-10-16 16:40:34 +1100 | [diff] [blame] | 353 | |
Dan Williams | 0403e38 | 2009-09-08 17:42:50 -0700 | [diff] [blame] | 354 | if (submit->flags & ASYNC_TX_FENCE) |
| 355 | dma_flags |= DMA_PREP_FENCE; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 356 | for (;;) { |
Dan Williams | 1786b94 | 2013-10-18 19:35:30 +0200 | [diff] [blame] | 357 | tx = device->device_prep_dma_pq_val(chan, pq, |
| 358 | unmap->addr, |
NeilBrown | b2141e6 | 2009-10-16 16:40:34 +1100 | [diff] [blame] | 359 | src_cnt, |
| 360 | coefs, |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 361 | len, pqres, |
| 362 | dma_flags); |
| 363 | if (likely(tx)) |
| 364 | break; |
| 365 | async_tx_quiesce(&submit->depend_tx); |
| 366 | dma_async_issue_pending(chan); |
| 367 | } |
Dan Williams | 1786b94 | 2013-10-18 19:35:30 +0200 | [diff] [blame] | 368 | |
| 369 | dma_set_unmap(tx, unmap); |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 370 | async_tx_submit(chan, tx, submit); |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 371 | } else { |
| 372 | struct page *p_src = P(blocks, disks); |
| 373 | struct page *q_src = Q(blocks, disks); |
| 374 | enum async_tx_flags flags_orig = submit->flags; |
| 375 | dma_async_tx_callback cb_fn_orig = submit->cb_fn; |
| 376 | void *scribble = submit->scribble; |
| 377 | void *cb_param_orig = submit->cb_param; |
| 378 | void *p, *q, *s; |
| 379 | |
| 380 | pr_debug("%s: (sync) disks: %d len: %zu\n", |
| 381 | __func__, disks, len); |
| 382 | |
| 383 | /* caller must provide a temporary result buffer and |
| 384 | * allow the input parameters to be preserved |
| 385 | */ |
| 386 | BUG_ON(!spare || !scribble); |
| 387 | |
| 388 | /* wait for any prerequisite operations */ |
| 389 | async_tx_quiesce(&submit->depend_tx); |
| 390 | |
| 391 | /* recompute p and/or q into the temporary buffer and then |
| 392 | * check to see the result matches the current value |
| 393 | */ |
| 394 | tx = NULL; |
| 395 | *pqres = 0; |
| 396 | if (p_src) { |
| 397 | init_async_submit(submit, ASYNC_TX_XOR_ZERO_DST, NULL, |
| 398 | NULL, NULL, scribble); |
| 399 | tx = async_xor(spare, blocks, offset, disks-2, len, submit); |
| 400 | async_tx_quiesce(&tx); |
| 401 | p = page_address(p_src) + offset; |
| 402 | s = page_address(spare) + offset; |
| 403 | *pqres |= !!memcmp(p, s, len) << SUM_CHECK_P; |
| 404 | } |
| 405 | |
| 406 | if (q_src) { |
| 407 | P(blocks, disks) = NULL; |
| 408 | Q(blocks, disks) = spare; |
| 409 | init_async_submit(submit, 0, NULL, NULL, NULL, scribble); |
| 410 | tx = async_gen_syndrome(blocks, offset, disks, len, submit); |
| 411 | async_tx_quiesce(&tx); |
| 412 | q = page_address(q_src) + offset; |
| 413 | s = page_address(spare) + offset; |
| 414 | *pqres |= !!memcmp(q, s, len) << SUM_CHECK_Q; |
| 415 | } |
| 416 | |
| 417 | /* restore P, Q and submit */ |
| 418 | P(blocks, disks) = p_src; |
| 419 | Q(blocks, disks) = q_src; |
| 420 | |
| 421 | submit->cb_fn = cb_fn_orig; |
| 422 | submit->cb_param = cb_param_orig; |
| 423 | submit->flags = flags_orig; |
| 424 | async_tx_sync_epilog(submit); |
Justin Maggard | c847509 | 2016-10-04 13:17:58 -0700 | [diff] [blame] | 425 | tx = NULL; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 426 | } |
Justin Maggard | c847509 | 2016-10-04 13:17:58 -0700 | [diff] [blame] | 427 | dmaengine_unmap_put(unmap); |
| 428 | |
| 429 | return tx; |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 430 | } |
| 431 | EXPORT_SYMBOL_GPL(async_syndrome_val); |
| 432 | |
| 433 | static int __init async_pq_init(void) |
| 434 | { |
Dan Williams | 030b077 | 2009-10-19 18:09:32 -0700 | [diff] [blame] | 435 | pq_scribble_page = alloc_page(GFP_KERNEL); |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 436 | |
Dan Williams | 030b077 | 2009-10-19 18:09:32 -0700 | [diff] [blame] | 437 | if (pq_scribble_page) |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 438 | return 0; |
| 439 | |
| 440 | pr_err("%s: failed to allocate required spare page\n", __func__); |
| 441 | |
| 442 | return -ENOMEM; |
| 443 | } |
| 444 | |
| 445 | static void __exit async_pq_exit(void) |
| 446 | { |
Joonsoo Kim | 95813b8 | 2016-03-17 14:19:29 -0700 | [diff] [blame] | 447 | __free_page(pq_scribble_page); |
Dan Williams | b2f46fd | 2009-07-14 12:20:36 -0700 | [diff] [blame] | 448 | } |
| 449 | |
| 450 | module_init(async_pq_init); |
| 451 | module_exit(async_pq_exit); |
| 452 | |
| 453 | MODULE_DESCRIPTION("asynchronous raid6 syndrome generation/validation"); |
| 454 | MODULE_LICENSE("GPL"); |