arch/arm/boot/dts/stm32f429.dtsi

/*
 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
 *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>

/ {
	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};
	};

	soc {
		dma-ranges = <0xc0000000 0x0 0x10000000>;

		timer2: timer@40000000 {
			compatible = "st,stm32-timer";
			reg = <0x40000000 0x400>;
			interrupts = <28>;
			clocks = <&rcc 0 128>;
			status = "disabled";
		};

		timer3: timer@40000400 {
			compatible = "st,stm32-timer";
			reg = <0x40000400 0x400>;
			interrupts = <29>;
			clocks = <&rcc 0 129>;
			status = "disabled";
		};

		timer4: timer@40000800 {
			compatible = "st,stm32-timer";
			reg = <0x40000800 0x400>;
			interrupts = <30>;
			clocks = <&rcc 0 130>;
			status = "disabled";
		};

		timer5: timer@40000c00 {
			compatible = "st,stm32-timer";
			reg = <0x40000c00 0x400>;
			interrupts = <50>;
			clocks = <&rcc 0 131>;
		};

		timer6: timer@40001000 {
			compatible = "st,stm32-timer";
			reg = <0x40001000 0x400>;
			interrupts = <54>;
			clocks = <&rcc 0 132>;
			status = "disabled";
		};

		timer7: timer@40001400 {
			compatible = "st,stm32-timer";
			reg = <0x40001400 0x400>;
			interrupts = <55>;
			clocks = <&rcc 0 133>;
			status = "disabled";
		};

		usart2: serial@40004400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004400 0x400>;
			interrupts = <38>;
			clocks =  <&rcc 0 145>;
			status = "disabled";
		};

		usart3: serial@40004800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004800 0x400>;
			interrupts = <39>;
			clocks = <&rcc 0 146>;
			status = "disabled";
		};

		usart4: serial@40004c00 {
			compatible = "st,stm32-uart";
			reg = <0x40004c00 0x400>;
			interrupts = <52>;
			clocks = <&rcc 0 147>;
			status = "disabled";
		};

		usart5: serial@40005000 {
			compatible = "st,stm32-uart";
			reg = <0x40005000 0x400>;
			interrupts = <53>;
			clocks = <&rcc 0 148>;
			status = "disabled";
		};

		usart7: serial@40007800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40007800 0x400>;
			interrupts = <82>;
			clocks = <&rcc 0 158>;
			status = "disabled";
		};

		usart8: serial@40007c00 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40007c00 0x400>;
			interrupts = <83>;
			clocks = <&rcc 0 159>;
			status = "disabled";
		};

		usart1: serial@40011000 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011000 0x400>;
			interrupts = <37>;
			clocks = <&rcc 0 164>;
			status = "disabled";
		};

		usart6: serial@40011400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011400 0x400>;
			interrupts = <71>;
			clocks = <&rcc 0 165>;
			status = "disabled";
		};

		syscfg: system-config@40013800 {
			compatible = "syscon";
			reg = <0x40013800 0x400>;
		};

		pin-controller {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32f429-pinctrl";
			ranges = <0 0x40020000 0x3000>;
			pins-are-numbered;

			gpioa: gpio@40020000 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x0 0x400>;
				clocks = <&rcc 0 0>;
				st,bank-name = "GPIOA";
			};

			gpiob: gpio@40020400 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x400 0x400>;
				clocks = <&rcc 0 1>;
				st,bank-name = "GPIOB";
			};

			gpioc: gpio@40020800 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x800 0x400>;
				clocks = <&rcc 0 2>;
				st,bank-name = "GPIOC";
			};

			gpiod: gpio@40020c00 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0xc00 0x400>;
				clocks = <&rcc 0 3>;
				st,bank-name = "GPIOD";
			};

			gpioe: gpio@40021000 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x1000 0x400>;
				clocks = <&rcc 0 4>;
				st,bank-name = "GPIOE";
			};

			gpiof: gpio@40021400 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x1400 0x400>;
				clocks = <&rcc 0 5>;
				st,bank-name = "GPIOF";
			};

			gpiog: gpio@40021800 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x1800 0x400>;
				clocks = <&rcc 0 6>;
				st,bank-name = "GPIOG";
			};

			gpioh: gpio@40021c00 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x1c00 0x400>;
				clocks = <&rcc 0 7>;
				st,bank-name = "GPIOH";
			};

			gpioi: gpio@40022000 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x2000 0x400>;
				clocks = <&rcc 0 8>;
				st,bank-name = "GPIOI";
			};

			gpioj: gpio@40022400 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x2400 0x400>;
				clocks = <&rcc 0 9>;
				st,bank-name = "GPIOJ";
			};

			gpiok: gpio@40022800 {
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x2800 0x400>;
				clocks = <&rcc 0 10>;
				st,bank-name = "GPIOK";
			};

			usart1_pins_a: usart1@0 {
				pins1 {
					pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
					bias-disable;
					drive-push-pull;
					slew-rate = <0>;
				};
				pins2 {
					pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
					bias-disable;
				};
			};

			usbotg_hs_pins_a: usbotg_hs@0 {
				pins {
					pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
						 <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
						 <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
						 <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
						 <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
						 <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
						 <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
						 <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
						 <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
						 <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
						 <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
						 <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
					bias-disable;
					drive-push-pull;
					slew-rate = <2>;
				};
			};

			ethernet0_mii: mii@0 {
				pins {
					pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
						 <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
						 <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
						 <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
						 <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
						 <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
						 <STM32F429_PA2_FUNC_ETH_MDIO>,
						 <STM32F429_PC1_FUNC_ETH_MDC>,
						 <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
						 <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
						 <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
						 <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
						 <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
						 <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
					slew-rate = <2>;
				};
			};
		};

		rcc: rcc@40023810 {
			#clock-cells = <2>;
			compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
			reg = <0x40023800 0x400>;
			clocks = <&clk_hse>;
		};

		dma1: dma-controller@40026000 {
			compatible = "st,stm32-dma";
			reg = <0x40026000 0x400>;
			interrupts = <11>,
				     <12>,
				     <13>,
				     <14>,
				     <15>,
				     <16>,
				     <17>,
				     <47>;
			clocks = <&rcc 0 21>;
			#dma-cells = <4>;
		};

		dma2: dma-controller@40026400 {
			compatible = "st,stm32-dma";
			reg = <0x40026400 0x400>;
			interrupts = <56>,
				     <57>,
				     <58>,
				     <59>,
				     <60>,
				     <68>,
				     <69>,
				     <70>;
			clocks = <&rcc 0 22>;
			#dma-cells = <4>;
			st,mem2mem;
		};

		ethernet0: dwmac@40028000 {
			compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
			reg = <0x40028000 0x8000>;
			reg-names = "stmmaceth";
			interrupts = <61>, <62>;
			interrupt-names = "macirq", "eth_wake_irq";
			clock-names = "stmmaceth", "tx-clk", "rx-clk";
			clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
			st,syscon = <&syscfg 0x4>;
			snps,pbl = <8>;
			snps,mixed-burst;
			dma-ranges;
			status = "disabled";
		};

		usbotg_hs: usb@40040000 {
			compatible = "snps,dwc2";
			dma-ranges;
			reg = <0x40040000 0x40000>;
			interrupts = <77>;
			clocks = <&rcc 0 29>;
			clock-names = "otg";
			status = "disabled";
		};

		rng: rng@50060800 {
			compatible = "st,stm32-rng";
			reg = <0x50060800 0x400>;
			interrupts = <80>;
			clocks = <&rcc 0 38>;
		};
	};
};

&systick {
	clocks = <&rcc 1 0>;
	status = "okay";
};