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Thomas Abraham43b169d2012-09-07 06:07:19 +09001/*
2 * Exynos specific definitions for Samsung pinctrl and gpiolib driver.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
8 *
9 * This file contains the Exynos specific definitions for the Samsung
10 * pinctrl/gpiolib interface drivers.
11 *
12 * Author: Thomas Abraham <thomas.ab@samsung.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 */
19
Thomas Abraham43b169d2012-09-07 06:07:19 +090020/* External GPIO and wakeup interrupt related definitions */
21#define EXYNOS_GPIO_ECON_OFFSET 0x700
Tomasz Figa7ccbc602013-05-22 16:03:17 +020022#define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
Thomas Abraham43b169d2012-09-07 06:07:19 +090023#define EXYNOS_GPIO_EMASK_OFFSET 0x900
24#define EXYNOS_GPIO_EPEND_OFFSET 0xA00
25#define EXYNOS_WKUP_ECON_OFFSET 0xE00
26#define EXYNOS_WKUP_EMASK_OFFSET 0xF00
27#define EXYNOS_WKUP_EPEND_OFFSET 0xF40
Abhilash Kesavan14c255d2014-10-09 19:24:31 +053028#define EXYNOS7_WKUP_ECON_OFFSET 0x700
29#define EXYNOS7_WKUP_EMASK_OFFSET 0x900
30#define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
Thomas Abraham43b169d2012-09-07 06:07:19 +090031#define EXYNOS_SVC_OFFSET 0xB08
Tomasz Figaee2f5732012-09-21 07:33:48 +090032#define EXYNOS_EINT_FUNC 0xF
Thomas Abraham43b169d2012-09-07 06:07:19 +090033
34/* helpers to access interrupt service register */
35#define EXYNOS_SVC_GROUP_SHIFT 3
36#define EXYNOS_SVC_GROUP_MASK 0x1f
37#define EXYNOS_SVC_NUM_MASK 7
38#define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \
39 EXYNOS_SVC_GROUP_MASK)
40
41/* Exynos specific external interrupt trigger types */
42#define EXYNOS_EINT_LEVEL_LOW 0
43#define EXYNOS_EINT_LEVEL_HIGH 1
44#define EXYNOS_EINT_EDGE_FALLING 2
45#define EXYNOS_EINT_EDGE_RISING 3
46#define EXYNOS_EINT_EDGE_BOTH 4
47#define EXYNOS_EINT_CON_MASK 0xF
48#define EXYNOS_EINT_CON_LEN 4
49
50#define EXYNOS_EINT_MAX_PER_BANK 8
51#define EXYNOS_EINT_NR_WKUP_EINT
52
Tomasz Figa40ba6222012-10-11 10:11:09 +020053#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
Thomas Abraham43b169d2012-09-07 06:07:19 +090054 { \
Tomasz Figa499147c2013-03-18 22:31:52 +010055 .type = &bank_type_off, \
Thomas Abraham43b169d2012-09-07 06:07:19 +090056 .pctl_offset = reg, \
Tomasz Figa40ba6222012-10-11 10:11:09 +020057 .nr_pins = pins, \
Thomas Abraham43b169d2012-09-07 06:07:19 +090058 .eint_type = EINT_TYPE_NONE, \
59 .name = id \
60 }
61
Tomasz Figa1b6056d2012-10-11 10:11:15 +020062#define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \
Thomas Abraham43b169d2012-09-07 06:07:19 +090063 { \
Tomasz Figa499147c2013-03-18 22:31:52 +010064 .type = &bank_type_off, \
Thomas Abraham43b169d2012-09-07 06:07:19 +090065 .pctl_offset = reg, \
Tomasz Figa40ba6222012-10-11 10:11:09 +020066 .nr_pins = pins, \
Thomas Abraham43b169d2012-09-07 06:07:19 +090067 .eint_type = EINT_TYPE_GPIO, \
Tomasz Figa1b6056d2012-10-11 10:11:15 +020068 .eint_offset = offs, \
Thomas Abraham43b169d2012-09-07 06:07:19 +090069 .name = id \
70 }
71
Tomasz Figaa04b07c2012-10-11 10:11:18 +020072#define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \
73 { \
Tomasz Figa499147c2013-03-18 22:31:52 +010074 .type = &bank_type_alive, \
Tomasz Figaa04b07c2012-10-11 10:11:18 +020075 .pctl_offset = reg, \
76 .nr_pins = pins, \
Tomasz Figaa04b07c2012-10-11 10:11:18 +020077 .eint_type = EINT_TYPE_WKUP, \
78 .eint_offset = offs, \
79 .name = id \
80 }
81
Chanwoo Choi8b1bd112016-11-09 17:40:10 +090082#define EXYNOS_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \
83 { \
84 .type = &bank_type_alive, \
85 .pctl_offset = reg, \
86 .nr_pins = pins, \
87 .eint_type = EINT_TYPE_WKUP, \
88 .eint_offset = offs, \
89 .name = id, \
90 .pctl_res_idx = pctl_idx, \
91 } \
92
Chanwoo Choi1259fed2016-12-30 13:14:18 +090093#define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \
94 { \
95 .type = &exynos5433_bank_type_off, \
96 .pctl_offset = reg, \
97 .nr_pins = pins, \
98 .eint_type = EINT_TYPE_GPIO, \
99 .eint_offset = offs, \
100 .name = id \
101 }
102
103#define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \
104 { \
105 .type = &exynos5433_bank_type_alive, \
106 .pctl_offset = reg, \
107 .nr_pins = pins, \
108 .eint_type = EINT_TYPE_WKUP, \
109 .eint_offset = offs, \
110 .name = id \
111 }
112
113#define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \
114 { \
115 .type = &exynos5433_bank_type_alive, \
116 .pctl_offset = reg, \
117 .nr_pins = pins, \
118 .eint_type = EINT_TYPE_WKUP, \
119 .eint_offset = offs, \
120 .name = id, \
121 .pctl_res_idx = pctl_idx, \
122 } \
123
Thomas Abraham43b169d2012-09-07 06:07:19 +0900124/**
Thomas Abraham43b169d2012-09-07 06:07:19 +0900125 * struct exynos_weint_data: irq specific data for all the wakeup interrupts
126 * generated by the external wakeup interrupt controller.
Thomas Abraham43b169d2012-09-07 06:07:19 +0900127 * @irq: interrupt number within the domain.
Tomasz Figaa04b07c2012-10-11 10:11:18 +0200128 * @bank: bank responsible for this interrupt
Thomas Abraham43b169d2012-09-07 06:07:19 +0900129 */
130struct exynos_weint_data {
Tomasz Figaa04b07c2012-10-11 10:11:18 +0200131 unsigned int irq;
132 struct samsung_pin_bank *bank;
133};
134
135/**
136 * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts
137 * generated by the external wakeup interrupt controller.
138 * @nr_banks: count of banks being part of the mux
139 * @banks: array of banks being part of the mux
140 */
141struct exynos_muxed_weint_data {
142 unsigned int nr_banks;
143 struct samsung_pin_bank *banks[];
Thomas Abraham43b169d2012-09-07 06:07:19 +0900144};