Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 2 | * Copyright 2005-2008 Analog Devices Inc. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 3 | * |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 4 | * Licensed under the GPL-2 or later |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _BF533_IRQ_H_ |
| 8 | #define _BF533_IRQ_H_ |
| 9 | |
| 10 | /* |
| 11 | * Interrupt source definitions |
| 12 | Event Source Core Event Name |
| 13 | Core Emulation ** |
| 14 | Events (highest priority) EMU 0 |
| 15 | Reset RST 1 |
| 16 | NMI NMI 2 |
| 17 | Exception EVX 3 |
| 18 | Reserved -- 4 |
| 19 | Hardware Error IVHW 5 |
| 20 | Core Timer IVTMR 6 * |
| 21 | PLL Wakeup Interrupt IVG7 7 |
| 22 | DMA Error (generic) IVG7 8 |
| 23 | PPI Error Interrupt IVG7 9 |
| 24 | SPORT0 Error Interrupt IVG7 10 |
| 25 | SPORT1 Error Interrupt IVG7 11 |
| 26 | SPI Error Interrupt IVG7 12 |
| 27 | UART Error Interrupt IVG7 13 |
| 28 | RTC Interrupt IVG8 14 |
| 29 | DMA0 Interrupt (PPI) IVG8 15 |
| 30 | DMA1 (SPORT0 RX) IVG9 16 |
| 31 | DMA2 (SPORT0 TX) IVG9 17 |
| 32 | DMA3 (SPORT1 RX) IVG9 18 |
| 33 | DMA4 (SPORT1 TX) IVG9 19 |
| 34 | DMA5 (PPI) IVG10 20 |
| 35 | DMA6 (UART RX) IVG10 21 |
| 36 | DMA7 (UART TX) IVG10 22 |
| 37 | Timer0 IVG11 23 |
| 38 | Timer1 IVG11 24 |
| 39 | Timer2 IVG11 25 |
| 40 | PF Interrupt A IVG12 26 |
| 41 | PF Interrupt B IVG12 27 |
| 42 | DMA8/9 Interrupt IVG13 28 |
| 43 | DMA10/11 Interrupt IVG13 29 |
| 44 | Watchdog Timer IVG13 30 |
Michael Hennerich | 56f8771 | 2008-05-10 00:11:59 +0800 | [diff] [blame] | 45 | |
| 46 | Softirq IVG14 31 |
| 47 | System Call -- |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 48 | (lowest priority) IVG15 32 * |
| 49 | */ |
Michael Hennerich | 56f8771 | 2008-05-10 00:11:59 +0800 | [diff] [blame] | 50 | #define SYS_IRQS 31 |
| 51 | #define NR_PERI_INTS 24 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 52 | |
| 53 | /* The ABSTRACT IRQ definitions */ |
| 54 | /** the first seven of the following are fixed, the rest you change if you need to **/ |
| 55 | #define IRQ_EMU 0 /*Emulation */ |
| 56 | #define IRQ_RST 1 /*reset */ |
| 57 | #define IRQ_NMI 2 /*Non Maskable */ |
| 58 | #define IRQ_EVX 3 /*Exception */ |
| 59 | #define IRQ_UNUSED 4 /*- unused interrupt*/ |
| 60 | #define IRQ_HWERR 5 /*Hardware Error */ |
| 61 | #define IRQ_CORETMR 6 /*Core timer */ |
| 62 | |
| 63 | #define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */ |
| 64 | #define IRQ_DMA_ERROR 8 /*DMA Error (general) */ |
| 65 | #define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */ |
| 66 | #define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */ |
| 67 | #define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */ |
| 68 | #define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */ |
Graf Yang | a0dcfb1 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 69 | #define IRQ_UART0_ERROR 13 /*UART Error Interrupt */ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 70 | #define IRQ_RTC 14 /*RTC Interrupt */ |
| 71 | #define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */ |
| 72 | #define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */ |
| 73 | #define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ |
| 74 | #define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ |
| 75 | #define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ |
Graf Yang | a0dcfb1 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 76 | #define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ |
| 77 | #define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */ |
| 78 | #define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */ |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 79 | #define IRQ_TIMER0 23 /*Timer 0 */ |
| 80 | #define IRQ_TIMER1 24 /*Timer 1 */ |
| 81 | #define IRQ_TIMER2 25 /*Timer 2 */ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 82 | #define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */ |
| 83 | #define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */ |
| 84 | #define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */ |
| 85 | #define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */ |
| 86 | #define IRQ_WATCH 30 /*Watch Dog Timer */ |
| 87 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 88 | #define IRQ_PF0 33 |
| 89 | #define IRQ_PF1 34 |
| 90 | #define IRQ_PF2 35 |
| 91 | #define IRQ_PF3 36 |
| 92 | #define IRQ_PF4 37 |
| 93 | #define IRQ_PF5 38 |
| 94 | #define IRQ_PF6 39 |
| 95 | #define IRQ_PF7 40 |
| 96 | #define IRQ_PF8 41 |
| 97 | #define IRQ_PF9 42 |
| 98 | #define IRQ_PF10 43 |
| 99 | #define IRQ_PF11 44 |
| 100 | #define IRQ_PF12 45 |
| 101 | #define IRQ_PF13 46 |
| 102 | #define IRQ_PF14 47 |
| 103 | #define IRQ_PF15 48 |
| 104 | |
Michael Hennerich | 301af29 | 2007-07-24 15:35:53 +0800 | [diff] [blame] | 105 | #define GPIO_IRQ_BASE IRQ_PF0 |
| 106 | |
Michael Hennerich | f3dec78 | 2010-01-19 14:45:38 +0000 | [diff] [blame] | 107 | #define NR_MACH_IRQS (IRQ_PF15 + 1) |
| 108 | #define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 109 | |
| 110 | #define IVG7 7 |
| 111 | #define IVG8 8 |
| 112 | #define IVG9 9 |
| 113 | #define IVG10 10 |
| 114 | #define IVG11 11 |
| 115 | #define IVG12 12 |
| 116 | #define IVG13 13 |
| 117 | #define IVG14 14 |
| 118 | #define IVG15 15 |
| 119 | |
| 120 | /* IAR0 BIT FIELDS*/ |
| 121 | #define RTC_ERROR_POS 28 |
| 122 | #define UART_ERROR_POS 24 |
| 123 | #define SPORT1_ERROR_POS 20 |
| 124 | #define SPI_ERROR_POS 16 |
| 125 | #define SPORT0_ERROR_POS 12 |
| 126 | #define PPI_ERROR_POS 8 |
| 127 | #define DMA_ERROR_POS 4 |
| 128 | #define PLLWAKE_ERROR_POS 0 |
| 129 | |
| 130 | /* IAR1 BIT FIELDS*/ |
| 131 | #define DMA7_UARTTX_POS 28 |
| 132 | #define DMA6_UARTRX_POS 24 |
| 133 | #define DMA5_SPI_POS 20 |
| 134 | #define DMA4_SPORT1TX_POS 16 |
| 135 | #define DMA3_SPORT1RX_POS 12 |
| 136 | #define DMA2_SPORT0TX_POS 8 |
| 137 | #define DMA1_SPORT0RX_POS 4 |
| 138 | #define DMA0_PPI_POS 0 |
| 139 | |
| 140 | /* IAR2 BIT FIELDS*/ |
| 141 | #define WDTIMER_POS 28 |
| 142 | #define MEMDMA1_POS 24 |
| 143 | #define MEMDMA0_POS 20 |
| 144 | #define PFB_POS 16 |
| 145 | #define PFA_POS 12 |
| 146 | #define TIMER2_POS 8 |
| 147 | #define TIMER1_POS 4 |
| 148 | #define TIMER0_POS 0 |
| 149 | |
| 150 | #endif /* _BF533_IRQ_H_ */ |