Linus Walleij | 3bfdebb | 2013-11-13 10:32:20 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2013 Linaro Ltd. |
| 3 | * |
| 4 | * The code contained herein is licensed under the GNU General Public |
| 5 | * License. You may obtain a copy of the GNU General Public License |
| 6 | * Version 2 or later at the following locations: |
| 7 | * |
| 8 | * http://www.opensource.org/licenses/gpl-license.html |
| 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ |
| 11 | |
| 12 | #include "ste-nomadik-pinctrl.dtsi" |
| 13 | |
| 14 | / { |
| 15 | soc { |
| 16 | pinctrl { |
| 17 | /* Settings for all UART default and sleep states */ |
| 18 | uart0 { |
| 19 | uart0_default_mode: uart0_default { |
| 20 | default_mux { |
| 21 | ste,function = "u0"; |
| 22 | ste,pins = "u0_a_1"; |
| 23 | }; |
| 24 | default_cfg1 { |
| 25 | ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ |
| 26 | ste,config = <&in_pu>; |
| 27 | }; |
| 28 | |
| 29 | default_cfg2 { |
| 30 | ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ |
| 31 | ste,config = <&out_hi>; |
| 32 | }; |
| 33 | }; |
| 34 | |
| 35 | uart0_sleep_mode: uart0_sleep { |
| 36 | sleep_cfg1 { |
| 37 | ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ |
| 38 | ste,config = <&slpm_in_wkup_pdis>; |
| 39 | }; |
| 40 | |
| 41 | sleep_cfg2 { |
| 42 | ste,pins = "GPIO1_AJ3"; /* RTS */ |
| 43 | ste,config = <&slpm_out_hi_wkup_pdis>; |
| 44 | }; |
| 45 | |
| 46 | sleep_cfg3 { |
| 47 | ste,pins = "GPIO3_AH3"; /* TXD */ |
| 48 | ste,config = <&slpm_out_wkup_pdis>; |
| 49 | }; |
| 50 | }; |
| 51 | }; |
| 52 | |
| 53 | uart1 { |
| 54 | uart1_default_mode: uart1_default { |
| 55 | default_mux { |
| 56 | ste,function = "u1"; |
| 57 | ste,pins = "u1rxtx_a_1"; |
| 58 | }; |
| 59 | default_cfg1 { |
| 60 | ste,pins = "GPIO4_AH6"; /* RXD */ |
| 61 | ste,config = <&in_pu>; |
| 62 | }; |
| 63 | |
| 64 | default_cfg2 { |
| 65 | ste,pins = "GPIO5_AG6"; /* TXD */ |
| 66 | ste,config = <&out_hi>; |
| 67 | }; |
| 68 | }; |
| 69 | |
| 70 | uart1_sleep_mode: uart1_sleep { |
| 71 | sleep_cfg1 { |
| 72 | ste,pins = "GPIO4_AH6"; /* RXD */ |
| 73 | ste,config = <&slpm_in_wkup_pdis>; |
| 74 | }; |
| 75 | |
| 76 | sleep_cfg2 { |
| 77 | ste,pins = "GPIO5_AG6"; /* TXD */ |
| 78 | ste,config = <&slpm_out_wkup_pdis>; |
| 79 | }; |
| 80 | }; |
| 81 | }; |
| 82 | |
| 83 | uart2 { |
| 84 | uart2_default_mode: uart2_default { |
| 85 | default_mux { |
| 86 | ste,function = "u2"; |
| 87 | ste,pins = "u2rxtx_c_1"; |
| 88 | }; |
| 89 | default_cfg1 { |
| 90 | ste,pins = "GPIO29_W2"; /* RXD */ |
| 91 | ste,config = <&in_pu>; |
| 92 | }; |
| 93 | |
| 94 | default_cfg2 { |
| 95 | ste,pins = "GPIO30_W3"; /* TXD */ |
| 96 | ste,config = <&out_hi>; |
| 97 | }; |
| 98 | }; |
| 99 | |
| 100 | uart2_sleep_mode: uart2_sleep { |
| 101 | sleep_cfg1 { |
| 102 | ste,pins = "GPIO29_W2"; /* RXD */ |
| 103 | ste,config = <&in_wkup_pdis>; |
| 104 | }; |
| 105 | |
| 106 | sleep_cfg2 { |
| 107 | ste,pins = "GPIO30_W3"; /* TXD */ |
| 108 | ste,config = <&out_wkup_pdis>; |
| 109 | }; |
| 110 | }; |
| 111 | }; |
| 112 | }; |
| 113 | }; |
| 114 | }; |