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Alex Deucherd38ceaf2015-04-20 16:55:21 -04001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <drm/drmP.h>
29#include <drm/amdgpu_drm.h>
30#include "amdgpu.h"
31#include "amdgpu_trace.h"
32
33/*
34 * GPUVM
35 * GPUVM is similar to the legacy gart on older asics, however
36 * rather than there being a single global gart table
37 * for the entire GPU, there are multiple VM page tables active
38 * at any given time. The VM page tables can contain a mix
39 * vram pages and system memory pages and system memory pages
40 * can be mapped as snooped (cached system pages) or unsnooped
41 * (uncached system pages).
42 * Each VM has an ID associated with it and there is a page table
43 * associated with each VMID. When execting a command buffer,
44 * the kernel tells the the ring what VMID to use for that command
45 * buffer. VMIDs are allocated dynamically as commands are submitted.
46 * The userspace drivers maintain their own address space and the kernel
47 * sets up their pages tables accordingly when they submit their
48 * command buffers and a VMID is assigned.
49 * Cayman/Trinity support up to 8 active VMs at any given time;
50 * SI supports 16.
51 */
52
53/**
54 * amdgpu_vm_num_pde - return the number of page directory entries
55 *
56 * @adev: amdgpu_device pointer
57 *
58 * Calculate the number of page directory entries (cayman+).
59 */
60static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
61{
62 return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;
63}
64
65/**
66 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
67 *
68 * @adev: amdgpu_device pointer
69 *
70 * Calculate the size of the page directory in bytes (cayman+).
71 */
72static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
73{
74 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);
75}
76
77/**
78 * amdgpu_vm_get_bos - add the vm BOs to a validation list
79 *
80 * @vm: vm providing the BOs
Christian König3c0eea62015-12-11 14:39:05 +010081 * @validated: head of validation list
82 * @duplicates: head of duplicates list
Alex Deucherd38ceaf2015-04-20 16:55:21 -040083 *
84 * Add the page directory to the list of BOs to
85 * validate for command submission (cayman+).
86 */
87struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
Christian König3c0eea62015-12-11 14:39:05 +010088 struct amdgpu_vm *vm,
89 struct list_head *validated,
90 struct list_head *duplicates)
Alex Deucherd38ceaf2015-04-20 16:55:21 -040091{
92 struct amdgpu_bo_list_entry *list;
93 unsigned i, idx;
94
95 list = drm_malloc_ab(vm->max_pde_used + 2,
96 sizeof(struct amdgpu_bo_list_entry));
monk.liu3d5a08c2015-05-26 10:22:41 +080097 if (!list) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -040098 return NULL;
monk.liu3d5a08c2015-05-26 10:22:41 +080099 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400100
101 /* add the vm page table to the list */
102 list[0].robj = vm->page_directory;
103 list[0].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
104 list[0].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
105 list[0].priority = 0;
106 list[0].tv.bo = &vm->page_directory->tbo;
107 list[0].tv.shared = true;
Christian König3c0eea62015-12-11 14:39:05 +0100108 list_add(&list[0].tv.head, validated);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400109
110 for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
111 if (!vm->page_tables[i].bo)
112 continue;
113
114 list[idx].robj = vm->page_tables[i].bo;
115 list[idx].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
116 list[idx].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
117 list[idx].priority = 0;
118 list[idx].tv.bo = &list[idx].robj->tbo;
119 list[idx].tv.shared = true;
Christian König3c0eea62015-12-11 14:39:05 +0100120 list_add(&list[idx++].tv.head, duplicates);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400121 }
122
123 return list;
124}
125
126/**
127 * amdgpu_vm_grab_id - allocate the next free VMID
128 *
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400129 * @vm: vm to allocate id for
Christian König7f8a5292015-07-20 16:09:40 +0200130 * @ring: ring we want to submit job to
131 * @sync: sync object where we add dependencies
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400132 *
Christian König7f8a5292015-07-20 16:09:40 +0200133 * Allocate an id for the vm, adding fences to the sync obj as necessary.
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400134 *
Christian König7f8a5292015-07-20 16:09:40 +0200135 * Global mutex must be locked!
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400136 */
Christian König7f8a5292015-07-20 16:09:40 +0200137int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
138 struct amdgpu_sync *sync)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400139{
Christian Königd5283292015-10-22 11:55:58 +0200140 struct fence *best[AMDGPU_MAX_RINGS] = {};
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400141 struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
142 struct amdgpu_device *adev = ring->adev;
143
144 unsigned choices[2] = {};
145 unsigned i;
146
147 /* check if the id is still valid */
Christian König1c16c0a2015-11-14 21:31:40 +0100148 if (vm_id->id) {
149 unsigned id = vm_id->id;
150 long owner;
151
152 owner = atomic_long_read(&adev->vm_manager.ids[id].owner);
153 if (owner == (long)vm) {
154 trace_amdgpu_vm_grab_id(vm_id->id, ring->idx);
155 return 0;
156 }
Christian König39ff8442015-09-28 12:01:20 +0200157 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400158
159 /* we definately need to flush */
160 vm_id->pd_gpu_addr = ~0ll;
161
162 /* skip over VMID 0, since it is the system VM */
163 for (i = 1; i < adev->vm_manager.nvm; ++i) {
Christian König1c16c0a2015-11-14 21:31:40 +0100164 struct fence *fence = adev->vm_manager.ids[i].active;
Christian Königd5283292015-10-22 11:55:58 +0200165 struct amdgpu_ring *fring;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400166
167 if (fence == NULL) {
168 /* found a free one */
169 vm_id->id = i;
170 trace_amdgpu_vm_grab_id(i, ring->idx);
Christian König7f8a5292015-07-20 16:09:40 +0200171 return 0;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400172 }
173
Christian Königd5283292015-10-22 11:55:58 +0200174 fring = amdgpu_ring_from_fence(fence);
175 if (best[fring->idx] == NULL ||
176 fence_is_later(best[fring->idx], fence)) {
177 best[fring->idx] = fence;
178 choices[fring == ring ? 0 : 1] = i;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400179 }
180 }
181
182 for (i = 0; i < 2; ++i) {
183 if (choices[i]) {
Christian Königd5283292015-10-22 11:55:58 +0200184 struct fence *fence;
Christian König7f8a5292015-07-20 16:09:40 +0200185
Christian König1c16c0a2015-11-14 21:31:40 +0100186 fence = adev->vm_manager.ids[choices[i]].active;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400187 vm_id->id = choices[i];
Christian König7f8a5292015-07-20 16:09:40 +0200188
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400189 trace_amdgpu_vm_grab_id(choices[i], ring->idx);
Christian Königd5283292015-10-22 11:55:58 +0200190 return amdgpu_sync_fence(ring->adev, sync, fence);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400191 }
192 }
193
194 /* should never happen */
195 BUG();
Christian König7f8a5292015-07-20 16:09:40 +0200196 return -EINVAL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400197}
198
199/**
200 * amdgpu_vm_flush - hardware flush the vm
201 *
202 * @ring: ring to use for flush
203 * @vm: vm we want to flush
204 * @updates: last vm update that we waited for
205 *
206 * Flush the vm (cayman+).
207 *
208 * Global and local mutex must be locked!
209 */
210void amdgpu_vm_flush(struct amdgpu_ring *ring,
211 struct amdgpu_vm *vm,
Chunming Zhou3c623382015-08-20 18:33:59 +0800212 struct fence *updates)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400213{
214 uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
215 struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
Chunming Zhou3c623382015-08-20 18:33:59 +0800216 struct fence *flushed_updates = vm_id->flushed_updates;
Christian Königb56c2282015-10-29 17:01:19 +0100217 bool is_later;
Chunming Zhou3c623382015-08-20 18:33:59 +0800218
Christian Königb56c2282015-10-29 17:01:19 +0100219 if (!flushed_updates)
220 is_later = true;
221 else if (!updates)
222 is_later = false;
223 else
224 is_later = fence_is_later(updates, flushed_updates);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400225
Christian Königb56c2282015-10-29 17:01:19 +0100226 if (pd_addr != vm_id->pd_gpu_addr || is_later) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400227 trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id);
Christian Königb56c2282015-10-29 17:01:19 +0100228 if (is_later) {
Chunming Zhou3c623382015-08-20 18:33:59 +0800229 vm_id->flushed_updates = fence_get(updates);
230 fence_put(flushed_updates);
231 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400232 vm_id->pd_gpu_addr = pd_addr;
233 amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr);
234 }
235}
236
237/**
238 * amdgpu_vm_fence - remember fence for vm
239 *
240 * @adev: amdgpu_device pointer
241 * @vm: vm we want to fence
242 * @fence: fence to remember
243 *
244 * Fence the vm (cayman+).
245 * Set the fence used to protect page table and id.
246 *
247 * Global and local mutex must be locked!
248 */
249void amdgpu_vm_fence(struct amdgpu_device *adev,
250 struct amdgpu_vm *vm,
Christian König16ae42f2015-11-03 14:53:28 +0100251 struct fence *fence)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400252{
Christian König16ae42f2015-11-03 14:53:28 +0100253 struct amdgpu_ring *ring = amdgpu_ring_from_fence(fence);
254 unsigned vm_id = vm->ids[ring->idx].id;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400255
Christian König1c16c0a2015-11-14 21:31:40 +0100256 fence_put(adev->vm_manager.ids[vm_id].active);
257 adev->vm_manager.ids[vm_id].active = fence_get(fence);
258 atomic_long_set(&adev->vm_manager.ids[vm_id].owner, (long)vm);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400259}
260
261/**
262 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
263 *
264 * @vm: requested vm
265 * @bo: requested buffer object
266 *
267 * Find @bo inside the requested vm (cayman+).
268 * Search inside the @bos vm list for the requested vm
269 * Returns the found bo_va or NULL if none is found
270 *
271 * Object has to be reserved!
272 */
273struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
274 struct amdgpu_bo *bo)
275{
276 struct amdgpu_bo_va *bo_va;
277
278 list_for_each_entry(bo_va, &bo->va, bo_list) {
279 if (bo_va->vm == vm) {
280 return bo_va;
281 }
282 }
283 return NULL;
284}
285
286/**
287 * amdgpu_vm_update_pages - helper to call the right asic function
288 *
289 * @adev: amdgpu_device pointer
290 * @ib: indirect buffer to fill with commands
291 * @pe: addr of the page entry
292 * @addr: dst addr to write into pe
293 * @count: number of page entries to update
294 * @incr: increase next addr by incr bytes
295 * @flags: hw access flags
296 * @gtt_flags: GTT hw access flags
297 *
298 * Traces the parameters and calls the right asic functions
299 * to setup the page table using the DMA.
300 */
301static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
302 struct amdgpu_ib *ib,
303 uint64_t pe, uint64_t addr,
304 unsigned count, uint32_t incr,
305 uint32_t flags, uint32_t gtt_flags)
306{
307 trace_amdgpu_vm_set_page(pe, addr, count, incr, flags);
308
309 if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) {
310 uint64_t src = adev->gart.table_addr + (addr >> 12) * 8;
311 amdgpu_vm_copy_pte(adev, ib, pe, src, count);
312
313 } else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) {
314 amdgpu_vm_write_pte(adev, ib, pe, addr,
315 count, incr, flags);
316
317 } else {
318 amdgpu_vm_set_pte_pde(adev, ib, pe, addr,
319 count, incr, flags);
320 }
321}
322
Junwei Zhang4c7eb912015-09-09 09:05:55 +0800323int amdgpu_vm_free_job(struct amdgpu_job *job)
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800324{
325 int i;
Junwei Zhang4c7eb912015-09-09 09:05:55 +0800326 for (i = 0; i < job->num_ibs; i++)
327 amdgpu_ib_free(job->adev, &job->ibs[i]);
328 kfree(job->ibs);
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800329 return 0;
330}
331
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400332/**
333 * amdgpu_vm_clear_bo - initially clear the page dir/table
334 *
335 * @adev: amdgpu_device pointer
336 * @bo: bo to clear
Chunming Zhouef9f0a82015-11-13 13:43:22 +0800337 *
338 * need to reserve bo first before calling it.
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400339 */
340static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
341 struct amdgpu_bo *bo)
342{
343 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
Chunming Zhou4af9f072015-08-03 12:57:31 +0800344 struct fence *fence = NULL;
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800345 struct amdgpu_ib *ib;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400346 unsigned entries;
347 uint64_t addr;
348 int r;
349
monk.liuca952612015-05-25 14:44:05 +0800350 r = reservation_object_reserve_shared(bo->tbo.resv);
351 if (r)
352 return r;
353
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400354 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
355 if (r)
Chunming Zhouef9f0a82015-11-13 13:43:22 +0800356 goto error;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400357
358 addr = amdgpu_bo_gpu_offset(bo);
359 entries = amdgpu_bo_size(bo) / 8;
360
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800361 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
362 if (!ib)
Chunming Zhouef9f0a82015-11-13 13:43:22 +0800363 goto error;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400364
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800365 r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, ib);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400366 if (r)
367 goto error_free;
368
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800369 ib->length_dw = 0;
370
371 amdgpu_vm_update_pages(adev, ib, addr, 0, entries, 0, 0, 0);
372 amdgpu_vm_pad_ib(adev, ib);
373 WARN_ON(ib->length_dw > 64);
Chunming Zhou4af9f072015-08-03 12:57:31 +0800374 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
375 &amdgpu_vm_free_job,
376 AMDGPU_FENCE_OWNER_VM,
377 &fence);
378 if (!r)
379 amdgpu_bo_fence(bo, fence, true);
Chunming Zhou281b4222015-08-12 12:58:31 +0800380 fence_put(fence);
Chunming Zhouef9f0a82015-11-13 13:43:22 +0800381 if (amdgpu_enable_scheduler)
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800382 return 0;
Chunming Zhouef9f0a82015-11-13 13:43:22 +0800383
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400384error_free:
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800385 amdgpu_ib_free(adev, ib);
386 kfree(ib);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400387
Chunming Zhouef9f0a82015-11-13 13:43:22 +0800388error:
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400389 return r;
390}
391
392/**
393 * amdgpu_vm_map_gart - get the physical address of a gart page
394 *
395 * @adev: amdgpu_device pointer
396 * @addr: the unmapped addr
397 *
398 * Look up the physical address of the page that the pte resolves
399 * to (cayman+).
400 * Returns the physical address of the page.
401 */
402uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr)
403{
404 uint64_t result;
405
406 /* page table offset */
407 result = adev->gart.pages_addr[addr >> PAGE_SHIFT];
408
409 /* in case cpu page size != gpu page size*/
410 result |= addr & (~PAGE_MASK);
411
412 return result;
413}
414
415/**
416 * amdgpu_vm_update_pdes - make sure that page directory is valid
417 *
418 * @adev: amdgpu_device pointer
419 * @vm: requested vm
420 * @start: start of GPU address range
421 * @end: end of GPU address range
422 *
423 * Allocates new page tables if necessary
424 * and updates the page directory (cayman+).
425 * Returns 0 for success, error for failure.
426 *
427 * Global and local mutex must be locked!
428 */
429int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
430 struct amdgpu_vm *vm)
431{
432 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
433 struct amdgpu_bo *pd = vm->page_directory;
434 uint64_t pd_addr = amdgpu_bo_gpu_offset(pd);
435 uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
436 uint64_t last_pde = ~0, last_pt = ~0;
437 unsigned count = 0, pt_idx, ndw;
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800438 struct amdgpu_ib *ib;
Chunming Zhou4af9f072015-08-03 12:57:31 +0800439 struct fence *fence = NULL;
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800440
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400441 int r;
442
443 /* padding, etc. */
444 ndw = 64;
445
446 /* assume the worst case */
447 ndw += vm->max_pde_used * 6;
448
449 /* update too big for an IB */
450 if (ndw > 0xfffff)
451 return -ENOMEM;
452
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800453 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
454 if (!ib)
455 return -ENOMEM;
456
457 r = amdgpu_ib_get(ring, NULL, ndw * 4, ib);
Sudip Mukherjee7a574552015-10-08 19:28:01 +0530458 if (r) {
459 kfree(ib);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400460 return r;
Sudip Mukherjee7a574552015-10-08 19:28:01 +0530461 }
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800462 ib->length_dw = 0;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400463
464 /* walk over the address space and update the page directory */
465 for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
466 struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo;
467 uint64_t pde, pt;
468
469 if (bo == NULL)
470 continue;
471
472 pt = amdgpu_bo_gpu_offset(bo);
473 if (vm->page_tables[pt_idx].addr == pt)
474 continue;
475 vm->page_tables[pt_idx].addr = pt;
476
477 pde = pd_addr + pt_idx * 8;
478 if (((last_pde + 8 * count) != pde) ||
479 ((last_pt + incr * count) != pt)) {
480
481 if (count) {
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800482 amdgpu_vm_update_pages(adev, ib, last_pde,
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400483 last_pt, count, incr,
484 AMDGPU_PTE_VALID, 0);
485 }
486
487 count = 1;
488 last_pde = pde;
489 last_pt = pt;
490 } else {
491 ++count;
492 }
493 }
494
495 if (count)
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800496 amdgpu_vm_update_pages(adev, ib, last_pde, last_pt, count,
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400497 incr, AMDGPU_PTE_VALID, 0);
498
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800499 if (ib->length_dw != 0) {
500 amdgpu_vm_pad_ib(adev, ib);
501 amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM);
502 WARN_ON(ib->length_dw > ndw);
Chunming Zhou4af9f072015-08-03 12:57:31 +0800503 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
504 &amdgpu_vm_free_job,
505 AMDGPU_FENCE_OWNER_VM,
506 &fence);
507 if (r)
508 goto error_free;
Bas Nieuwenhuizen05906de2015-08-14 20:08:40 +0200509
Chunming Zhou4af9f072015-08-03 12:57:31 +0800510 amdgpu_bo_fence(pd, fence, true);
Bas Nieuwenhuizen05906de2015-08-14 20:08:40 +0200511 fence_put(vm->page_directory_fence);
512 vm->page_directory_fence = fence_get(fence);
Chunming Zhou281b4222015-08-12 12:58:31 +0800513 fence_put(fence);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400514 }
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800515
516 if (!amdgpu_enable_scheduler || ib->length_dw == 0) {
517 amdgpu_ib_free(adev, ib);
518 kfree(ib);
519 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400520
521 return 0;
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800522
523error_free:
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800524 amdgpu_ib_free(adev, ib);
525 kfree(ib);
Chunming Zhou4af9f072015-08-03 12:57:31 +0800526 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400527}
528
529/**
530 * amdgpu_vm_frag_ptes - add fragment information to PTEs
531 *
532 * @adev: amdgpu_device pointer
533 * @ib: IB for the update
534 * @pe_start: first PTE to handle
535 * @pe_end: last PTE to handle
536 * @addr: addr those PTEs should point to
537 * @flags: hw mapping flags
538 * @gtt_flags: GTT hw mapping flags
539 *
540 * Global and local mutex must be locked!
541 */
542static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
543 struct amdgpu_ib *ib,
544 uint64_t pe_start, uint64_t pe_end,
545 uint64_t addr, uint32_t flags,
546 uint32_t gtt_flags)
547{
548 /**
549 * The MC L1 TLB supports variable sized pages, based on a fragment
550 * field in the PTE. When this field is set to a non-zero value, page
551 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
552 * flags are considered valid for all PTEs within the fragment range
553 * and corresponding mappings are assumed to be physically contiguous.
554 *
555 * The L1 TLB can store a single PTE for the whole fragment,
556 * significantly increasing the space available for translation
557 * caching. This leads to large improvements in throughput when the
558 * TLB is under pressure.
559 *
560 * The L2 TLB distributes small and large fragments into two
561 * asymmetric partitions. The large fragment cache is significantly
562 * larger. Thus, we try to use large fragments wherever possible.
563 * Userspace can support this by aligning virtual base address and
564 * allocation size to the fragment size.
565 */
566
567 /* SI and newer are optimized for 64KB */
568 uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB;
569 uint64_t frag_align = 0x80;
570
571 uint64_t frag_start = ALIGN(pe_start, frag_align);
572 uint64_t frag_end = pe_end & ~(frag_align - 1);
573
574 unsigned count;
575
576 /* system pages are non continuously */
577 if ((flags & AMDGPU_PTE_SYSTEM) || !(flags & AMDGPU_PTE_VALID) ||
578 (frag_start >= frag_end)) {
579
580 count = (pe_end - pe_start) / 8;
581 amdgpu_vm_update_pages(adev, ib, pe_start, addr, count,
582 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
583 return;
584 }
585
586 /* handle the 4K area at the beginning */
587 if (pe_start != frag_start) {
588 count = (frag_start - pe_start) / 8;
589 amdgpu_vm_update_pages(adev, ib, pe_start, addr, count,
590 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
591 addr += AMDGPU_GPU_PAGE_SIZE * count;
592 }
593
594 /* handle the area in the middle */
595 count = (frag_end - frag_start) / 8;
596 amdgpu_vm_update_pages(adev, ib, frag_start, addr, count,
597 AMDGPU_GPU_PAGE_SIZE, flags | frag_flags,
598 gtt_flags);
599
600 /* handle the 4K area at the end */
601 if (frag_end != pe_end) {
602 addr += AMDGPU_GPU_PAGE_SIZE * count;
603 count = (pe_end - frag_end) / 8;
604 amdgpu_vm_update_pages(adev, ib, frag_end, addr, count,
605 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
606 }
607}
608
609/**
610 * amdgpu_vm_update_ptes - make sure that page tables are valid
611 *
612 * @adev: amdgpu_device pointer
613 * @vm: requested vm
614 * @start: start of GPU address range
615 * @end: end of GPU address range
616 * @dst: destination address to map to
617 * @flags: mapping flags
618 *
619 * Update the page tables in the range @start - @end (cayman+).
620 *
621 * Global and local mutex must be locked!
622 */
623static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
624 struct amdgpu_vm *vm,
625 struct amdgpu_ib *ib,
626 uint64_t start, uint64_t end,
627 uint64_t dst, uint32_t flags,
628 uint32_t gtt_flags)
629{
630 uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
631 uint64_t last_pte = ~0, last_dst = ~0;
Christian Königa60c4232015-09-01 15:33:25 +0200632 void *owner = AMDGPU_FENCE_OWNER_VM;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400633 unsigned count = 0;
634 uint64_t addr;
635
Christian Königa60c4232015-09-01 15:33:25 +0200636 /* sync to everything on unmapping */
637 if (!(flags & AMDGPU_PTE_VALID))
638 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
639
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400640 /* walk over the address space and update the page tables */
641 for (addr = start; addr < end; ) {
642 uint64_t pt_idx = addr >> amdgpu_vm_block_size;
643 struct amdgpu_bo *pt = vm->page_tables[pt_idx].bo;
644 unsigned nptes;
645 uint64_t pte;
646 int r;
647
Christian Königa60c4232015-09-01 15:33:25 +0200648 amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv, owner);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400649 r = reservation_object_reserve_shared(pt->tbo.resv);
650 if (r)
651 return r;
652
653 if ((addr & ~mask) == (end & ~mask))
654 nptes = end - addr;
655 else
656 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
657
658 pte = amdgpu_bo_gpu_offset(pt);
659 pte += (addr & mask) * 8;
660
661 if ((last_pte + 8 * count) != pte) {
662
663 if (count) {
664 amdgpu_vm_frag_ptes(adev, ib, last_pte,
665 last_pte + 8 * count,
666 last_dst, flags,
667 gtt_flags);
668 }
669
670 count = nptes;
671 last_pte = pte;
672 last_dst = dst;
673 } else {
674 count += nptes;
675 }
676
677 addr += nptes;
678 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
679 }
680
681 if (count) {
682 amdgpu_vm_frag_ptes(adev, ib, last_pte,
683 last_pte + 8 * count,
684 last_dst, flags, gtt_flags);
685 }
686
687 return 0;
688}
689
690/**
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400691 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
692 *
693 * @adev: amdgpu_device pointer
694 * @vm: requested vm
695 * @mapping: mapped range and flags to use for the update
696 * @addr: addr to set the area to
697 * @gtt_flags: flags as they are used for GTT
698 * @fence: optional resulting fence
699 *
700 * Fill in the page table entries for @mapping.
701 * Returns 0 for success, -EINVAL for failure.
702 *
703 * Object have to be reserved and mutex must be locked!
704 */
705static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
706 struct amdgpu_vm *vm,
707 struct amdgpu_bo_va_mapping *mapping,
708 uint64_t addr, uint32_t gtt_flags,
Chunming Zhoubb1e38a42015-08-03 18:19:38 +0800709 struct fence **fence)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400710{
711 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
712 unsigned nptes, ncmds, ndw;
713 uint32_t flags = gtt_flags;
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800714 struct amdgpu_ib *ib;
Chunming Zhou4af9f072015-08-03 12:57:31 +0800715 struct fence *f = NULL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400716 int r;
717
718 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
719 * but in case of something, we filter the flags in first place
720 */
721 if (!(mapping->flags & AMDGPU_PTE_READABLE))
722 flags &= ~AMDGPU_PTE_READABLE;
723 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
724 flags &= ~AMDGPU_PTE_WRITEABLE;
725
726 trace_amdgpu_vm_bo_update(mapping);
727
728 nptes = mapping->it.last - mapping->it.start + 1;
729
730 /*
731 * reserve space for one command every (1 << BLOCK_SIZE)
732 * entries or 2k dwords (whatever is smaller)
733 */
734 ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1;
735
736 /* padding, etc. */
737 ndw = 64;
738
739 if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) {
740 /* only copy commands needed */
741 ndw += ncmds * 7;
742
743 } else if (flags & AMDGPU_PTE_SYSTEM) {
744 /* header for write data commands */
745 ndw += ncmds * 4;
746
747 /* body of write data command */
748 ndw += nptes * 2;
749
750 } else {
751 /* set page commands needed */
752 ndw += ncmds * 10;
753
754 /* two extra commands for begin/end of fragment */
755 ndw += 2 * 10;
756 }
757
758 /* update too big for an IB */
759 if (ndw > 0xfffff)
760 return -ENOMEM;
761
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800762 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
763 if (!ib)
764 return -ENOMEM;
765
766 r = amdgpu_ib_get(ring, NULL, ndw * 4, ib);
767 if (r) {
768 kfree(ib);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400769 return r;
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800770 }
771
772 ib->length_dw = 0;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400773
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800774 r = amdgpu_vm_update_ptes(adev, vm, ib, mapping->it.start,
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400775 mapping->it.last + 1, addr + mapping->offset,
776 flags, gtt_flags);
777
778 if (r) {
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800779 amdgpu_ib_free(adev, ib);
780 kfree(ib);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400781 return r;
782 }
783
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800784 amdgpu_vm_pad_ib(adev, ib);
785 WARN_ON(ib->length_dw > ndw);
Chunming Zhou4af9f072015-08-03 12:57:31 +0800786 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
787 &amdgpu_vm_free_job,
788 AMDGPU_FENCE_OWNER_VM,
789 &f);
790 if (r)
791 goto error_free;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400792
Christian Königbf60efd2015-09-04 10:47:56 +0200793 amdgpu_bo_fence(vm->page_directory, f, true);
Chunming Zhou4af9f072015-08-03 12:57:31 +0800794 if (fence) {
795 fence_put(*fence);
796 *fence = fence_get(f);
797 }
Chunming Zhou281b4222015-08-12 12:58:31 +0800798 fence_put(f);
Chunming Zhou4af9f072015-08-03 12:57:31 +0800799 if (!amdgpu_enable_scheduler) {
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800800 amdgpu_ib_free(adev, ib);
801 kfree(ib);
802 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400803 return 0;
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800804
805error_free:
Chunming Zhoud5fc5e82015-07-21 16:52:10 +0800806 amdgpu_ib_free(adev, ib);
807 kfree(ib);
Chunming Zhou4af9f072015-08-03 12:57:31 +0800808 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400809}
810
811/**
812 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
813 *
814 * @adev: amdgpu_device pointer
815 * @bo_va: requested BO and VM object
816 * @mem: ttm mem
817 *
818 * Fill in the page table entries for @bo_va.
819 * Returns 0 for success, -EINVAL for failure.
820 *
821 * Object have to be reserved and mutex must be locked!
822 */
823int amdgpu_vm_bo_update(struct amdgpu_device *adev,
824 struct amdgpu_bo_va *bo_va,
825 struct ttm_mem_reg *mem)
826{
827 struct amdgpu_vm *vm = bo_va->vm;
828 struct amdgpu_bo_va_mapping *mapping;
829 uint32_t flags;
830 uint64_t addr;
831 int r;
832
833 if (mem) {
Christian Königb7d698d2015-09-07 12:32:09 +0200834 addr = (u64)mem->start << PAGE_SHIFT;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400835 if (mem->mem_type != TTM_PL_TT)
836 addr += adev->vm_manager.vram_base_offset;
837 } else {
838 addr = 0;
839 }
840
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400841 flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
842
Christian König7fc11952015-07-30 11:53:42 +0200843 spin_lock(&vm->status_lock);
844 if (!list_empty(&bo_va->vm_status))
845 list_splice_init(&bo_va->valids, &bo_va->invalids);
846 spin_unlock(&vm->status_lock);
847
848 list_for_each_entry(mapping, &bo_va->invalids, list) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400849 r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, addr,
850 flags, &bo_va->last_pt_update);
851 if (r)
852 return r;
853 }
854
Christian Königd6c10f62015-09-28 12:00:23 +0200855 if (trace_amdgpu_vm_bo_mapping_enabled()) {
856 list_for_each_entry(mapping, &bo_va->valids, list)
857 trace_amdgpu_vm_bo_mapping(mapping);
858
859 list_for_each_entry(mapping, &bo_va->invalids, list)
860 trace_amdgpu_vm_bo_mapping(mapping);
861 }
862
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400863 spin_lock(&vm->status_lock);
monk.liu6d1d0ef2015-08-14 13:36:41 +0800864 list_splice_init(&bo_va->invalids, &bo_va->valids);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400865 list_del_init(&bo_va->vm_status);
Christian König7fc11952015-07-30 11:53:42 +0200866 if (!mem)
867 list_add(&bo_va->vm_status, &vm->cleared);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400868 spin_unlock(&vm->status_lock);
869
870 return 0;
871}
872
873/**
874 * amdgpu_vm_clear_freed - clear freed BOs in the PT
875 *
876 * @adev: amdgpu_device pointer
877 * @vm: requested vm
878 *
879 * Make sure all freed BOs are cleared in the PT.
880 * Returns 0 for success.
881 *
882 * PTs have to be reserved and mutex must be locked!
883 */
884int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
885 struct amdgpu_vm *vm)
886{
887 struct amdgpu_bo_va_mapping *mapping;
888 int r;
889
jimqu9c4153b2015-12-04 17:17:00 +0800890 spin_lock(&vm->freed_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400891 while (!list_empty(&vm->freed)) {
892 mapping = list_first_entry(&vm->freed,
893 struct amdgpu_bo_va_mapping, list);
894 list_del(&mapping->list);
jimqu9c4153b2015-12-04 17:17:00 +0800895 spin_unlock(&vm->freed_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400896 r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, 0, 0, NULL);
897 kfree(mapping);
898 if (r)
899 return r;
900
jimqu9c4153b2015-12-04 17:17:00 +0800901 spin_lock(&vm->freed_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400902 }
jimqu9c4153b2015-12-04 17:17:00 +0800903 spin_unlock(&vm->freed_lock);
904
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400905 return 0;
906
907}
908
909/**
910 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
911 *
912 * @adev: amdgpu_device pointer
913 * @vm: requested vm
914 *
915 * Make sure all invalidated BOs are cleared in the PT.
916 * Returns 0 for success.
917 *
918 * PTs have to be reserved and mutex must be locked!
919 */
920int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
monk.liucfe2c972015-05-26 15:01:54 +0800921 struct amdgpu_vm *vm, struct amdgpu_sync *sync)
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400922{
monk.liucfe2c972015-05-26 15:01:54 +0800923 struct amdgpu_bo_va *bo_va = NULL;
Christian König91e1a522015-07-06 22:06:40 +0200924 int r = 0;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400925
926 spin_lock(&vm->status_lock);
927 while (!list_empty(&vm->invalidated)) {
928 bo_va = list_first_entry(&vm->invalidated,
929 struct amdgpu_bo_va, vm_status);
930 spin_unlock(&vm->status_lock);
Chunming Zhou69b576a2015-11-18 11:17:39 +0800931 mutex_lock(&bo_va->mutex);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400932 r = amdgpu_vm_bo_update(adev, bo_va, NULL);
Chunming Zhou69b576a2015-11-18 11:17:39 +0800933 mutex_unlock(&bo_va->mutex);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400934 if (r)
935 return r;
936
937 spin_lock(&vm->status_lock);
938 }
939 spin_unlock(&vm->status_lock);
940
monk.liucfe2c972015-05-26 15:01:54 +0800941 if (bo_va)
Chunming Zhoubb1e38a42015-08-03 18:19:38 +0800942 r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
Christian König91e1a522015-07-06 22:06:40 +0200943
944 return r;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400945}
946
947/**
948 * amdgpu_vm_bo_add - add a bo to a specific vm
949 *
950 * @adev: amdgpu_device pointer
951 * @vm: requested vm
952 * @bo: amdgpu buffer object
953 *
954 * Add @bo into the requested vm (cayman+).
955 * Add @bo to the list of bos associated with the vm
956 * Returns newly added bo_va or NULL for failure
957 *
958 * Object has to be reserved!
959 */
960struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
961 struct amdgpu_vm *vm,
962 struct amdgpu_bo *bo)
963{
964 struct amdgpu_bo_va *bo_va;
965
966 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
967 if (bo_va == NULL) {
968 return NULL;
969 }
970 bo_va->vm = vm;
971 bo_va->bo = bo;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400972 bo_va->ref_count = 1;
973 INIT_LIST_HEAD(&bo_va->bo_list);
Christian König7fc11952015-07-30 11:53:42 +0200974 INIT_LIST_HEAD(&bo_va->valids);
975 INIT_LIST_HEAD(&bo_va->invalids);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400976 INIT_LIST_HEAD(&bo_va->vm_status);
Chunming Zhou69b576a2015-11-18 11:17:39 +0800977 mutex_init(&bo_va->mutex);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400978 list_add_tail(&bo_va->bo_list, &bo->va);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400979
980 return bo_va;
981}
982
983/**
984 * amdgpu_vm_bo_map - map bo inside a vm
985 *
986 * @adev: amdgpu_device pointer
987 * @bo_va: bo_va to store the address
988 * @saddr: where to map the BO
989 * @offset: requested offset in the BO
990 * @flags: attributes of pages (read/write/valid/etc.)
991 *
992 * Add a mapping of the BO at the specefied addr into the VM.
993 * Returns 0 for success, error for failure.
994 *
Chunming Zhou49b02b12015-11-13 14:18:38 +0800995 * Object has to be reserved and unreserved outside!
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400996 */
997int amdgpu_vm_bo_map(struct amdgpu_device *adev,
998 struct amdgpu_bo_va *bo_va,
999 uint64_t saddr, uint64_t offset,
1000 uint64_t size, uint32_t flags)
1001{
1002 struct amdgpu_bo_va_mapping *mapping;
1003 struct amdgpu_vm *vm = bo_va->vm;
1004 struct interval_tree_node *it;
1005 unsigned last_pfn, pt_idx;
1006 uint64_t eaddr;
1007 int r;
1008
Christian König0be52de2015-05-18 14:37:27 +02001009 /* validate the parameters */
1010 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
Chunming Zhou49b02b12015-11-13 14:18:38 +08001011 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
Christian König0be52de2015-05-18 14:37:27 +02001012 return -EINVAL;
Christian König0be52de2015-05-18 14:37:27 +02001013
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001014 /* make sure object fit at this offset */
1015 eaddr = saddr + size;
Chunming Zhou49b02b12015-11-13 14:18:38 +08001016 if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo)))
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001017 return -EINVAL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001018
1019 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
1020 if (last_pfn > adev->vm_manager.max_pfn) {
1021 dev_err(adev->dev, "va above limit (0x%08X > 0x%08X)\n",
1022 last_pfn, adev->vm_manager.max_pfn);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001023 return -EINVAL;
1024 }
1025
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001026 saddr /= AMDGPU_GPU_PAGE_SIZE;
1027 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1028
Chunming Zhouc25867d2015-11-13 13:32:01 +08001029 spin_lock(&vm->it_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001030 it = interval_tree_iter_first(&vm->va, saddr, eaddr - 1);
Chunming Zhouc25867d2015-11-13 13:32:01 +08001031 spin_unlock(&vm->it_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001032 if (it) {
1033 struct amdgpu_bo_va_mapping *tmp;
1034 tmp = container_of(it, struct amdgpu_bo_va_mapping, it);
1035 /* bo and tmp overlap, invalid addr */
1036 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1037 "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr,
1038 tmp->it.start, tmp->it.last + 1);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001039 r = -EINVAL;
Chunming Zhouf48b2652015-10-16 14:06:19 +08001040 goto error;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001041 }
1042
1043 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1044 if (!mapping) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001045 r = -ENOMEM;
Chunming Zhouf48b2652015-10-16 14:06:19 +08001046 goto error;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001047 }
1048
1049 INIT_LIST_HEAD(&mapping->list);
1050 mapping->it.start = saddr;
1051 mapping->it.last = eaddr - 1;
1052 mapping->offset = offset;
1053 mapping->flags = flags;
1054
Chunming Zhou69b576a2015-11-18 11:17:39 +08001055 mutex_lock(&bo_va->mutex);
Christian König7fc11952015-07-30 11:53:42 +02001056 list_add(&mapping->list, &bo_va->invalids);
Chunming Zhou69b576a2015-11-18 11:17:39 +08001057 mutex_unlock(&bo_va->mutex);
Chunming Zhouc25867d2015-11-13 13:32:01 +08001058 spin_lock(&vm->it_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001059 interval_tree_insert(&mapping->it, &vm->va);
Chunming Zhouc25867d2015-11-13 13:32:01 +08001060 spin_unlock(&vm->it_lock);
Christian König93e3e432015-06-09 16:58:33 +02001061 trace_amdgpu_vm_bo_map(bo_va, mapping);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001062
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001063 /* Make sure the page tables are allocated */
1064 saddr >>= amdgpu_vm_block_size;
1065 eaddr >>= amdgpu_vm_block_size;
1066
1067 BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
1068
1069 if (eaddr > vm->max_pde_used)
1070 vm->max_pde_used = eaddr;
1071
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001072 /* walk over the address space and allocate the page tables */
1073 for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
Christian Königbf60efd2015-09-04 10:47:56 +02001074 struct reservation_object *resv = vm->page_directory->tbo.resv;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001075 struct amdgpu_bo *pt;
1076
1077 if (vm->page_tables[pt_idx].bo)
1078 continue;
1079
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001080 r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
1081 AMDGPU_GPU_PAGE_SIZE, true,
Alex Deucher857d9132015-08-27 00:14:16 -04001082 AMDGPU_GEM_DOMAIN_VRAM,
1083 AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
Christian Königbf60efd2015-09-04 10:47:56 +02001084 NULL, resv, &pt);
Chunming Zhou49b02b12015-11-13 14:18:38 +08001085 if (r)
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001086 goto error_free;
Chunming Zhou49b02b12015-11-13 14:18:38 +08001087
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001088 r = amdgpu_vm_clear_bo(adev, pt);
1089 if (r) {
1090 amdgpu_bo_unref(&pt);
1091 goto error_free;
1092 }
1093
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001094 vm->page_tables[pt_idx].addr = 0;
1095 vm->page_tables[pt_idx].bo = pt;
1096 }
1097
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001098 return 0;
1099
1100error_free:
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001101 list_del(&mapping->list);
Chunming Zhouc25867d2015-11-13 13:32:01 +08001102 spin_lock(&vm->it_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001103 interval_tree_remove(&mapping->it, &vm->va);
Chunming Zhouc25867d2015-11-13 13:32:01 +08001104 spin_unlock(&vm->it_lock);
Christian König93e3e432015-06-09 16:58:33 +02001105 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001106 kfree(mapping);
1107
Chunming Zhouf48b2652015-10-16 14:06:19 +08001108error:
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001109 return r;
1110}
1111
1112/**
1113 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1114 *
1115 * @adev: amdgpu_device pointer
1116 * @bo_va: bo_va to remove the address from
1117 * @saddr: where to the BO is mapped
1118 *
1119 * Remove a mapping of the BO at the specefied addr from the VM.
1120 * Returns 0 for success, error for failure.
1121 *
Chunming Zhou49b02b12015-11-13 14:18:38 +08001122 * Object has to be reserved and unreserved outside!
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001123 */
1124int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1125 struct amdgpu_bo_va *bo_va,
1126 uint64_t saddr)
1127{
1128 struct amdgpu_bo_va_mapping *mapping;
1129 struct amdgpu_vm *vm = bo_va->vm;
Christian König7fc11952015-07-30 11:53:42 +02001130 bool valid = true;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001131
Christian König6c7fc502015-06-05 20:56:17 +02001132 saddr /= AMDGPU_GPU_PAGE_SIZE;
Chunming Zhou69b576a2015-11-18 11:17:39 +08001133 mutex_lock(&bo_va->mutex);
Christian König7fc11952015-07-30 11:53:42 +02001134 list_for_each_entry(mapping, &bo_va->valids, list) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001135 if (mapping->it.start == saddr)
1136 break;
1137 }
1138
Christian König7fc11952015-07-30 11:53:42 +02001139 if (&mapping->list == &bo_va->valids) {
1140 valid = false;
1141
1142 list_for_each_entry(mapping, &bo_va->invalids, list) {
1143 if (mapping->it.start == saddr)
1144 break;
1145 }
1146
Chunming Zhou69b576a2015-11-18 11:17:39 +08001147 if (&mapping->list == &bo_va->invalids) {
1148 mutex_unlock(&bo_va->mutex);
Christian König7fc11952015-07-30 11:53:42 +02001149 return -ENOENT;
Chunming Zhou69b576a2015-11-18 11:17:39 +08001150 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001151 }
Chunming Zhou69b576a2015-11-18 11:17:39 +08001152 mutex_unlock(&bo_va->mutex);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001153 list_del(&mapping->list);
Chunming Zhouc25867d2015-11-13 13:32:01 +08001154 spin_lock(&vm->it_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001155 interval_tree_remove(&mapping->it, &vm->va);
Chunming Zhouc25867d2015-11-13 13:32:01 +08001156 spin_unlock(&vm->it_lock);
Christian König93e3e432015-06-09 16:58:33 +02001157 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001158
jimqu9c4153b2015-12-04 17:17:00 +08001159 if (valid) {
1160 spin_lock(&vm->freed_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001161 list_add(&mapping->list, &vm->freed);
jimqu9c4153b2015-12-04 17:17:00 +08001162 spin_unlock(&vm->freed_lock);
1163 } else {
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001164 kfree(mapping);
jimqu9c4153b2015-12-04 17:17:00 +08001165 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001166
1167 return 0;
1168}
1169
1170/**
1171 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1172 *
1173 * @adev: amdgpu_device pointer
1174 * @bo_va: requested bo_va
1175 *
1176 * Remove @bo_va->bo from the requested vm (cayman+).
1177 *
1178 * Object have to be reserved!
1179 */
1180void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1181 struct amdgpu_bo_va *bo_va)
1182{
1183 struct amdgpu_bo_va_mapping *mapping, *next;
1184 struct amdgpu_vm *vm = bo_va->vm;
1185
1186 list_del(&bo_va->bo_list);
1187
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001188 spin_lock(&vm->status_lock);
1189 list_del(&bo_va->vm_status);
1190 spin_unlock(&vm->status_lock);
1191
Christian König7fc11952015-07-30 11:53:42 +02001192 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001193 list_del(&mapping->list);
Chunming Zhouc25867d2015-11-13 13:32:01 +08001194 spin_lock(&vm->it_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001195 interval_tree_remove(&mapping->it, &vm->va);
Chunming Zhouc25867d2015-11-13 13:32:01 +08001196 spin_unlock(&vm->it_lock);
Christian König93e3e432015-06-09 16:58:33 +02001197 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
jimqu9c4153b2015-12-04 17:17:00 +08001198 spin_lock(&vm->freed_lock);
Christian König7fc11952015-07-30 11:53:42 +02001199 list_add(&mapping->list, &vm->freed);
jimqu9c4153b2015-12-04 17:17:00 +08001200 spin_unlock(&vm->freed_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001201 }
Christian König7fc11952015-07-30 11:53:42 +02001202 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1203 list_del(&mapping->list);
Chunming Zhouc25867d2015-11-13 13:32:01 +08001204 spin_lock(&vm->it_lock);
Christian König7fc11952015-07-30 11:53:42 +02001205 interval_tree_remove(&mapping->it, &vm->va);
Chunming Zhouc25867d2015-11-13 13:32:01 +08001206 spin_unlock(&vm->it_lock);
Christian König7fc11952015-07-30 11:53:42 +02001207 kfree(mapping);
1208 }
Chunming Zhoubb1e38a42015-08-03 18:19:38 +08001209 fence_put(bo_va->last_pt_update);
Chunming Zhou69b576a2015-11-18 11:17:39 +08001210 mutex_destroy(&bo_va->mutex);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001211 kfree(bo_va);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001212}
1213
1214/**
1215 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1216 *
1217 * @adev: amdgpu_device pointer
1218 * @vm: requested vm
1219 * @bo: amdgpu buffer object
1220 *
1221 * Mark @bo as invalid (cayman+).
1222 */
1223void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1224 struct amdgpu_bo *bo)
1225{
1226 struct amdgpu_bo_va *bo_va;
1227
1228 list_for_each_entry(bo_va, &bo->va, bo_list) {
Christian König7fc11952015-07-30 11:53:42 +02001229 spin_lock(&bo_va->vm->status_lock);
1230 if (list_empty(&bo_va->vm_status))
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001231 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
Christian König7fc11952015-07-30 11:53:42 +02001232 spin_unlock(&bo_va->vm->status_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001233 }
1234}
1235
1236/**
1237 * amdgpu_vm_init - initialize a vm instance
1238 *
1239 * @adev: amdgpu_device pointer
1240 * @vm: requested vm
1241 *
1242 * Init @vm fields (cayman+).
1243 */
1244int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1245{
1246 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
1247 AMDGPU_VM_PTE_COUNT * 8);
1248 unsigned pd_size, pd_entries, pts_size;
1249 int i, r;
1250
1251 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1252 vm->ids[i].id = 0;
1253 vm->ids[i].flushed_updates = NULL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001254 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001255 vm->va = RB_ROOT;
1256 spin_lock_init(&vm->status_lock);
1257 INIT_LIST_HEAD(&vm->invalidated);
Christian König7fc11952015-07-30 11:53:42 +02001258 INIT_LIST_HEAD(&vm->cleared);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001259 INIT_LIST_HEAD(&vm->freed);
Chunming Zhouc25867d2015-11-13 13:32:01 +08001260 spin_lock_init(&vm->it_lock);
jimqu9c4153b2015-12-04 17:17:00 +08001261 spin_lock_init(&vm->freed_lock);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001262 pd_size = amdgpu_vm_directory_size(adev);
1263 pd_entries = amdgpu_vm_num_pdes(adev);
1264
1265 /* allocate page table array */
1266 pts_size = pd_entries * sizeof(struct amdgpu_vm_pt);
1267 vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
1268 if (vm->page_tables == NULL) {
1269 DRM_ERROR("Cannot allocate memory for page table array\n");
1270 return -ENOMEM;
1271 }
1272
Bas Nieuwenhuizen05906de2015-08-14 20:08:40 +02001273 vm->page_directory_fence = NULL;
1274
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001275 r = amdgpu_bo_create(adev, pd_size, align, true,
Alex Deucher857d9132015-08-27 00:14:16 -04001276 AMDGPU_GEM_DOMAIN_VRAM,
1277 AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
Christian König72d76682015-09-03 17:34:59 +02001278 NULL, NULL, &vm->page_directory);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001279 if (r)
1280 return r;
Chunming Zhouef9f0a82015-11-13 13:43:22 +08001281 r = amdgpu_bo_reserve(vm->page_directory, false);
1282 if (r) {
1283 amdgpu_bo_unref(&vm->page_directory);
1284 vm->page_directory = NULL;
1285 return r;
1286 }
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001287 r = amdgpu_vm_clear_bo(adev, vm->page_directory);
Chunming Zhouef9f0a82015-11-13 13:43:22 +08001288 amdgpu_bo_unreserve(vm->page_directory);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001289 if (r) {
1290 amdgpu_bo_unref(&vm->page_directory);
1291 vm->page_directory = NULL;
1292 return r;
1293 }
1294
1295 return 0;
1296}
1297
1298/**
1299 * amdgpu_vm_fini - tear down a vm instance
1300 *
1301 * @adev: amdgpu_device pointer
1302 * @vm: requested vm
1303 *
1304 * Tear down @vm (cayman+).
1305 * Unbind the VM and remove all bos from the vm bo list
1306 */
1307void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1308{
1309 struct amdgpu_bo_va_mapping *mapping, *tmp;
1310 int i;
1311
1312 if (!RB_EMPTY_ROOT(&vm->va)) {
1313 dev_err(adev->dev, "still active bo inside vm\n");
1314 }
1315 rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) {
1316 list_del(&mapping->list);
1317 interval_tree_remove(&mapping->it, &vm->va);
1318 kfree(mapping);
1319 }
1320 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
1321 list_del(&mapping->list);
1322 kfree(mapping);
1323 }
1324
1325 for (i = 0; i < amdgpu_vm_num_pdes(adev); i++)
1326 amdgpu_bo_unref(&vm->page_tables[i].bo);
1327 kfree(vm->page_tables);
1328
1329 amdgpu_bo_unref(&vm->page_directory);
Bas Nieuwenhuizen05906de2015-08-14 20:08:40 +02001330 fence_put(vm->page_directory_fence);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001331 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
Christian König1c16c0a2015-11-14 21:31:40 +01001332 unsigned id = vm->ids[i].id;
1333
1334 atomic_long_cmpxchg(&adev->vm_manager.ids[id].owner,
1335 (long)vm, 0);
Chunming Zhou3c623382015-08-20 18:33:59 +08001336 fence_put(vm->ids[i].flushed_updates);
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001337 }
1338
Alex Deucherd38ceaf2015-04-20 16:55:21 -04001339}
Christian Königea89f8c2015-11-15 20:52:06 +01001340
1341/**
1342 * amdgpu_vm_manager_fini - cleanup VM manager
1343 *
1344 * @adev: amdgpu_device pointer
1345 *
1346 * Cleanup the VM manager and free resources.
1347 */
1348void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
1349{
1350 unsigned i;
1351
1352 for (i = 0; i < AMDGPU_NUM_VM; ++i)
Christian König1c16c0a2015-11-14 21:31:40 +01001353 fence_put(adev->vm_manager.ids[i].active);
Christian Königea89f8c2015-11-15 20:52:06 +01001354}