blob: 0de320084c4502fbd999b91aca42bfae08230a24 [file] [log] [blame]
Kevin Hilman51c5d842016-10-19 11:18:24 -07001/*
2 * Amlogic SD/eMMC driver for the GX/S905 family SoCs
3 *
4 * Copyright (c) 2016 BayLibre, SAS.
5 * Author: Kevin Hilman <khilman@baylibre.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution
19 * in the file called COPYING.
20 */
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
27#include <linux/ioport.h>
28#include <linux/spinlock.h>
29#include <linux/dma-mapping.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/mmc.h>
32#include <linux/mmc/sdio.h>
33#include <linux/mmc/slot-gpio.h>
34#include <linux/io.h>
35#include <linux/clk.h>
36#include <linux/clk-provider.h>
37#include <linux/regulator/consumer.h>
Ulf Hanssonb8789ec2016-12-30 13:47:23 +010038#include <linux/interrupt.h>
Heiner Kallweit1231e7e2017-03-25 11:23:24 +010039#include <linux/bitfield.h>
Kevin Hilman51c5d842016-10-19 11:18:24 -070040
41#define DRIVER_NAME "meson-gx-mmc"
42
43#define SD_EMMC_CLOCK 0x0
Heiner Kallweit1231e7e2017-03-25 11:23:24 +010044#define CLK_DIV_MASK GENMASK(5, 0)
Kevin Hilman51c5d842016-10-19 11:18:24 -070045#define CLK_DIV_MAX 63
Heiner Kallweit1231e7e2017-03-25 11:23:24 +010046#define CLK_SRC_MASK GENMASK(7, 6)
Kevin Hilman51c5d842016-10-19 11:18:24 -070047#define CLK_SRC_XTAL 0 /* external crystal */
48#define CLK_SRC_XTAL_RATE 24000000
49#define CLK_SRC_PLL 1 /* FCLK_DIV2 */
50#define CLK_SRC_PLL_RATE 1000000000
Heiner Kallweit1231e7e2017-03-25 11:23:24 +010051#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
Kevin Hilman51c5d842016-10-19 11:18:24 -070052#define CLK_PHASE_0 0
53#define CLK_PHASE_90 1
54#define CLK_PHASE_180 2
55#define CLK_PHASE_270 3
56#define CLK_ALWAYS_ON BIT(24)
57
58#define SD_EMMC_DElAY 0x4
59#define SD_EMMC_ADJUST 0x8
60#define SD_EMMC_CALOUT 0x10
61#define SD_EMMC_START 0x40
62#define START_DESC_INIT BIT(0)
63#define START_DESC_BUSY BIT(1)
Heiner Kallweit1231e7e2017-03-25 11:23:24 +010064#define START_DESC_ADDR_MASK GENMASK(31, 2)
Kevin Hilman51c5d842016-10-19 11:18:24 -070065
66#define SD_EMMC_CFG 0x44
Heiner Kallweit1231e7e2017-03-25 11:23:24 +010067#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
Kevin Hilman51c5d842016-10-19 11:18:24 -070068#define CFG_BUS_WIDTH_1 0x0
69#define CFG_BUS_WIDTH_4 0x1
70#define CFG_BUS_WIDTH_8 0x2
71#define CFG_DDR BIT(2)
Heiner Kallweit1231e7e2017-03-25 11:23:24 +010072#define CFG_BLK_LEN_MASK GENMASK(7, 4)
73#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
74#define CFG_RC_CC_MASK GENMASK(15, 12)
Kevin Hilman51c5d842016-10-19 11:18:24 -070075#define CFG_STOP_CLOCK BIT(22)
76#define CFG_CLK_ALWAYS_ON BIT(18)
Heiner Kallweite21e6fd2017-02-07 22:35:59 +010077#define CFG_CHK_DS BIT(20)
Kevin Hilman51c5d842016-10-19 11:18:24 -070078#define CFG_AUTO_CLK BIT(23)
79
80#define SD_EMMC_STATUS 0x48
81#define STATUS_BUSY BIT(31)
82
83#define SD_EMMC_IRQ_EN 0x4c
Heiner Kallweit1231e7e2017-03-25 11:23:24 +010084#define IRQ_EN_MASK GENMASK(13, 0)
85#define IRQ_RXD_ERR_MASK GENMASK(7, 0)
Kevin Hilman51c5d842016-10-19 11:18:24 -070086#define IRQ_TXD_ERR BIT(8)
87#define IRQ_DESC_ERR BIT(9)
88#define IRQ_RESP_ERR BIT(10)
89#define IRQ_RESP_TIMEOUT BIT(11)
90#define IRQ_DESC_TIMEOUT BIT(12)
91#define IRQ_END_OF_CHAIN BIT(13)
92#define IRQ_RESP_STATUS BIT(14)
93#define IRQ_SDIO BIT(15)
94
95#define SD_EMMC_CMD_CFG 0x50
96#define SD_EMMC_CMD_ARG 0x54
97#define SD_EMMC_CMD_DAT 0x58
98#define SD_EMMC_CMD_RSP 0x5c
99#define SD_EMMC_CMD_RSP1 0x60
100#define SD_EMMC_CMD_RSP2 0x64
101#define SD_EMMC_CMD_RSP3 0x68
102
103#define SD_EMMC_RXD 0x94
104#define SD_EMMC_TXD 0x94
105#define SD_EMMC_LAST_REG SD_EMMC_TXD
106
107#define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
108#define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
Heiner Kallweitbb11eff2017-03-04 13:37:46 +0100109#define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
110#define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
Kevin Hilman51c5d842016-10-19 11:18:24 -0700111#define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
112#define MUX_CLK_NUM_PARENTS 2
113
114struct meson_host {
115 struct device *dev;
116 struct mmc_host *mmc;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700117 struct mmc_command *cmd;
118
119 spinlock_t lock;
120 void __iomem *regs;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700121 struct clk *core_clk;
122 struct clk_mux mux;
123 struct clk *mux_clk;
Heiner Kallweit5da86882017-02-07 22:34:32 +0100124 unsigned long current_clock;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700125
126 struct clk_divider cfg_div;
127 struct clk *cfg_div_clk;
128
129 unsigned int bounce_buf_size;
130 void *bounce_buf;
131 dma_addr_t bounce_dma_addr;
132
133 bool vqmmc_enabled;
134};
135
136struct sd_emmc_desc {
137 u32 cmd_cfg;
138 u32 cmd_arg;
139 u32 cmd_data;
140 u32 cmd_resp;
141};
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100142
143#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
Kevin Hilman51c5d842016-10-19 11:18:24 -0700144#define CMD_CFG_BLOCK_MODE BIT(9)
145#define CMD_CFG_R1B BIT(10)
146#define CMD_CFG_END_OF_CHAIN BIT(11)
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100147#define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
Kevin Hilman51c5d842016-10-19 11:18:24 -0700148#define CMD_CFG_NO_RESP BIT(16)
149#define CMD_CFG_NO_CMD BIT(17)
150#define CMD_CFG_DATA_IO BIT(18)
151#define CMD_CFG_DATA_WR BIT(19)
152#define CMD_CFG_RESP_NOCRC BIT(20)
153#define CMD_CFG_RESP_128 BIT(21)
154#define CMD_CFG_RESP_NUM BIT(22)
155#define CMD_CFG_DATA_NUM BIT(23)
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100156#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
Kevin Hilman51c5d842016-10-19 11:18:24 -0700157#define CMD_CFG_ERROR BIT(30)
158#define CMD_CFG_OWNER BIT(31)
159
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100160#define CMD_DATA_MASK GENMASK(31, 2)
Kevin Hilman51c5d842016-10-19 11:18:24 -0700161#define CMD_DATA_BIG_ENDIAN BIT(1)
162#define CMD_DATA_SRAM BIT(0)
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100163#define CMD_RESP_MASK GENMASK(31, 1)
Kevin Hilman51c5d842016-10-19 11:18:24 -0700164#define CMD_RESP_SRAM BIT(0)
165
Heiner Kallweit4eee86c2017-03-25 11:26:18 +0100166static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
167{
168 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
169
170 if (!timeout)
171 return SD_EMMC_CMD_TIMEOUT_DATA;
172
173 timeout = roundup_pow_of_two(timeout);
174
175 return min(timeout, 32768U); /* max. 2^15 ms */
176}
177
Heiner Kallweite5e4a3e2017-03-25 11:28:13 +0100178static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
179{
180 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
181 return cmd->mrq->cmd;
182 else if (mmc_op_multi(cmd->opcode) &&
183 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
184 return cmd->mrq->stop;
185 else
186 return NULL;
187}
188
Kevin Hilman51c5d842016-10-19 11:18:24 -0700189static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate)
190{
191 struct mmc_host *mmc = host->mmc;
Heiner Kallweit5da86882017-02-07 22:34:32 +0100192 int ret;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700193 u32 cfg;
194
195 if (clk_rate) {
196 if (WARN_ON(clk_rate > mmc->f_max))
197 clk_rate = mmc->f_max;
198 else if (WARN_ON(clk_rate < mmc->f_min))
199 clk_rate = mmc->f_min;
200 }
201
Heiner Kallweit5da86882017-02-07 22:34:32 +0100202 if (clk_rate == host->current_clock)
Kevin Hilman51c5d842016-10-19 11:18:24 -0700203 return 0;
204
205 /* stop clock */
206 cfg = readl(host->regs + SD_EMMC_CFG);
207 if (!(cfg & CFG_STOP_CLOCK)) {
208 cfg |= CFG_STOP_CLOCK;
209 writel(cfg, host->regs + SD_EMMC_CFG);
210 }
211
212 dev_dbg(host->dev, "change clock rate %u -> %lu\n",
213 mmc->actual_clock, clk_rate);
214
Heiner Kallweit5da86882017-02-07 22:34:32 +0100215 if (!clk_rate) {
Kevin Hilman51c5d842016-10-19 11:18:24 -0700216 mmc->actual_clock = 0;
Heiner Kallweit5da86882017-02-07 22:34:32 +0100217 host->current_clock = 0;
218 /* return with clock being stopped */
Kevin Hilman51c5d842016-10-19 11:18:24 -0700219 return 0;
220 }
221
222 ret = clk_set_rate(host->cfg_div_clk, clk_rate);
Heiner Kallweit5da86882017-02-07 22:34:32 +0100223 if (ret) {
224 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
225 clk_rate, ret);
226 return ret;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700227 }
228
Heiner Kallweit5da86882017-02-07 22:34:32 +0100229 mmc->actual_clock = clk_get_rate(host->cfg_div_clk);
230 host->current_clock = clk_rate;
231
232 if (clk_rate != mmc->actual_clock)
233 dev_dbg(host->dev,
234 "divider requested rate %lu != actual rate %u\n",
235 clk_rate, mmc->actual_clock);
236
237 /* (re)start clock */
238 cfg = readl(host->regs + SD_EMMC_CFG);
239 cfg &= ~CFG_STOP_CLOCK;
240 writel(cfg, host->regs + SD_EMMC_CFG);
241
242 return 0;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700243}
244
245/*
246 * The SD/eMMC IP block has an internal mux and divider used for
247 * generating the MMC clock. Use the clock framework to create and
248 * manage these clocks.
249 */
250static int meson_mmc_clk_init(struct meson_host *host)
251{
252 struct clk_init_data init;
253 char clk_name[32];
254 int i, ret = 0;
255 const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
Kevin Hilman51c5d842016-10-19 11:18:24 -0700256 const char *clk_div_parents[1];
Kevin Hilman51c5d842016-10-19 11:18:24 -0700257 u32 clk_reg, cfg;
258
259 /* get the mux parents */
260 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
Heiner Kallweite9883ef2017-03-04 13:24:09 +0100261 struct clk *clk;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700262 char name[16];
263
264 snprintf(name, sizeof(name), "clkin%d", i);
Heiner Kallweite9883ef2017-03-04 13:24:09 +0100265 clk = devm_clk_get(host->dev, name);
266 if (IS_ERR(clk)) {
267 if (clk != ERR_PTR(-EPROBE_DEFER))
Kevin Hilman51c5d842016-10-19 11:18:24 -0700268 dev_err(host->dev, "Missing clock %s\n", name);
Heiner Kallweite9883ef2017-03-04 13:24:09 +0100269 return PTR_ERR(clk);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700270 }
271
Heiner Kallweite9883ef2017-03-04 13:24:09 +0100272 mux_parent_names[i] = __clk_get_name(clk);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700273 }
274
Kevin Hilman51c5d842016-10-19 11:18:24 -0700275 /* create the mux */
276 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
277 init.name = clk_name;
278 init.ops = &clk_mux_ops;
279 init.flags = 0;
280 init.parent_names = mux_parent_names;
Heiner Kallweit7558c112017-03-04 13:22:57 +0100281 init.num_parents = MUX_CLK_NUM_PARENTS;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700282 host->mux.reg = host->regs + SD_EMMC_CLOCK;
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100283 host->mux.shift = __bf_shf(CLK_SRC_MASK);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700284 host->mux.mask = CLK_SRC_MASK;
285 host->mux.flags = 0;
286 host->mux.table = NULL;
287 host->mux.hw.init = &init;
288
289 host->mux_clk = devm_clk_register(host->dev, &host->mux.hw);
290 if (WARN_ON(IS_ERR(host->mux_clk)))
291 return PTR_ERR(host->mux_clk);
292
293 /* create the divider */
294 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
Heiner Kallweit7b9ebad2017-03-04 13:26:24 +0100295 init.name = clk_name;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700296 init.ops = &clk_divider_ops;
297 init.flags = CLK_SET_RATE_PARENT;
298 clk_div_parents[0] = __clk_get_name(host->mux_clk);
299 init.parent_names = clk_div_parents;
300 init.num_parents = ARRAY_SIZE(clk_div_parents);
301
302 host->cfg_div.reg = host->regs + SD_EMMC_CLOCK;
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100303 host->cfg_div.shift = __bf_shf(CLK_DIV_MASK);
304 host->cfg_div.width = __builtin_popcountl(CLK_DIV_MASK);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700305 host->cfg_div.hw.init = &init;
306 host->cfg_div.flags = CLK_DIVIDER_ONE_BASED |
307 CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ALLOW_ZERO;
308
309 host->cfg_div_clk = devm_clk_register(host->dev, &host->cfg_div.hw);
310 if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk)))
311 return PTR_ERR(host->cfg_div_clk);
312
313 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
314 clk_reg = 0;
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100315 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
316 clk_reg |= FIELD_PREP(CLK_SRC_MASK, CLK_SRC_XTAL);
317 clk_reg |= FIELD_PREP(CLK_DIV_MASK, CLK_DIV_MAX);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700318 clk_reg &= ~CLK_ALWAYS_ON;
319 writel(clk_reg, host->regs + SD_EMMC_CLOCK);
320
321 /* Ensure clock starts in "auto" mode, not "always on" */
322 cfg = readl(host->regs + SD_EMMC_CFG);
323 cfg &= ~CFG_CLK_ALWAYS_ON;
324 cfg |= CFG_AUTO_CLK;
325 writel(cfg, host->regs + SD_EMMC_CFG);
326
327 ret = clk_prepare_enable(host->cfg_div_clk);
Ulf Hanssona4c38c82017-02-08 12:36:20 +0100328 if (ret)
329 return ret;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700330
Ulf Hanssona4c38c82017-02-08 12:36:20 +0100331 /* Get the nearest minimum clock to 400KHz */
332 host->mmc->f_min = clk_round_rate(host->cfg_div_clk, 400000);
333
334 ret = meson_mmc_clk_set(host, host->mmc->f_min);
Heiner Kallweitcac3a472017-03-04 13:25:14 +0100335 if (ret)
Kevin Hilman51c5d842016-10-19 11:18:24 -0700336 clk_disable_unprepare(host->cfg_div_clk);
337
338 return ret;
339}
340
341static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
342{
343 struct meson_host *host = mmc_priv(mmc);
344 u32 bus_width;
345 u32 val, orig;
346
347 /*
348 * GPIO regulator, only controls switching between 1v8 and
349 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
350 */
351 switch (ios->power_mode) {
352 case MMC_POWER_OFF:
353 if (!IS_ERR(mmc->supply.vmmc))
354 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
355
356 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
357 regulator_disable(mmc->supply.vqmmc);
358 host->vqmmc_enabled = false;
359 }
360
361 break;
362
363 case MMC_POWER_UP:
364 if (!IS_ERR(mmc->supply.vmmc))
365 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
366 break;
367
368 case MMC_POWER_ON:
369 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
370 int ret = regulator_enable(mmc->supply.vqmmc);
371
372 if (ret < 0)
373 dev_err(mmc_dev(mmc),
374 "failed to enable vqmmc regulator\n");
375 else
376 host->vqmmc_enabled = true;
377 }
378
379 break;
380 }
381
382
383 meson_mmc_clk_set(host, ios->clock);
384
385 /* Bus width */
Kevin Hilman51c5d842016-10-19 11:18:24 -0700386 switch (ios->bus_width) {
387 case MMC_BUS_WIDTH_1:
388 bus_width = CFG_BUS_WIDTH_1;
389 break;
390 case MMC_BUS_WIDTH_4:
391 bus_width = CFG_BUS_WIDTH_4;
392 break;
393 case MMC_BUS_WIDTH_8:
394 bus_width = CFG_BUS_WIDTH_8;
395 break;
396 default:
397 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
398 ios->bus_width);
399 bus_width = CFG_BUS_WIDTH_4;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700400 }
401
402 val = readl(host->regs + SD_EMMC_CFG);
403 orig = val;
404
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100405 val &= ~CFG_BUS_WIDTH_MASK;
406 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700407
Heiner Kallweite21e6fd2017-02-07 22:35:59 +0100408 val &= ~CFG_DDR;
409 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
410 ios->timing == MMC_TIMING_MMC_DDR52 ||
411 ios->timing == MMC_TIMING_MMC_HS400)
412 val |= CFG_DDR;
413
414 val &= ~CFG_CHK_DS;
415 if (ios->timing == MMC_TIMING_MMC_HS400)
416 val |= CFG_CHK_DS;
417
Heiner Kallweitc01d1212017-03-04 13:35:13 +0100418 if (val != orig) {
419 writel(val, host->regs + SD_EMMC_CFG);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700420 dev_dbg(host->dev, "%s: SD_EMMC_CFG: 0x%08x -> 0x%08x\n",
421 __func__, orig, val);
Heiner Kallweitc01d1212017-03-04 13:35:13 +0100422 }
Kevin Hilman51c5d842016-10-19 11:18:24 -0700423}
424
Heiner Kallweit3d6c9912017-03-04 13:20:44 +0100425static void meson_mmc_request_done(struct mmc_host *mmc,
426 struct mmc_request *mrq)
Kevin Hilman51c5d842016-10-19 11:18:24 -0700427{
428 struct meson_host *host = mmc_priv(mmc);
429
Kevin Hilman51c5d842016-10-19 11:18:24 -0700430 host->cmd = NULL;
431 mmc_request_done(host->mmc, mrq);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700432}
433
Heiner Kallweit3d03f6a2017-03-27 21:57:11 +0200434static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
435{
436 struct meson_host *host = mmc_priv(mmc);
437 u32 cfg, blksz_old;
438
439 cfg = readl(host->regs + SD_EMMC_CFG);
440 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
441
442 if (!is_power_of_2(blksz))
443 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
444
445 blksz = ilog2(blksz);
446
447 /* check if block-size matches, if not update */
448 if (blksz == blksz_old)
449 return;
450
451 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
452 blksz_old, blksz);
453
454 cfg &= ~CFG_BLK_LEN_MASK;
455 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
456 writel(cfg, host->regs + SD_EMMC_CFG);
457}
458
Kevin Hilman51c5d842016-10-19 11:18:24 -0700459static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
460{
461 struct meson_host *host = mmc_priv(mmc);
Heiner Kallweit00412dd2017-03-22 22:33:44 +0100462 struct mmc_data *data = cmd->data;
Heiner Kallweit3d03f6a2017-03-27 21:57:11 +0200463 u32 cmd_cfg = 0, cmd_data = 0;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700464 unsigned int xfer_bytes = 0;
465
466 /* Setup descriptors */
467 dma_rmb();
Kevin Hilman51c5d842016-10-19 11:18:24 -0700468
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100469 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
Heiner Kallweita322feb2017-03-22 22:33:47 +0100470 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */
Kevin Hilman51c5d842016-10-19 11:18:24 -0700471
472 /* Response */
473 if (cmd->flags & MMC_RSP_PRESENT) {
Kevin Hilman51c5d842016-10-19 11:18:24 -0700474 if (cmd->flags & MMC_RSP_136)
Heiner Kallweita322feb2017-03-22 22:33:47 +0100475 cmd_cfg |= CMD_CFG_RESP_128;
476 cmd_cfg |= CMD_CFG_RESP_NUM;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700477
478 if (!(cmd->flags & MMC_RSP_CRC))
Heiner Kallweita322feb2017-03-22 22:33:47 +0100479 cmd_cfg |= CMD_CFG_RESP_NOCRC;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700480
481 if (cmd->flags & MMC_RSP_BUSY)
Heiner Kallweita322feb2017-03-22 22:33:47 +0100482 cmd_cfg |= CMD_CFG_R1B;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700483 } else {
Heiner Kallweita322feb2017-03-22 22:33:47 +0100484 cmd_cfg |= CMD_CFG_NO_RESP;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700485 }
486
487 /* data? */
Heiner Kallweit00412dd2017-03-22 22:33:44 +0100488 if (data) {
Heiner Kallweita322feb2017-03-22 22:33:47 +0100489 cmd_cfg |= CMD_CFG_DATA_IO;
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100490 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
Heiner Kallweit4eee86c2017-03-25 11:26:18 +0100491 ilog2(meson_mmc_get_timeout_msecs(data)));
Heiner Kallweita744c6f2017-03-22 22:34:01 +0100492
Heiner Kallweit00412dd2017-03-22 22:33:44 +0100493 if (data->blocks > 1) {
Heiner Kallweita322feb2017-03-22 22:33:47 +0100494 cmd_cfg |= CMD_CFG_BLOCK_MODE;
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100495 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
496 data->blocks);
Heiner Kallweit3d03f6a2017-03-27 21:57:11 +0200497 meson_mmc_set_blksz(mmc, data->blksz);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700498 } else {
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100499 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700500 }
501
Heiner Kallweit00412dd2017-03-22 22:33:44 +0100502 data->bytes_xfered = 0;
503 xfer_bytes = data->blksz * data->blocks;
504 if (data->flags & MMC_DATA_WRITE) {
Heiner Kallweita322feb2017-03-22 22:33:47 +0100505 cmd_cfg |= CMD_CFG_DATA_WR;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700506 WARN_ON(xfer_bytes > host->bounce_buf_size);
Heiner Kallweit00412dd2017-03-22 22:33:44 +0100507 sg_copy_to_buffer(data->sg, data->sg_len,
Kevin Hilman51c5d842016-10-19 11:18:24 -0700508 host->bounce_buf, xfer_bytes);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700509 dma_wmb();
Kevin Hilman51c5d842016-10-19 11:18:24 -0700510 }
511
Heiner Kallweita322feb2017-03-22 22:33:47 +0100512 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700513 } else {
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100514 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
515 ilog2(SD_EMMC_CMD_TIMEOUT));
Kevin Hilman51c5d842016-10-19 11:18:24 -0700516 }
Kevin Hilman51c5d842016-10-19 11:18:24 -0700517
518 host->cmd = cmd;
519
520 /* Last descriptor */
Heiner Kallweita322feb2017-03-22 22:33:47 +0100521 cmd_cfg |= CMD_CFG_END_OF_CHAIN;
522 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
523 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
524 writel(0, host->regs + SD_EMMC_CMD_RSP);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700525 wmb(); /* ensure descriptor is written before kicked */
Heiner Kallweita322feb2017-03-22 22:33:47 +0100526 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700527}
528
529static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
530{
531 struct meson_host *host = mmc_priv(mmc);
532
Kevin Hilman51c5d842016-10-19 11:18:24 -0700533 /* Stop execution */
534 writel(0, host->regs + SD_EMMC_START);
535
Kevin Hilman51c5d842016-10-19 11:18:24 -0700536 if (mrq->sbc)
537 meson_mmc_start_cmd(mmc, mrq->sbc);
538 else
539 meson_mmc_start_cmd(mmc, mrq->cmd);
540}
541
Heiner Kallweit3d6c9912017-03-04 13:20:44 +0100542static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
Kevin Hilman51c5d842016-10-19 11:18:24 -0700543{
544 struct meson_host *host = mmc_priv(mmc);
545
546 if (cmd->flags & MMC_RSP_136) {
547 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
548 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
549 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
550 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
551 } else if (cmd->flags & MMC_RSP_PRESENT) {
552 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
553 }
Kevin Hilman51c5d842016-10-19 11:18:24 -0700554}
555
556static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
557{
558 struct meson_host *host = dev_id;
Heinrich Schuchardt19a91dd2016-12-23 16:01:08 +0100559 struct mmc_command *cmd;
Heiner Kallweit2c8d96a2017-03-22 22:33:53 +0100560 struct mmc_data *data;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700561 u32 irq_en, status, raw_status;
562 irqreturn_t ret = IRQ_HANDLED;
563
564 if (WARN_ON(!host))
565 return IRQ_NONE;
566
Heinrich Schuchardt19a91dd2016-12-23 16:01:08 +0100567 cmd = host->cmd;
568
Kevin Hilman51c5d842016-10-19 11:18:24 -0700569 if (WARN_ON(!cmd))
570 return IRQ_NONE;
571
Heiner Kallweit2c8d96a2017-03-22 22:33:53 +0100572 data = cmd->data;
573
Kevin Hilman51c5d842016-10-19 11:18:24 -0700574 spin_lock(&host->lock);
575 irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
576 raw_status = readl(host->regs + SD_EMMC_STATUS);
577 status = raw_status & irq_en;
578
579 if (!status) {
580 dev_warn(host->dev, "Spurious IRQ! status=0x%08x, irq_en=0x%08x\n",
581 raw_status, irq_en);
582 ret = IRQ_NONE;
583 goto out;
584 }
585
Heiner Kallweit1f8066d2017-03-22 22:33:50 +0100586 meson_mmc_read_resp(host->mmc, cmd);
587
Kevin Hilman51c5d842016-10-19 11:18:24 -0700588 cmd->error = 0;
589 if (status & IRQ_RXD_ERR_MASK) {
590 dev_dbg(host->dev, "Unhandled IRQ: RXD error\n");
591 cmd->error = -EILSEQ;
592 }
593 if (status & IRQ_TXD_ERR) {
594 dev_dbg(host->dev, "Unhandled IRQ: TXD error\n");
595 cmd->error = -EILSEQ;
596 }
597 if (status & IRQ_DESC_ERR)
598 dev_dbg(host->dev, "Unhandled IRQ: Descriptor error\n");
599 if (status & IRQ_RESP_ERR) {
600 dev_dbg(host->dev, "Unhandled IRQ: Response error\n");
601 cmd->error = -EILSEQ;
602 }
603 if (status & IRQ_RESP_TIMEOUT) {
604 dev_dbg(host->dev, "Unhandled IRQ: Response timeout\n");
605 cmd->error = -ETIMEDOUT;
606 }
607 if (status & IRQ_DESC_TIMEOUT) {
608 dev_dbg(host->dev, "Unhandled IRQ: Descriptor timeout\n");
609 cmd->error = -ETIMEDOUT;
610 }
611 if (status & IRQ_SDIO)
612 dev_dbg(host->dev, "Unhandled IRQ: SDIO.\n");
613
Heiner Kallweit2c8d96a2017-03-22 22:33:53 +0100614 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
615 if (data && !cmd->error)
616 data->bytes_xfered = data->blksz * data->blocks;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700617 ret = IRQ_WAKE_THREAD;
Heiner Kallweit2c8d96a2017-03-22 22:33:53 +0100618 } else {
Kevin Hilman51c5d842016-10-19 11:18:24 -0700619 dev_warn(host->dev, "Unknown IRQ! status=0x%04x: MMC CMD%u arg=0x%08x flags=0x%08x stop=%d\n",
620 status, cmd->opcode, cmd->arg,
Heiner Kallweit7cdcc482017-03-04 13:36:45 +0100621 cmd->flags, cmd->mrq->stop ? 1 : 0);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700622 if (cmd->data) {
623 struct mmc_data *data = cmd->data;
624
625 dev_warn(host->dev, "\tblksz %u blocks %u flags 0x%08x (%s%s)",
626 data->blksz, data->blocks, data->flags,
627 data->flags & MMC_DATA_WRITE ? "write" : "",
628 data->flags & MMC_DATA_READ ? "read" : "");
629 }
630 }
631
632out:
633 /* ack all (enabled) interrupts */
634 writel(status, host->regs + SD_EMMC_STATUS);
635
Heiner Kallweit1f8066d2017-03-22 22:33:50 +0100636 if (ret == IRQ_HANDLED)
Kevin Hilman51c5d842016-10-19 11:18:24 -0700637 meson_mmc_request_done(host->mmc, cmd->mrq);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700638
639 spin_unlock(&host->lock);
640 return ret;
641}
642
643static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
644{
645 struct meson_host *host = dev_id;
Heiner Kallweite5e4a3e2017-03-25 11:28:13 +0100646 struct mmc_command *next_cmd, *cmd = host->cmd;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700647 struct mmc_data *data;
648 unsigned int xfer_bytes;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700649
Kevin Hilman51c5d842016-10-19 11:18:24 -0700650 if (WARN_ON(!cmd))
Heinrich Schuchardt19a91dd2016-12-23 16:01:08 +0100651 return IRQ_NONE;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700652
653 data = cmd->data;
Heiner Kallweit690f90b2017-02-07 22:34:41 +0100654 if (data && data->flags & MMC_DATA_READ) {
Kevin Hilman51c5d842016-10-19 11:18:24 -0700655 xfer_bytes = data->blksz * data->blocks;
Heiner Kallweit690f90b2017-02-07 22:34:41 +0100656 WARN_ON(xfer_bytes > host->bounce_buf_size);
657 sg_copy_from_buffer(data->sg, data->sg_len,
658 host->bounce_buf, xfer_bytes);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700659 }
660
Heiner Kallweite5e4a3e2017-03-25 11:28:13 +0100661 next_cmd = meson_mmc_get_next_command(cmd);
662 if (next_cmd)
663 meson_mmc_start_cmd(host->mmc, next_cmd);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700664 else
Heiner Kallweite5e4a3e2017-03-25 11:28:13 +0100665 meson_mmc_request_done(host->mmc, cmd->mrq);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700666
Heiner Kallweit690f90b2017-02-07 22:34:41 +0100667 return IRQ_HANDLED;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700668}
669
670/*
671 * NOTE: we only need this until the GPIO/pinctrl driver can handle
672 * interrupts. For now, the MMC core will use this for polling.
673 */
674static int meson_mmc_get_cd(struct mmc_host *mmc)
675{
676 int status = mmc_gpio_get_cd(mmc);
677
678 if (status == -ENOSYS)
679 return 1; /* assume present */
680
681 return status;
682}
683
Heiner Kallweitc01d1212017-03-04 13:35:13 +0100684static void meson_mmc_cfg_init(struct meson_host *host)
685{
686 u32 cfg = 0;
687
Heiner Kallweit1231e7e2017-03-25 11:23:24 +0100688 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
689 ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
690 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
691 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
Heiner Kallweitc01d1212017-03-04 13:35:13 +0100692
693 writel(cfg, host->regs + SD_EMMC_CFG);
694}
695
Kevin Hilman51c5d842016-10-19 11:18:24 -0700696static const struct mmc_host_ops meson_mmc_ops = {
697 .request = meson_mmc_request,
698 .set_ios = meson_mmc_set_ios,
699 .get_cd = meson_mmc_get_cd,
700};
701
702static int meson_mmc_probe(struct platform_device *pdev)
703{
704 struct resource *res;
705 struct meson_host *host;
706 struct mmc_host *mmc;
Heiner Kallweit9a1da4d2017-03-04 13:21:54 +0100707 int ret, irq;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700708
709 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
710 if (!mmc)
711 return -ENOMEM;
712 host = mmc_priv(mmc);
713 host->mmc = mmc;
714 host->dev = &pdev->dev;
715 dev_set_drvdata(&pdev->dev, host);
716
717 spin_lock_init(&host->lock);
718
719 /* Get regulators and the supported OCR mask */
720 host->vqmmc_enabled = false;
721 ret = mmc_regulator_get_supply(mmc);
722 if (ret == -EPROBE_DEFER)
723 goto free_host;
724
725 ret = mmc_of_parse(mmc);
726 if (ret) {
Kevin Hilmandc012052017-01-25 16:01:39 -0800727 if (ret != -EPROBE_DEFER)
728 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700729 goto free_host;
730 }
731
732 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
733 host->regs = devm_ioremap_resource(&pdev->dev, res);
734 if (IS_ERR(host->regs)) {
735 ret = PTR_ERR(host->regs);
736 goto free_host;
737 }
738
Heiner Kallweit9a1da4d2017-03-04 13:21:54 +0100739 irq = platform_get_irq(pdev, 0);
740 if (!irq) {
Kevin Hilman51c5d842016-10-19 11:18:24 -0700741 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
742 ret = -EINVAL;
743 goto free_host;
744 }
745
746 host->core_clk = devm_clk_get(&pdev->dev, "core");
747 if (IS_ERR(host->core_clk)) {
748 ret = PTR_ERR(host->core_clk);
749 goto free_host;
750 }
751
752 ret = clk_prepare_enable(host->core_clk);
753 if (ret)
754 goto free_host;
755
756 ret = meson_mmc_clk_init(host);
757 if (ret)
Michał Zegance473d52017-03-14 21:05:20 +0100758 goto err_core_clk;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700759
760 /* Stop execution */
761 writel(0, host->regs + SD_EMMC_START);
762
763 /* clear, ack, enable all interrupts */
764 writel(0, host->regs + SD_EMMC_IRQ_EN);
765 writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS);
Heiner Kallweit92763b92017-02-07 22:34:51 +0100766 writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700767
Heiner Kallweitc01d1212017-03-04 13:35:13 +0100768 /* set config to sane default */
769 meson_mmc_cfg_init(host);
770
Heiner Kallweit9a1da4d2017-03-04 13:21:54 +0100771 ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq,
772 meson_mmc_irq_thread, IRQF_SHARED,
Heiner Kallweitf016c672017-03-25 11:24:41 +0100773 NULL, host);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700774 if (ret)
Heiner Kallweitcac3a472017-03-04 13:25:14 +0100775 goto err_div_clk;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700776
Heiner Kallweite5e4a3e2017-03-25 11:28:13 +0100777 mmc->caps |= MMC_CAP_CMD23;
Heiner Kallweitefe0b662017-02-07 22:34:58 +0100778 mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
779 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
780
Kevin Hilman51c5d842016-10-19 11:18:24 -0700781 /* data bounce buffer */
Heiner Kallweit4136fcb2017-02-07 22:35:02 +0100782 host->bounce_buf_size = mmc->max_req_size;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700783 host->bounce_buf =
784 dma_alloc_coherent(host->dev, host->bounce_buf_size,
785 &host->bounce_dma_addr, GFP_KERNEL);
786 if (host->bounce_buf == NULL) {
787 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
788 ret = -ENOMEM;
Heiner Kallweitcac3a472017-03-04 13:25:14 +0100789 goto err_div_clk;
Kevin Hilman51c5d842016-10-19 11:18:24 -0700790 }
791
792 mmc->ops = &meson_mmc_ops;
793 mmc_add_host(mmc);
794
795 return 0;
796
Heiner Kallweitcac3a472017-03-04 13:25:14 +0100797err_div_clk:
Kevin Hilman51c5d842016-10-19 11:18:24 -0700798 clk_disable_unprepare(host->cfg_div_clk);
Michał Zegance473d52017-03-14 21:05:20 +0100799err_core_clk:
Kevin Hilman51c5d842016-10-19 11:18:24 -0700800 clk_disable_unprepare(host->core_clk);
Michał Zegance473d52017-03-14 21:05:20 +0100801free_host:
Kevin Hilman51c5d842016-10-19 11:18:24 -0700802 mmc_free_host(mmc);
803 return ret;
804}
805
806static int meson_mmc_remove(struct platform_device *pdev)
807{
808 struct meson_host *host = dev_get_drvdata(&pdev->dev);
809
Michał Zegana01fc2a2017-02-18 18:06:47 +0100810 mmc_remove_host(host->mmc);
811
Heiner Kallweit92763b92017-02-07 22:34:51 +0100812 /* disable interrupts */
813 writel(0, host->regs + SD_EMMC_IRQ_EN);
814
Heiner Kallweit62d721a2017-02-07 22:35:40 +0100815 dma_free_coherent(host->dev, host->bounce_buf_size,
816 host->bounce_buf, host->bounce_dma_addr);
Kevin Hilman51c5d842016-10-19 11:18:24 -0700817
818 clk_disable_unprepare(host->cfg_div_clk);
819 clk_disable_unprepare(host->core_clk);
820
821 mmc_free_host(host->mmc);
822 return 0;
823}
824
825static const struct of_device_id meson_mmc_of_match[] = {
826 { .compatible = "amlogic,meson-gx-mmc", },
827 { .compatible = "amlogic,meson-gxbb-mmc", },
828 { .compatible = "amlogic,meson-gxl-mmc", },
829 { .compatible = "amlogic,meson-gxm-mmc", },
830 {}
831};
832MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
833
834static struct platform_driver meson_mmc_driver = {
835 .probe = meson_mmc_probe,
836 .remove = meson_mmc_remove,
837 .driver = {
838 .name = DRIVER_NAME,
839 .of_match_table = of_match_ptr(meson_mmc_of_match),
840 },
841};
842
843module_platform_driver(meson_mmc_driver);
844
845MODULE_DESCRIPTION("Amlogic S905*/GX* SD/eMMC driver");
846MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
847MODULE_LICENSE("GPL v2");