Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 1 | /* |
| 2 | * PMC-Sierra MSP board specific pci_ops |
| 3 | * |
| 4 | * Copyright 2001 MontaVista Software Inc. |
| 5 | * Copyright 2005-2007 PMC-Sierra, Inc |
| 6 | * |
| 7 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net |
| 8 | * |
| 9 | * Much of the code is derived from the original DDB5074 port by |
Geert Uytterhoeven | 5e888e8 | 2014-04-22 12:51:13 +0200 | [diff] [blame] | 10 | * Geert Uytterhoeven <geert@linux-m68k.org> |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 11 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 12 | * This program is free software; you can redistribute it and/or modify it |
| 13 | * under the terms of the GNU General Public License as published by the |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 14 | * Free Software Foundation; either version 2 of the License, or (at your |
| 15 | * option) any later version. |
| 16 | * |
| 17 | */ |
| 18 | |
| 19 | #define PCI_COUNTERS 1 |
| 20 | |
| 21 | #include <linux/types.h> |
| 22 | #include <linux/pci.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | |
| 25 | #if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS) |
| 26 | #include <linux/proc_fs.h> |
| 27 | #include <linux/seq_file.h> |
| 28 | #endif /* CONFIG_PROC_FS && PCI_COUNTERS */ |
| 29 | |
| 30 | #include <linux/kernel.h> |
| 31 | #include <linux/init.h> |
| 32 | |
| 33 | #include <asm/byteorder.h> |
| 34 | #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL) |
| 35 | #include <asm/mipsmtregs.h> |
| 36 | #endif |
| 37 | |
| 38 | #include <msp_prom.h> |
| 39 | #include <msp_cic_int.h> |
| 40 | #include <msp_pci.h> |
| 41 | #include <msp_regs.h> |
| 42 | #include <msp_regops.h> |
| 43 | |
| 44 | #define PCI_ACCESS_READ 0 |
| 45 | #define PCI_ACCESS_WRITE 1 |
| 46 | |
| 47 | #if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS) |
| 48 | static char proc_init; |
| 49 | extern struct proc_dir_entry *proc_bus_pci_dir; |
| 50 | unsigned int pci_int_count[32]; |
| 51 | |
| 52 | static void pci_proc_init(void); |
| 53 | |
| 54 | /***************************************************************************** |
| 55 | * |
David Howells | 2427015 | 2013-04-11 00:21:15 +0100 | [diff] [blame] | 56 | * FUNCTION: show_msp_pci_counts |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 57 | * _________________________________________________________________________ |
| 58 | * |
| 59 | * DESCRIPTION: Prints the count of how many times each PCI |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 60 | * interrupt has asserted. Can be invoked by the |
| 61 | * /proc filesystem. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 62 | * |
David Howells | 2427015 | 2013-04-11 00:21:15 +0100 | [diff] [blame] | 63 | * INPUTS: m - synthetic file construction data |
| 64 | * v - iterator |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 65 | * |
David Howells | 2427015 | 2013-04-11 00:21:15 +0100 | [diff] [blame] | 66 | * RETURNS: 0 or error |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 67 | * |
| 68 | ****************************************************************************/ |
David Howells | 2427015 | 2013-04-11 00:21:15 +0100 | [diff] [blame] | 69 | static int show_msp_pci_counts(struct seq_file *m, void *v) |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 70 | { |
| 71 | int i; |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 72 | unsigned int intcount, total = 0; |
| 73 | |
| 74 | for (i = 0; i < 32; ++i) { |
| 75 | intcount = pci_int_count[i]; |
| 76 | if (intcount != 0) { |
David Howells | 2427015 | 2013-04-11 00:21:15 +0100 | [diff] [blame] | 77 | seq_printf(m, "[%d] = %u\n", i, intcount); |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 78 | total += intcount; |
| 79 | } |
| 80 | } |
| 81 | |
David Howells | 2427015 | 2013-04-11 00:21:15 +0100 | [diff] [blame] | 82 | seq_printf(m, "total = %u\n", total); |
| 83 | return 0; |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 84 | } |
| 85 | |
| 86 | /***************************************************************************** |
| 87 | * |
David Howells | 2427015 | 2013-04-11 00:21:15 +0100 | [diff] [blame] | 88 | * FUNCTION: gen_pci_cfg_wr_show |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 89 | * _________________________________________________________________________ |
| 90 | * |
| 91 | * DESCRIPTION: Generates a configuration write cycle for debug purposes. |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 92 | * The IDSEL line asserted and location and data written are |
| 93 | * immaterial. Just want to be able to prove that a |
| 94 | * configuration write can be correctly generated on the |
| 95 | * PCI bus. Intent is that this function by invocable from |
| 96 | * the /proc filesystem. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 97 | * |
David Howells | 2427015 | 2013-04-11 00:21:15 +0100 | [diff] [blame] | 98 | * INPUTS: m - synthetic file construction data |
| 99 | * v - iterator |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 100 | * |
David Howells | 2427015 | 2013-04-11 00:21:15 +0100 | [diff] [blame] | 101 | * RETURNS: 0 or error |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 102 | * |
| 103 | ****************************************************************************/ |
David Howells | 2427015 | 2013-04-11 00:21:15 +0100 | [diff] [blame] | 104 | static int gen_pci_cfg_wr_show(struct seq_file *m, void *v) |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 105 | { |
| 106 | unsigned char where = 0; /* Write to static Device/Vendor ID */ |
| 107 | unsigned char bus_num = 0; /* Bus 0 */ |
| 108 | unsigned char dev_fn = 0xF; /* Arbitrary device number */ |
| 109 | u32 wr_data = 0xFF00AA00; /* Arbitrary data */ |
| 110 | struct msp_pci_regs *preg = (void *)PCI_BASE_REG; |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 111 | unsigned long value; |
| 112 | int intr; |
| 113 | |
David Howells | 2427015 | 2013-04-11 00:21:15 +0100 | [diff] [blame] | 114 | seq_puts(m, "PMC MSP PCI: Beginning\n"); |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 115 | |
| 116 | if (proc_init == 0) { |
| 117 | pci_proc_init(); |
| 118 | proc_init = ~0; |
| 119 | } |
| 120 | |
David Howells | 2427015 | 2013-04-11 00:21:15 +0100 | [diff] [blame] | 121 | seq_puts(m, "PMC MSP PCI: Before Cfg Wr\n"); |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 122 | |
| 123 | /* |
| 124 | * Generate PCI Configuration Write Cycle |
| 125 | */ |
| 126 | |
| 127 | /* Clear cause register bits */ |
| 128 | preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F); |
| 129 | |
| 130 | /* Setup address that is to appear on PCI bus */ |
| 131 | preg->config_addr = BPCI_CFGADDR_ENABLE | |
| 132 | (bus_num << BPCI_CFGADDR_BUSNUM_SHF) | |
| 133 | (dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) | |
| 134 | (where & 0xFC); |
| 135 | |
| 136 | value = cpu_to_le32(wr_data); |
| 137 | |
| 138 | /* Launch the PCI configuration write cycle */ |
| 139 | *PCI_CONFIG_SPACE_REG = value; |
| 140 | |
| 141 | /* |
| 142 | * Check if the PCI configuration cycle (rd or wr) succeeded, by |
| 143 | * checking the status bits for errors like master or target abort. |
| 144 | */ |
| 145 | intr = preg->if_status; |
| 146 | |
David Howells | 2427015 | 2013-04-11 00:21:15 +0100 | [diff] [blame] | 147 | seq_puts(m, "PMC MSP PCI: After Cfg Wr\n"); |
| 148 | return 0; |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | /***************************************************************************** |
| 152 | * |
| 153 | * FUNCTION: pci_proc_init |
| 154 | * _________________________________________________________________________ |
| 155 | * |
| 156 | * DESCRIPTION: Create entries in the /proc filesystem for debug access. |
| 157 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 158 | * INPUTS: none |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 159 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 160 | * OUTPUTS: none |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 161 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 162 | * RETURNS: none |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 163 | * |
| 164 | ****************************************************************************/ |
| 165 | static void pci_proc_init(void) |
| 166 | { |
Christoph Hellwig | 3f3942a | 2018-05-15 15:57:23 +0200 | [diff] [blame^] | 167 | proc_create_single("pmc_msp_pci_rd_cnt", 0, NULL, show_msp_pci_counts); |
| 168 | proc_create_single("pmc_msp_pci_cfg_wr", 0, NULL, gen_pci_cfg_wr_show); |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 169 | } |
| 170 | #endif /* CONFIG_PROC_FS && PCI_COUNTERS */ |
| 171 | |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 172 | /***************************************************************************** |
| 173 | * |
| 174 | * STRUCT: pci_io_resource |
| 175 | * _________________________________________________________________________ |
| 176 | * |
| 177 | * DESCRIPTION: Defines the address range that pciauto() will use to |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 178 | * assign to the I/O BARs of PCI devices. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 179 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 180 | * Use the start and end addresses of the MSP7120 PCI Host |
| 181 | * Controller I/O space, in the form that they appear on the |
| 182 | * PCI bus AFTER MSP7120 has performed address translation. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 183 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 184 | * For I/O accesses, MSP7120 ignores OATRAN and maps I/O |
| 185 | * accesses into the bottom 0xFFF region of address space, |
| 186 | * so that is the range to put into the pci_io_resource |
| 187 | * struct. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 188 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 189 | * In MSP4200, the start address was 0x04 instead of the |
| 190 | * expected 0x00. Will just assume there was a good reason |
| 191 | * for this! |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 192 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 193 | * NOTES: Linux, by default, will assign I/O space to the lowest |
| 194 | * region of address space. Since MSP7120 and Linux, |
| 195 | * by default, have no offset in between how they map, the |
| 196 | * io_offset element of pci_controller struct should be set |
| 197 | * to zero. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 198 | * ELEMENTS: |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 199 | * name - String used for a meaningful name. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 200 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 201 | * start - Start address of MSP7120's I/O space, as MSP7120 presents |
| 202 | * the address on the PCI bus. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 203 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 204 | * end - End address of MSP7120's I/O space, as MSP7120 presents |
| 205 | * the address on the PCI bus. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 206 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 207 | * flags - Attributes indicating the type of resource. In this case, |
| 208 | * indicate I/O space. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 209 | * |
| 210 | ****************************************************************************/ |
| 211 | static struct resource pci_io_resource = { |
| 212 | .name = "pci IO space", |
| 213 | .start = 0x04, |
| 214 | .end = 0x0FFF, |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 215 | .flags = IORESOURCE_IO /* I/O space */ |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 216 | }; |
| 217 | |
| 218 | /***************************************************************************** |
| 219 | * |
| 220 | * STRUCT: pci_mem_resource |
| 221 | * _________________________________________________________________________ |
| 222 | * |
| 223 | * DESCRIPTION: Defines the address range that pciauto() will use to |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 224 | * assign to the memory BARs of PCI devices. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 225 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 226 | * The .start and .end values are dependent upon how address |
| 227 | * translation is performed by the OATRAN regiser. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 228 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 229 | * The values to use for .start and .end are the values |
| 230 | * in the form they appear on the PCI bus AFTER MSP7120 has |
| 231 | * performed OATRAN address translation. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 232 | * |
| 233 | * ELEMENTS: |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 234 | * name - String used for a meaningful name. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 235 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 236 | * start - Start address of MSP7120's memory space, as MSP7120 presents |
| 237 | * the address on the PCI bus. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 238 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 239 | * end - End address of MSP7120's memory space, as MSP7120 presents |
| 240 | * the address on the PCI bus. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 241 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 242 | * flags - Attributes indicating the type of resource. In this case, |
| 243 | * indicate memory space. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 244 | * |
| 245 | ****************************************************************************/ |
| 246 | static struct resource pci_mem_resource = { |
| 247 | .name = "pci memory space", |
| 248 | .start = MSP_PCI_SPACE_BASE, |
| 249 | .end = MSP_PCI_SPACE_END, |
| 250 | .flags = IORESOURCE_MEM /* memory space */ |
| 251 | }; |
| 252 | |
| 253 | /***************************************************************************** |
| 254 | * |
| 255 | * FUNCTION: bpci_interrupt |
| 256 | * _________________________________________________________________________ |
| 257 | * |
| 258 | * DESCRIPTION: PCI status interrupt handler. Updates the count of how |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 259 | * many times each status bit has been set, then clears |
| 260 | * the status bits. If the appropriate macros are defined, |
| 261 | * these counts can be viewed via the /proc filesystem. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 262 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 263 | * INPUTS: irq - unused |
| 264 | * dev_id - unused |
| 265 | * pt_regs - unused |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 266 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 267 | * OUTPUTS: none |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 268 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 269 | * RETURNS: PCIBIOS_SUCCESSFUL - success |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 270 | * |
| 271 | ****************************************************************************/ |
Anoop P A | a18059a | 2010-11-18 16:02:50 +0530 | [diff] [blame] | 272 | static irqreturn_t bpci_interrupt(int irq, void *dev_id) |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 273 | { |
| 274 | struct msp_pci_regs *preg = (void *)PCI_BASE_REG; |
| 275 | unsigned int stat = preg->if_status; |
| 276 | |
| 277 | #if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS) |
| 278 | int i; |
| 279 | for (i = 0; i < 32; ++i) { |
| 280 | if ((1 << i) & stat) |
| 281 | ++pci_int_count[i]; |
| 282 | } |
| 283 | #endif /* PROC_FS && PCI_COUNTERS */ |
| 284 | |
| 285 | /* printk("PCI ISR: Status=%08X\n", stat); */ |
| 286 | |
| 287 | /* write to clear all asserted interrupts */ |
| 288 | preg->if_status = stat; |
| 289 | |
Anoop P A | a18059a | 2010-11-18 16:02:50 +0530 | [diff] [blame] | 290 | return IRQ_HANDLED; |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 291 | } |
| 292 | |
| 293 | /***************************************************************************** |
| 294 | * |
| 295 | * FUNCTION: msp_pcibios_config_access |
| 296 | * _________________________________________________________________________ |
| 297 | * |
| 298 | * DESCRIPTION: Performs a PCI configuration access (rd or wr), then |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 299 | * checks that the access succeeded by querying MSP7120's |
| 300 | * PCI status bits. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 301 | * |
| 302 | * INPUTS: |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 303 | * access_type - kind of PCI configuration cycle to perform |
| 304 | * (read or write). Legal values are |
| 305 | * PCI_ACCESS_WRITE and PCI_ACCESS_READ. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 306 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 307 | * bus - pointer to the bus number of the device to |
| 308 | * be targeted for the configuration cycle. |
| 309 | * The only element of the pci_bus structure |
| 310 | * used is bus->number. This argument determines |
| 311 | * if the configuration access will be Type 0 or |
| 312 | * Type 1. Since MSP7120 assumes itself to be the |
| 313 | * PCI Host, any non-zero bus->number generates |
| 314 | * a Type 1 access. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 315 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 316 | * devfn - this is an 8-bit field. The lower three bits |
| 317 | * specify the function number of the device to |
| 318 | * be targeted for the configuration cycle, with |
| 319 | * all three-bit combinations being legal. The |
| 320 | * upper five bits specify the device number, |
| 321 | * with legal values being 10 to 31. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 322 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 323 | * where - address within the Configuration Header |
| 324 | * space to access. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 325 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 326 | * data - for write accesses, contains the data to |
| 327 | * write. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 328 | * |
| 329 | * OUTPUTS: |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 330 | * data - for read accesses, contains the value read. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 331 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 332 | * RETURNS: PCIBIOS_SUCCESSFUL - success |
| 333 | * -1 - access failure |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 334 | * |
| 335 | ****************************************************************************/ |
| 336 | int msp_pcibios_config_access(unsigned char access_type, |
| 337 | struct pci_bus *bus, |
| 338 | unsigned int devfn, |
| 339 | unsigned char where, |
| 340 | u32 *data) |
| 341 | { |
| 342 | struct msp_pci_regs *preg = (void *)PCI_BASE_REG; |
| 343 | unsigned char bus_num = bus->number; |
| 344 | unsigned char dev_fn = (unsigned char)devfn; |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 345 | unsigned long intr; |
| 346 | unsigned long value; |
| 347 | static char pciirqflag; |
Roel Kluin | 9718426 | 2009-09-18 12:50:11 -0700 | [diff] [blame] | 348 | int ret; |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 349 | #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL) |
| 350 | unsigned int vpe_status; |
| 351 | #endif |
| 352 | |
| 353 | #if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS) |
| 354 | if (proc_init == 0) { |
| 355 | pci_proc_init(); |
| 356 | proc_init = ~0; |
| 357 | } |
| 358 | #endif /* CONFIG_PROC_FS && PCI_COUNTERS */ |
| 359 | |
| 360 | /* |
| 361 | * Just the first time this function invokes, allocate |
| 362 | * an interrupt line for PCI host status interrupts. The |
| 363 | * allocation assigns an interrupt handler to the interrupt. |
| 364 | */ |
| 365 | if (pciirqflag == 0) { |
Roel Kluin | 9718426 | 2009-09-18 12:50:11 -0700 | [diff] [blame] | 366 | ret = request_irq(MSP_INT_PCI,/* Hardcoded internal MSP7120 wiring */ |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 367 | bpci_interrupt, |
Yong Zhang | 8b5690f | 2011-11-22 14:38:03 +0000 | [diff] [blame] | 368 | IRQF_SHARED, |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 369 | "PMC MSP PCI Host", |
| 370 | preg); |
Roel Kluin | 9718426 | 2009-09-18 12:50:11 -0700 | [diff] [blame] | 371 | if (ret != 0) |
| 372 | return ret; |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 373 | pciirqflag = ~0; |
| 374 | } |
| 375 | |
| 376 | #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL) |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 377 | vpe_status = dvpe(); |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 378 | #endif |
| 379 | |
| 380 | /* |
| 381 | * Clear PCI cause register bits. |
| 382 | * |
| 383 | * In Polo, the PCI Host had a dedicated DMA called the |
| 384 | * Block Copy (not to be confused with the general purpose Block |
| 385 | * Copy Engine block). There appear to have been special interrupts |
| 386 | * for this Block Copy, called Block Copy 0 Fault (BC0F) and |
| 387 | * Block Copy 1 Fault (BC1F). MSP4200 and MSP7120 don't have this |
| 388 | * dedicated Block Copy block, so these two interrupts are now |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 389 | * marked reserved. In case the Block Copy is resurrected in a |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 390 | * future design, maintain the code that treats these two interrupts |
| 391 | * specially. |
| 392 | * |
| 393 | * Write to clear all interrupts in the PCI status register, aside |
| 394 | * from BC0F and BC1F. |
| 395 | */ |
| 396 | preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F); |
| 397 | |
| 398 | /* Setup address that is to appear on PCI bus */ |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 399 | preg->config_addr = BPCI_CFGADDR_ENABLE | |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 400 | (bus_num << BPCI_CFGADDR_BUSNUM_SHF) | |
| 401 | (dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) | |
| 402 | (where & 0xFC); |
| 403 | |
| 404 | /* IF access is a PCI configuration write */ |
| 405 | if (access_type == PCI_ACCESS_WRITE) { |
| 406 | value = cpu_to_le32(*data); |
| 407 | *PCI_CONFIG_SPACE_REG = value; |
| 408 | } else { |
| 409 | /* ELSE access is a PCI configuration read */ |
| 410 | value = le32_to_cpu(*PCI_CONFIG_SPACE_REG); |
| 411 | *data = value; |
| 412 | } |
| 413 | |
| 414 | /* |
| 415 | * Check if the PCI configuration cycle (rd or wr) succeeded, by |
| 416 | * checking the status bits for errors like master or target abort. |
| 417 | */ |
| 418 | intr = preg->if_status; |
| 419 | |
| 420 | /* Clear config access */ |
| 421 | preg->config_addr = 0; |
| 422 | |
| 423 | /* IF error occurred */ |
| 424 | if (intr & ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F)) { |
| 425 | /* Clear status bits */ |
| 426 | preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F); |
| 427 | |
| 428 | #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL) |
| 429 | evpe(vpe_status); |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 430 | #endif |
| 431 | |
| 432 | return -1; |
| 433 | } |
| 434 | |
| 435 | #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL) |
| 436 | evpe(vpe_status); |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 437 | #endif |
| 438 | |
| 439 | return PCIBIOS_SUCCESSFUL; |
| 440 | } |
| 441 | |
| 442 | /***************************************************************************** |
| 443 | * |
| 444 | * FUNCTION: msp_pcibios_read_config_byte |
| 445 | * _________________________________________________________________________ |
| 446 | * |
| 447 | * DESCRIPTION: Read a byte from PCI configuration address spac |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 448 | * Since the hardware can't address 8 bit chunks |
| 449 | * directly, read a 32-bit chunk, then mask off extraneous |
| 450 | * bits. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 451 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 452 | * INPUTS bus - structure containing attributes for the PCI bus |
| 453 | * that the read is destined for. |
| 454 | * devfn - device/function combination that the read is |
| 455 | * destined for. |
| 456 | * where - register within the Configuration Header space |
| 457 | * to access. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 458 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 459 | * OUTPUTS val - read data |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 460 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 461 | * RETURNS: PCIBIOS_SUCCESSFUL - success |
| 462 | * -1 - read access failure |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 463 | * |
| 464 | ****************************************************************************/ |
| 465 | static int |
| 466 | msp_pcibios_read_config_byte(struct pci_bus *bus, |
| 467 | unsigned int devfn, |
| 468 | int where, |
| 469 | u32 *val) |
| 470 | { |
| 471 | u32 data = 0; |
| 472 | |
| 473 | /* |
| 474 | * If the config access did not complete normally (e.g., underwent |
| 475 | * master abort) do the PCI compliant thing, which is to supply an |
| 476 | * all ones value. |
| 477 | */ |
| 478 | if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, |
| 479 | where, &data)) { |
| 480 | *val = 0xFFFFFFFF; |
| 481 | return -1; |
| 482 | } |
| 483 | |
| 484 | *val = (data >> ((where & 3) << 3)) & 0x0ff; |
| 485 | |
| 486 | return PCIBIOS_SUCCESSFUL; |
| 487 | } |
| 488 | |
| 489 | /***************************************************************************** |
| 490 | * |
| 491 | * FUNCTION: msp_pcibios_read_config_word |
| 492 | * _________________________________________________________________________ |
| 493 | * |
| 494 | * DESCRIPTION: Read a word (16 bits) from PCI configuration address space. |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 495 | * Since the hardware can't address 16 bit chunks |
| 496 | * directly, read a 32-bit chunk, then mask off extraneous |
| 497 | * bits. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 498 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 499 | * INPUTS bus - structure containing attributes for the PCI bus |
| 500 | * that the read is destined for. |
| 501 | * devfn - device/function combination that the read is |
| 502 | * destined for. |
| 503 | * where - register within the Configuration Header space |
| 504 | * to access. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 505 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 506 | * OUTPUTS val - read data |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 507 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 508 | * RETURNS: PCIBIOS_SUCCESSFUL - success |
| 509 | * PCIBIOS_BAD_REGISTER_NUMBER - bad register address |
| 510 | * -1 - read access failure |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 511 | * |
| 512 | ****************************************************************************/ |
| 513 | static int |
| 514 | msp_pcibios_read_config_word(struct pci_bus *bus, |
| 515 | unsigned int devfn, |
| 516 | int where, |
| 517 | u32 *val) |
| 518 | { |
| 519 | u32 data = 0; |
| 520 | |
| 521 | /* if (where & 1) */ /* Commented out non-compliant code. |
| 522 | * Should allow word access to configuration |
| 523 | * registers, with only exception being when |
| 524 | * the word access would wrap around into |
| 525 | * the next dword. |
| 526 | */ |
| 527 | if ((where & 3) == 3) { |
| 528 | *val = 0xFFFFFFFF; |
| 529 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 530 | } |
| 531 | |
| 532 | /* |
| 533 | * If the config access did not complete normally (e.g., underwent |
| 534 | * master abort) do the PCI compliant thing, which is to supply an |
| 535 | * all ones value. |
| 536 | */ |
| 537 | if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, |
| 538 | where, &data)) { |
| 539 | *val = 0xFFFFFFFF; |
| 540 | return -1; |
| 541 | } |
| 542 | |
| 543 | *val = (data >> ((where & 3) << 3)) & 0x0ffff; |
| 544 | |
| 545 | return PCIBIOS_SUCCESSFUL; |
| 546 | } |
| 547 | |
| 548 | /***************************************************************************** |
| 549 | * |
| 550 | * FUNCTION: msp_pcibios_read_config_dword |
| 551 | * _________________________________________________________________________ |
| 552 | * |
| 553 | * DESCRIPTION: Read a double word (32 bits) from PCI configuration |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 554 | * address space. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 555 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 556 | * INPUTS bus - structure containing attributes for the PCI bus |
| 557 | * that the read is destined for. |
| 558 | * devfn - device/function combination that the read is |
| 559 | * destined for. |
| 560 | * where - register within the Configuration Header space |
| 561 | * to access. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 562 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 563 | * OUTPUTS val - read data |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 564 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 565 | * RETURNS: PCIBIOS_SUCCESSFUL - success |
| 566 | * PCIBIOS_BAD_REGISTER_NUMBER - bad register address |
| 567 | * -1 - read access failure |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 568 | * |
| 569 | ****************************************************************************/ |
| 570 | static int |
| 571 | msp_pcibios_read_config_dword(struct pci_bus *bus, |
| 572 | unsigned int devfn, |
| 573 | int where, |
| 574 | u32 *val) |
| 575 | { |
| 576 | u32 data = 0; |
| 577 | |
| 578 | /* Address must be dword aligned. */ |
| 579 | if (where & 3) { |
| 580 | *val = 0xFFFFFFFF; |
| 581 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 582 | } |
| 583 | |
| 584 | /* |
| 585 | * If the config access did not complete normally (e.g., underwent |
| 586 | * master abort) do the PCI compliant thing, which is to supply an |
| 587 | * all ones value. |
| 588 | */ |
| 589 | if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, |
| 590 | where, &data)) { |
| 591 | *val = 0xFFFFFFFF; |
| 592 | return -1; |
| 593 | } |
| 594 | |
| 595 | *val = data; |
| 596 | |
| 597 | return PCIBIOS_SUCCESSFUL; |
| 598 | } |
| 599 | |
| 600 | /***************************************************************************** |
| 601 | * |
| 602 | * FUNCTION: msp_pcibios_write_config_byte |
| 603 | * _________________________________________________________________________ |
| 604 | * |
| 605 | * DESCRIPTION: Write a byte to PCI configuration address space. |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 606 | * Since the hardware can't address 8 bit chunks |
| 607 | * directly, a read-modify-write is performed. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 608 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 609 | * INPUTS bus - structure containing attributes for the PCI bus |
| 610 | * that the write is destined for. |
| 611 | * devfn - device/function combination that the write is |
| 612 | * destined for. |
| 613 | * where - register within the Configuration Header space |
| 614 | * to access. |
| 615 | * val - value to write |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 616 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 617 | * OUTPUTS none |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 618 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 619 | * RETURNS: PCIBIOS_SUCCESSFUL - success |
| 620 | * -1 - write access failure |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 621 | * |
| 622 | ****************************************************************************/ |
| 623 | static int |
| 624 | msp_pcibios_write_config_byte(struct pci_bus *bus, |
| 625 | unsigned int devfn, |
| 626 | int where, |
| 627 | u8 val) |
| 628 | { |
| 629 | u32 data = 0; |
| 630 | |
| 631 | /* read config space */ |
| 632 | if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, |
| 633 | where, &data)) |
| 634 | return -1; |
| 635 | |
| 636 | /* modify the byte within the dword */ |
| 637 | data = (data & ~(0xff << ((where & 3) << 3))) | |
| 638 | (val << ((where & 3) << 3)); |
| 639 | |
| 640 | /* write back the full dword */ |
| 641 | if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, |
| 642 | where, &data)) |
| 643 | return -1; |
| 644 | |
| 645 | return PCIBIOS_SUCCESSFUL; |
| 646 | } |
| 647 | |
| 648 | /***************************************************************************** |
| 649 | * |
| 650 | * FUNCTION: msp_pcibios_write_config_word |
| 651 | * _________________________________________________________________________ |
| 652 | * |
| 653 | * DESCRIPTION: Write a word (16-bits) to PCI configuration address space. |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 654 | * Since the hardware can't address 16 bit chunks |
| 655 | * directly, a read-modify-write is performed. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 656 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 657 | * INPUTS bus - structure containing attributes for the PCI bus |
| 658 | * that the write is destined for. |
| 659 | * devfn - device/function combination that the write is |
| 660 | * destined for. |
| 661 | * where - register within the Configuration Header space |
| 662 | * to access. |
| 663 | * val - value to write |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 664 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 665 | * OUTPUTS none |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 666 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 667 | * RETURNS: PCIBIOS_SUCCESSFUL - success |
| 668 | * PCIBIOS_BAD_REGISTER_NUMBER - bad register address |
| 669 | * -1 - write access failure |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 670 | * |
| 671 | ****************************************************************************/ |
| 672 | static int |
| 673 | msp_pcibios_write_config_word(struct pci_bus *bus, |
| 674 | unsigned int devfn, |
| 675 | int where, |
| 676 | u16 val) |
| 677 | { |
| 678 | u32 data = 0; |
| 679 | |
| 680 | /* Fixed non-compliance: if (where & 1) */ |
| 681 | if ((where & 3) == 3) |
| 682 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 683 | |
| 684 | /* read config space */ |
| 685 | if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, |
| 686 | where, &data)) |
| 687 | return -1; |
| 688 | |
| 689 | /* modify the word within the dword */ |
| 690 | data = (data & ~(0xffff << ((where & 3) << 3))) | |
| 691 | (val << ((where & 3) << 3)); |
| 692 | |
| 693 | /* write back the full dword */ |
| 694 | if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, |
| 695 | where, &data)) |
| 696 | return -1; |
| 697 | |
| 698 | return PCIBIOS_SUCCESSFUL; |
| 699 | } |
| 700 | |
| 701 | /***************************************************************************** |
| 702 | * |
| 703 | * FUNCTION: msp_pcibios_write_config_dword |
| 704 | * _________________________________________________________________________ |
| 705 | * |
| 706 | * DESCRIPTION: Write a double word (32-bits) to PCI configuration address |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 707 | * space. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 708 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 709 | * INPUTS bus - structure containing attributes for the PCI bus |
| 710 | * that the write is destined for. |
| 711 | * devfn - device/function combination that the write is |
| 712 | * destined for. |
| 713 | * where - register within the Configuration Header space |
| 714 | * to access. |
| 715 | * val - value to write |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 716 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 717 | * OUTPUTS none |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 718 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 719 | * RETURNS: PCIBIOS_SUCCESSFUL - success |
| 720 | * PCIBIOS_BAD_REGISTER_NUMBER - bad register address |
| 721 | * -1 - write access failure |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 722 | * |
| 723 | ****************************************************************************/ |
| 724 | static int |
| 725 | msp_pcibios_write_config_dword(struct pci_bus *bus, |
| 726 | unsigned int devfn, |
| 727 | int where, |
| 728 | u32 val) |
| 729 | { |
| 730 | /* check that address is dword aligned */ |
| 731 | if (where & 3) |
| 732 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 733 | |
| 734 | /* perform write */ |
| 735 | if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, |
| 736 | where, &val)) |
| 737 | return -1; |
| 738 | |
| 739 | return PCIBIOS_SUCCESSFUL; |
| 740 | } |
| 741 | |
| 742 | /***************************************************************************** |
| 743 | * |
| 744 | * FUNCTION: msp_pcibios_read_config |
| 745 | * _________________________________________________________________________ |
| 746 | * |
| 747 | * DESCRIPTION: Interface the PCI configuration read request with |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 748 | * the appropriate function, based on how many bytes |
| 749 | * the read request is. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 750 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 751 | * INPUTS bus - structure containing attributes for the PCI bus |
| 752 | * that the write is destined for. |
| 753 | * devfn - device/function combination that the write is |
| 754 | * destined for. |
| 755 | * where - register within the Configuration Header space |
| 756 | * to access. |
| 757 | * size - in units of bytes, should be 1, 2, or 4. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 758 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 759 | * OUTPUTS val - value read, with any extraneous bytes masked |
| 760 | * to zero. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 761 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 762 | * RETURNS: PCIBIOS_SUCCESSFUL - success |
| 763 | * -1 - failure |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 764 | * |
| 765 | ****************************************************************************/ |
| 766 | int |
| 767 | msp_pcibios_read_config(struct pci_bus *bus, |
| 768 | unsigned int devfn, |
| 769 | int where, |
| 770 | int size, |
| 771 | u32 *val) |
| 772 | { |
| 773 | if (size == 1) { |
| 774 | if (msp_pcibios_read_config_byte(bus, devfn, where, val)) { |
| 775 | return -1; |
| 776 | } |
| 777 | } else if (size == 2) { |
| 778 | if (msp_pcibios_read_config_word(bus, devfn, where, val)) { |
| 779 | return -1; |
| 780 | } |
| 781 | } else if (size == 4) { |
| 782 | if (msp_pcibios_read_config_dword(bus, devfn, where, val)) { |
| 783 | return -1; |
| 784 | } |
| 785 | } else { |
| 786 | *val = 0xFFFFFFFF; |
| 787 | return -1; |
| 788 | } |
| 789 | |
| 790 | return PCIBIOS_SUCCESSFUL; |
| 791 | } |
| 792 | |
| 793 | /***************************************************************************** |
| 794 | * |
| 795 | * FUNCTION: msp_pcibios_write_config |
| 796 | * _________________________________________________________________________ |
| 797 | * |
| 798 | * DESCRIPTION: Interface the PCI configuration write request with |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 799 | * the appropriate function, based on how many bytes |
| 800 | * the read request is. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 801 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 802 | * INPUTS bus - structure containing attributes for the PCI bus |
| 803 | * that the write is destined for. |
| 804 | * devfn - device/function combination that the write is |
| 805 | * destined for. |
| 806 | * where - register within the Configuration Header space |
| 807 | * to access. |
| 808 | * size - in units of bytes, should be 1, 2, or 4. |
| 809 | * val - value to write |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 810 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 811 | * OUTPUTS: none |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 812 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 813 | * RETURNS: PCIBIOS_SUCCESSFUL - success |
| 814 | * -1 - failure |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 815 | * |
| 816 | ****************************************************************************/ |
| 817 | int |
| 818 | msp_pcibios_write_config(struct pci_bus *bus, |
| 819 | unsigned int devfn, |
| 820 | int where, |
| 821 | int size, |
| 822 | u32 val) |
| 823 | { |
| 824 | if (size == 1) { |
| 825 | if (msp_pcibios_write_config_byte(bus, devfn, |
| 826 | where, (u8)(0xFF & val))) { |
| 827 | return -1; |
| 828 | } |
| 829 | } else if (size == 2) { |
| 830 | if (msp_pcibios_write_config_word(bus, devfn, |
| 831 | where, (u16)(0xFFFF & val))) { |
| 832 | return -1; |
| 833 | } |
| 834 | } else if (size == 4) { |
| 835 | if (msp_pcibios_write_config_dword(bus, devfn, where, val)) { |
| 836 | return -1; |
| 837 | } |
| 838 | } else { |
| 839 | return -1; |
| 840 | } |
| 841 | |
| 842 | return PCIBIOS_SUCCESSFUL; |
| 843 | } |
| 844 | |
| 845 | /***************************************************************************** |
| 846 | * |
| 847 | * STRUCTURE: msp_pci_ops |
| 848 | * _________________________________________________________________________ |
| 849 | * |
| 850 | * DESCRIPTION: structure to abstract the hardware specific PCI |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 851 | * configuration accesses. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 852 | * |
| 853 | * ELEMENTS: |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 854 | * read - function for Linux to generate PCI Configuration reads. |
| 855 | * write - function for Linux to generate PCI Configuration writes. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 856 | * |
| 857 | ****************************************************************************/ |
| 858 | struct pci_ops msp_pci_ops = { |
| 859 | .read = msp_pcibios_read_config, |
| 860 | .write = msp_pcibios_write_config |
| 861 | }; |
| 862 | |
| 863 | /***************************************************************************** |
| 864 | * |
| 865 | * STRUCTURE: msp_pci_controller |
| 866 | * _________________________________________________________________________ |
| 867 | * |
| 868 | * Describes the attributes of the MSP7120 PCI Host Controller |
| 869 | * |
| 870 | * ELEMENTS: |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 871 | * pci_ops - abstracts the hardware specific PCI configuration |
| 872 | * accesses. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 873 | * |
| 874 | * mem_resource - address range pciauto() uses to assign to PCI device |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 875 | * memory BARs. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 876 | * |
| 877 | * mem_offset - offset between how MSP7120 outbound PCI memory |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 878 | * transaction addresses appear on the PCI bus and how Linux |
| 879 | * wants to configure memory BARs of the PCI devices. |
| 880 | * MSP7120 does nothing funky, so just set to zero. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 881 | * |
| 882 | * io_resource - address range pciauto() uses to assign to PCI device |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 883 | * I/O BARs. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 884 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 885 | * io_offset - offset between how MSP7120 outbound PCI I/O |
| 886 | * transaction addresses appear on the PCI bus and how |
| 887 | * Linux defaults to configure I/O BARs of the PCI devices. |
| 888 | * MSP7120 maps outbound I/O accesses into the bottom |
| 889 | * bottom 4K of PCI address space (and ignores OATRAN). |
| 890 | * Since the Linux default is to configure I/O BARs to the |
| 891 | * bottom 4K, no special offset is needed. Just set to zero. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 892 | * |
| 893 | ****************************************************************************/ |
| 894 | static struct pci_controller msp_pci_controller = { |
| 895 | .pci_ops = &msp_pci_ops, |
| 896 | .mem_resource = &pci_mem_resource, |
| 897 | .mem_offset = 0, |
Ben Hutchings | 8faf2e6 | 2010-06-13 22:22:59 +0100 | [diff] [blame] | 898 | .io_map_base = MSP_PCI_IOSPACE_BASE, |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 899 | .io_resource = &pci_io_resource, |
| 900 | .io_offset = 0 |
| 901 | }; |
| 902 | |
| 903 | /***************************************************************************** |
| 904 | * |
| 905 | * FUNCTION: msp_pci_init |
| 906 | * _________________________________________________________________________ |
| 907 | * |
| 908 | * DESCRIPTION: Initialize the PCI Host Controller and register it with |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 909 | * Linux so Linux can seize control of the PCI bus. |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 910 | * |
| 911 | ****************************************************************************/ |
| 912 | void __init msp_pci_init(void) |
| 913 | { |
| 914 | struct msp_pci_regs *preg = (void *)PCI_BASE_REG; |
| 915 | u32 id; |
| 916 | |
| 917 | /* Extract Device ID */ |
| 918 | id = read_reg32(PCI_JTAG_DEVID_REG, 0xFFFF) >> 12; |
| 919 | |
| 920 | /* Check if JTAG ID identifies MSP7120 */ |
| 921 | if (!MSP_HAS_PCI(id)) { |
| 922 | printk(KERN_WARNING "PCI: No PCI; id reads as %x\n", id); |
| 923 | goto no_pci; |
| 924 | } |
| 925 | |
| 926 | /* |
| 927 | * Enable flushing of the PCI-SDRAM queue upon a read |
| 928 | * of the SDRAM's Memory Configuration Register. |
| 929 | */ |
| 930 | *(unsigned long *)QFLUSH_REG_1 = 3; |
| 931 | |
| 932 | /* Configure PCI Host Controller. */ |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 933 | preg->if_status = ~0; /* Clear cause register bits */ |
Marc St-Jean | 6f95e60 | 2007-06-14 15:56:23 -0600 | [diff] [blame] | 934 | preg->config_addr = 0; /* Clear config access */ |
| 935 | preg->oatran = MSP_PCI_OATRAN; /* PCI outbound addr translation */ |
| 936 | preg->if_mask = 0xF8BF87C0; /* Enable all PCI status interrupts */ |
| 937 | |
| 938 | /* configure so inb(), outb(), and family are functional */ |
| 939 | set_io_port_base(MSP_PCI_IOSPACE_BASE); |
| 940 | |
| 941 | /* Tell Linux the details of the MSP7120 PCI Host Controller */ |
| 942 | register_pci_controller(&msp_pci_controller); |
| 943 | |
| 944 | return; |
| 945 | |
| 946 | no_pci: |
| 947 | /* Disable PCI channel */ |
| 948 | printk(KERN_WARNING "PCI: no host PCI bus detected\n"); |
| 949 | } |