| Matt Porter | 931398e | 2013-09-23 11:14:44 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2013 Linaro Limited |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | */ |
| 10 | |
| 11 | /dts-v1/; |
| 12 | #include "vf610.dtsi" |
| 13 | |
| 14 | / { |
| 15 | model = "PHYTEC Cosmic/Cosmic+ Board"; |
| 16 | compatible = "phytec,vf610-cosmic", "fsl,vf610"; |
| 17 | |
| 18 | chosen { |
| 19 | bootargs = "console=ttyLP1,115200"; |
| 20 | }; |
| 21 | |
| 22 | memory { |
| 23 | reg = <0x80000000 0x10000000>; |
| 24 | }; |
| 25 | |
| Stefan Agner | 3f3ebfb | 2014-11-02 21:36:44 +0100 | [diff] [blame^] | 26 | enet_ext: enet_ext { |
| 27 | compatible = "fixed-clock"; |
| 28 | #clock-cells = <0>; |
| 29 | clock-frequency = <50000000>; |
| Matt Porter | 931398e | 2013-09-23 11:14:44 -0400 | [diff] [blame] | 30 | }; |
| Stefan Agner | 3f3ebfb | 2014-11-02 21:36:44 +0100 | [diff] [blame^] | 31 | }; |
| Matt Porter | 931398e | 2013-09-23 11:14:44 -0400 | [diff] [blame] | 32 | |
| Stefan Agner | 3f3ebfb | 2014-11-02 21:36:44 +0100 | [diff] [blame^] | 33 | &clks { |
| 34 | clocks = <&sxosc>, <&fxosc>, <&enet_ext>; |
| 35 | clock-names = "sxosc", "fxosc", "enet_ext"; |
| Matt Porter | 931398e | 2013-09-23 11:14:44 -0400 | [diff] [blame] | 36 | }; |
| 37 | |
| 38 | &fec1 { |
| 39 | phy-mode = "rmii"; |
| 40 | pinctrl-names = "default"; |
| Shawn Guo | 07ed1ee | 2013-12-09 14:42:54 +0800 | [diff] [blame] | 41 | pinctrl-0 = <&pinctrl_fec1>; |
| Matt Porter | 931398e | 2013-09-23 11:14:44 -0400 | [diff] [blame] | 42 | status = "okay"; |
| 43 | }; |
| 44 | |
| Shawn Guo | 07ed1ee | 2013-12-09 14:42:54 +0800 | [diff] [blame] | 45 | &iomuxc { |
| 46 | vf610-cosmic { |
| 47 | pinctrl_fec1: fec1grp { |
| 48 | fsl,pins = < |
| 49 | VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 |
| 50 | VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 |
| 51 | VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 |
| 52 | VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 |
| 53 | VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 |
| 54 | VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 |
| 55 | VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 |
| 56 | VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 |
| 57 | VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 |
| 58 | >; |
| 59 | }; |
| 60 | |
| 61 | pinctrl_uart1: uart1grp { |
| 62 | fsl,pins = < |
| 63 | VF610_PAD_PTB4__UART1_TX 0x21a2 |
| 64 | VF610_PAD_PTB5__UART1_RX 0x21a1 |
| 65 | >; |
| 66 | }; |
| 67 | }; |
| 68 | }; |
| 69 | |
| Matt Porter | 931398e | 2013-09-23 11:14:44 -0400 | [diff] [blame] | 70 | &uart1 { |
| 71 | pinctrl-names = "default"; |
| Shawn Guo | 07ed1ee | 2013-12-09 14:42:54 +0800 | [diff] [blame] | 72 | pinctrl-0 = <&pinctrl_uart1>; |
| Matt Porter | 931398e | 2013-09-23 11:14:44 -0400 | [diff] [blame] | 73 | status = "okay"; |
| 74 | }; |