blob: d7d3a8d642827d85e9d8b4213cee47db5947ae32 [file] [log] [blame]
Anton Vorontsovd94f9442010-03-25 17:12:41 +03001/*
2 * Copyright 2008 Cavium Networks
3 *
4 * This file is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, Version 2, as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __MACH_BOARD_CNS3XXXH
10#define __MACH_BOARD_CNS3XXXH
11
12/*
13 * Memory map
14 */
15#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */
16#define CNS3XXX_FLASH_SIZE SZ_256M
17
18#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */
19
20#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
21
22#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
23#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000
24
25#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
26#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000
27
28#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
29#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000
30
31#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
32#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000
33
34#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
35#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000
36
37#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
38#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000
39
40#define SMC_MEMC_STATUS_OFFSET 0x000
41#define SMC_MEMIF_CFG_OFFSET 0x004
42#define SMC_MEMC_CFG_SET_OFFSET 0x008
43#define SMC_MEMC_CFG_CLR_OFFSET 0x00C
44#define SMC_DIRECT_CMD_OFFSET 0x010
45#define SMC_SET_CYCLES_OFFSET 0x014
46#define SMC_SET_OPMODE_OFFSET 0x018
47#define SMC_REFRESH_PERIOD_0_OFFSET 0x020
48#define SMC_REFRESH_PERIOD_1_OFFSET 0x024
49#define SMC_SRAM_CYCLES0_0_OFFSET 0x100
50#define SMC_NAND_CYCLES0_0_OFFSET 0x100
51#define SMC_OPMODE0_0_OFFSET 0x104
52#define SMC_SRAM_CYCLES0_1_OFFSET 0x120
53#define SMC_NAND_CYCLES0_1_OFFSET 0x120
54#define SMC_OPMODE0_1_OFFSET 0x124
55#define SMC_USER_STATUS_OFFSET 0x200
56#define SMC_USER_CONFIG_OFFSET 0x204
57#define SMC_ECC_STATUS_OFFSET 0x300
58#define SMC_ECC_MEMCFG_OFFSET 0x304
59#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308
60#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C
61#define SMC_ECC_ADDR0_OFFSET 0x310
62#define SMC_ECC_ADDR1_OFFSET 0x314
63#define SMC_ECC_VALUE0_OFFSET 0x318
64#define SMC_ECC_VALUE1_OFFSET 0x31C
65#define SMC_ECC_VALUE2_OFFSET 0x320
66#define SMC_ECC_VALUE3_OFFSET 0x324
67#define SMC_PERIPH_ID_0_OFFSET 0xFE0
68#define SMC_PERIPH_ID_1_OFFSET 0xFE4
69#define SMC_PERIPH_ID_2_OFFSET 0xFE8
70#define SMC_PERIPH_ID_3_OFFSET 0xFEC
71#define SMC_PCELL_ID_0_OFFSET 0xFF0
72#define SMC_PCELL_ID_1_OFFSET 0xFF4
73#define SMC_PCELL_ID_2_OFFSET 0xFF8
74#define SMC_PCELL_ID_3_OFFSET 0xFFC
75
76#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
77#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000
78
79#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
80#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000
81
82#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
83#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000
84
85#define RTC_SEC_OFFSET 0x00
86#define RTC_MIN_OFFSET 0x04
87#define RTC_HOUR_OFFSET 0x08
88#define RTC_DAY_OFFSET 0x0C
89#define RTC_SEC_ALM_OFFSET 0x10
90#define RTC_MIN_ALM_OFFSET 0x14
91#define RTC_HOUR_ALM_OFFSET 0x18
92#define RTC_REC_OFFSET 0x1C
93#define RTC_CTRL_OFFSET 0x20
94#define RTC_INTR_STS_OFFSET 0x34
95
96#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
97#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */
98
99#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
100#define CNS3XXX_PM_BASE_VIRT 0xFFF08000
101
102#define PM_CLK_GATE_OFFSET 0x00
103#define PM_SOFT_RST_OFFSET 0x04
104#define PM_HS_CFG_OFFSET 0x08
105#define PM_CACTIVE_STA_OFFSET 0x0C
106#define PM_PWR_STA_OFFSET 0x10
107#define PM_SYS_CLK_CTRL_OFFSET 0x14
108#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18
109#define PM_PLL_HM_PD_OFFSET 0x1C
110
111#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
112#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000
113
114#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
115#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000
116
117#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */
118#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000
119
120#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */
121#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000
122
123#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */
124#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000
125
126#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */
127#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000
128
129#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */
130#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000
131
132#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
133#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800
134
135#define TIMER1_COUNTER_OFFSET 0x00
136#define TIMER1_AUTO_RELOAD_OFFSET 0x04
137#define TIMER1_MATCH_V1_OFFSET 0x08
138#define TIMER1_MATCH_V2_OFFSET 0x0C
139
140#define TIMER2_COUNTER_OFFSET 0x10
141#define TIMER2_AUTO_RELOAD_OFFSET 0x14
142#define TIMER2_MATCH_V1_OFFSET 0x18
143#define TIMER2_MATCH_V2_OFFSET 0x1C
144
145#define TIMER1_2_CONTROL_OFFSET 0x30
146#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34
147#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38
148
149#define TIMER_FREERUN_OFFSET 0x40
150#define TIMER_FREERUN_CONTROL_OFFSET 0x44
151
152#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */
153#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000
154
155#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */
156#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000
157
158#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */
159#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000
160
161#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */
162#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000
163
164#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */
165#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000
166
167#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
Anton Vorontsovd94f9442010-03-25 17:12:41 +0300168
169#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
170#define CNS3XXX_SATA2_SIZE SZ_16M
171#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000
172
173#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */
174#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000
175
176#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */
177#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000
178
179#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */
180#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000
181
182#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */
183#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000
184
185#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
Anton Vorontsovd94f9442010-03-25 17:12:41 +0300186
187#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
188#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000
189
190#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
191#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000
192
193#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */
194#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000
195
196#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */
197#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000
198
199#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */
200#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000
201
202#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */
203#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000
204
205#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */
206#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000
207
208#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */
209#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000
210
211#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */
212#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000
213
214#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */
215#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000
216
217#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */
218#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000
219
220#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */
221#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000
222
223#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */
224#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000
225
226/*
227 * Testchip peripheral and fpga gic regions
228 */
229#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
230#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000
231
232#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
233#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100
234
235#define CNS3XXX_TC11MP_TWD_BASE 0x90000600
236#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600
237
238#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */
239#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000
240
241#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
242#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
243
244/*
245 * Misc block
246 */
247#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
Anton Vorontsovd94f9442010-03-25 17:12:41 +0300248
Anton Vorontsov6eb5d142010-06-02 14:12:08 +0400249#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00)
250#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04)
251#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08)
252#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C)
253#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10)
254#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14)
255#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18)
256#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C)
257#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20)
258#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24)
259#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28)
260#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C)
261#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30)
262#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34)
263#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40)
264#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44)
265#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48)
266#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C)
267#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50)
268#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54)
Anton Vorontsovd94f9442010-03-25 17:12:41 +0300269
Anton Vorontsov6eb5d142010-06-02 14:12:08 +0400270#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310)
Anton Vorontsovd94f9442010-03-25 17:12:41 +0300271
Anton Vorontsov6eb5d142010-06-02 14:12:08 +0400272#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800)
273#define MISC_USB_STS_REG MISC_MEM_MAP(0x804)
274#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808)
275#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c)
276#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810)
277#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814)
Anton Vorontsovd94f9442010-03-25 17:12:41 +0300278
279#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004)
280#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100)
281#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100)
282#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100)
283#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100)
284#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100)
285#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100)
286#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100)
287#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100)
288#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100)
289#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100)
290#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100)
291#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100)
292#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100)
293#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100)
294#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
295#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
296
297/*
298 * Power management and clock control
299 */
Anton Vorontsov6eb5d142010-06-02 14:12:08 +0400300#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
Anton Vorontsovd94f9442010-03-25 17:12:41 +0300301
Anton Vorontsov6eb5d142010-06-02 14:12:08 +0400302#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000)
303#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004)
304#define PM_HS_CFG_REG PMU_MEM_MAP(0x008)
305#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C)
306#define PM_PWR_STA_REG PMU_MEM_MAP(0x010)
307#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014)
308#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018)
309#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C)
310#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020)
311#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024)
312#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028)
313#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C)
314#define PM_CSR_REG PMU_MEM_MAP(0x030)
Anton Vorontsovd94f9442010-03-25 17:12:41 +0300315
316/* PM_CLK_GATE_REG */
317#define PM_CLK_GATE_REG_OFFSET_SDIO (25)
318#define PM_CLK_GATE_REG_OFFSET_GPU (24)
319#define PM_CLK_GATE_REG_OFFSET_CIM (23)
320#define PM_CLK_GATE_REG_OFFSET_LCDC (22)
321#define PM_CLK_GATE_REG_OFFSET_I2S (21)
322#define PM_CLK_GATE_REG_OFFSET_RAID (20)
323#define PM_CLK_GATE_REG_OFFSET_SATA (19)
324#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x))
325#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16)
326#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15)
327#define PM_CLK_GATE_REG_OFFSET_TIMER (14)
328#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13)
329#define PM_CLK_GATE_REG_OFFSET_HCIE (12)
330#define PM_CLK_GATE_REG_OFFSET_SWITCH (11)
331#define PM_CLK_GATE_REG_OFFSET_GPIO (10)
332#define PM_CLK_GATE_REG_OFFSET_UART3 (9)
333#define PM_CLK_GATE_REG_OFFSET_UART2 (8)
334#define PM_CLK_GATE_REG_OFFSET_UART1 (7)
335#define PM_CLK_GATE_REG_OFFSET_RTC (5)
336#define PM_CLK_GATE_REG_OFFSET_GDMA (4)
337#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3)
338#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1)
339#define PM_CLK_GATE_REG_MASK (0x03FFFFBA)
340
341/* PM_SOFT_RST_REG */
342#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31)
343#define PM_SOFT_RST_REG_OFFST_CPU1 (29)
344#define PM_SOFT_RST_REG_OFFST_CPU0 (28)
345#define PM_SOFT_RST_REG_OFFST_SDIO (25)
346#define PM_SOFT_RST_REG_OFFST_GPU (24)
347#define PM_SOFT_RST_REG_OFFST_CIM (23)
348#define PM_SOFT_RST_REG_OFFST_LCDC (22)
349#define PM_SOFT_RST_REG_OFFST_I2S (21)
350#define PM_SOFT_RST_REG_OFFST_RAID (20)
351#define PM_SOFT_RST_REG_OFFST_SATA (19)
352#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x))
353#define PM_SOFT_RST_REG_OFFST_USB_HOST (16)
354#define PM_SOFT_RST_REG_OFFST_USB_OTG (15)
355#define PM_SOFT_RST_REG_OFFST_TIMER (14)
356#define PM_SOFT_RST_REG_OFFST_CRYPTO (13)
357#define PM_SOFT_RST_REG_OFFST_HCIE (12)
358#define PM_SOFT_RST_REG_OFFST_SWITCH (11)
359#define PM_SOFT_RST_REG_OFFST_GPIO (10)
360#define PM_SOFT_RST_REG_OFFST_UART3 (9)
361#define PM_SOFT_RST_REG_OFFST_UART2 (8)
362#define PM_SOFT_RST_REG_OFFST_UART1 (7)
363#define PM_SOFT_RST_REG_OFFST_RTC (5)
364#define PM_SOFT_RST_REG_OFFST_GDMA (4)
365#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3)
366#define PM_SOFT_RST_REG_OFFST_DMC (2)
367#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1)
368#define PM_SOFT_RST_REG_OFFST_GLOBAL (0)
369#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF)
370
371/* PMHS_CFG_REG */
372#define PM_HS_CFG_REG_OFFSET_SDIO (25)
373#define PM_HS_CFG_REG_OFFSET_GPU (24)
374#define PM_HS_CFG_REG_OFFSET_CIM (23)
375#define PM_HS_CFG_REG_OFFSET_LCDC (22)
376#define PM_HS_CFG_REG_OFFSET_I2S (21)
377#define PM_HS_CFG_REG_OFFSET_RAID (20)
378#define PM_HS_CFG_REG_OFFSET_SATA (19)
379#define PM_HS_CFG_REG_OFFSET_PCIE1 (18)
380#define PM_HS_CFG_REG_OFFSET_PCIE0 (17)
381#define PM_HS_CFG_REG_OFFSET_USB_HOST (16)
382#define PM_HS_CFG_REG_OFFSET_USB_OTG (15)
383#define PM_HS_CFG_REG_OFFSET_TIMER (14)
384#define PM_HS_CFG_REG_OFFSET_CRYPTO (13)
385#define PM_HS_CFG_REG_OFFSET_HCIE (12)
386#define PM_HS_CFG_REG_OFFSET_SWITCH (11)
387#define PM_HS_CFG_REG_OFFSET_GPIO (10)
388#define PM_HS_CFG_REG_OFFSET_UART3 (9)
389#define PM_HS_CFG_REG_OFFSET_UART2 (8)
390#define PM_HS_CFG_REG_OFFSET_UART1 (7)
391#define PM_HS_CFG_REG_OFFSET_RTC (5)
392#define PM_HS_CFG_REG_OFFSET_GDMA (4)
393#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3)
394#define PM_HS_CFG_REG_OFFSET_DMC (2)
395#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1)
396#define PM_HS_CFG_REG_MASK (0x03FFFFBE)
397#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806)
398
399/* PM_CACTIVE_STA_REG */
400#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25)
401#define PM_CACTIVE_STA_REG_OFFSET_GPU (24)
402#define PM_CACTIVE_STA_REG_OFFSET_CIM (23)
403#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22)
404#define PM_CACTIVE_STA_REG_OFFSET_I2S (21)
405#define PM_CACTIVE_STA_REG_OFFSET_RAID (20)
406#define PM_CACTIVE_STA_REG_OFFSET_SATA (19)
407#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18)
408#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17)
409#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16)
410#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15)
411#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14)
412#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13)
413#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12)
414#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11)
415#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10)
416#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9)
417#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8)
418#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7)
419#define PM_CACTIVE_STA_REG_OFFSET_RTC (5)
420#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4)
421#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3)
422#define PM_CACTIVE_STA_REG_OFFSET_DMC (2)
423#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1)
424#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE)
425
426/* PM_PWR_STA_REG */
427#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25)
428#define PM_PWR_STA_REG_REG_OFFSET_GPU (24)
429#define PM_PWR_STA_REG_REG_OFFSET_CIM (23)
430#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22)
431#define PM_PWR_STA_REG_REG_OFFSET_I2S (21)
432#define PM_PWR_STA_REG_REG_OFFSET_RAID (20)
433#define PM_PWR_STA_REG_REG_OFFSET_SATA (19)
434#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18)
435#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17)
436#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16)
437#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15)
438#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14)
439#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13)
440#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12)
441#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11)
442#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10)
443#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9)
444#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8)
445#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7)
446#define PM_PWR_STA_REG_REG_OFFSET_RTC (5)
447#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4)
448#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3)
449#define PM_PWR_STA_REG_REG_OFFSET_DMC (2)
450#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1)
451#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE)
452
453/* PM_CLK_CTRL_REG */
454#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31)
455#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30)
456#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29)
457#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28)
458#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27)
459#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24)
460#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22)
461#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20)
462#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16)
463#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14)
464#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12)
465#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9)
466#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7)
467#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6)
468#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4)
469#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0)
470
471#define PM_CPU_CLK_DIV(DIV) { \
472 PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
473 PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
474}
475
476#define PM_PLL_CPU_SEL(CPU) { \
477 PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
478 PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
479}
480
481/* PM_PLL_LCD_I2S_CTRL_REG */
482#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22)
483#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17)
484#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11)
485#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3)
486#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0)
487
488/* PM_PLL_HM_PD_CTRL_REG */
489#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11)
490#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10)
491#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6)
492#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5)
493#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4)
494#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3)
495#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2)
496#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C)
497
498/* PM_WDT_CTRL_REG */
499#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0)
500
501/* PM_CSR_REG - Clock Scaling Register*/
502#define PM_CSR_REG_OFFSET_CSR_EN (30)
503#define PM_CSR_REG_OFFSET_CSR_NUM (0)
504
505#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK)
506
507/* Software reset*/
508#define CNS3XXX_PWR_SOFTWARE_RST(BLOCK) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK)
509
510/*
511 * CNS3XXX support several power saving mode as following,
512 * DFS, IDLE, HALT, DOZE, SLEEP, Hibernate
513 */
514#define CNS3XXX_PWR_CPU_MODE_DFS (0)
515#define CNS3XXX_PWR_CPU_MODE_IDLE (1)
516#define CNS3XXX_PWR_CPU_MODE_HALT (2)
517#define CNS3XXX_PWR_CPU_MODE_DOZE (3)
518#define CNS3XXX_PWR_CPU_MODE_SLEEP (4)
519#define CNS3XXX_PWR_CPU_MODE_HIBERNATE (5)
520
521#define CNS3XXX_PWR_PLL(BLOCK) (0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK)
522#define CNS3XXX_PWR_PLL_ALL PM_PLL_HM_PD_CTRL_REG_MASK
523
524/* Change CPU frequency and divider */
525#define CNS3XXX_PWR_PLL_CPU_300MHZ (0)
526#define CNS3XXX_PWR_PLL_CPU_333MHZ (1)
527#define CNS3XXX_PWR_PLL_CPU_366MHZ (2)
528#define CNS3XXX_PWR_PLL_CPU_400MHZ (3)
529#define CNS3XXX_PWR_PLL_CPU_433MHZ (4)
530#define CNS3XXX_PWR_PLL_CPU_466MHZ (5)
531#define CNS3XXX_PWR_PLL_CPU_500MHZ (6)
532#define CNS3XXX_PWR_PLL_CPU_533MHZ (7)
533#define CNS3XXX_PWR_PLL_CPU_566MHZ (8)
534#define CNS3XXX_PWR_PLL_CPU_600MHZ (9)
535#define CNS3XXX_PWR_PLL_CPU_633MHZ (10)
536#define CNS3XXX_PWR_PLL_CPU_666MHZ (11)
537#define CNS3XXX_PWR_PLL_CPU_700MHZ (12)
538
539#define CNS3XXX_PWR_CPU_CLK_DIV_BY1 (0)
540#define CNS3XXX_PWR_CPU_CLK_DIV_BY2 (1)
541#define CNS3XXX_PWR_CPU_CLK_DIV_BY4 (2)
542
543/* Change DDR2 frequency */
544#define CNS3XXX_PWR_PLL_DDR2_200MHZ (0)
545#define CNS3XXX_PWR_PLL_DDR2_266MHZ (1)
546#define CNS3XXX_PWR_PLL_DDR2_333MHZ (2)
547#define CNS3XXX_PWR_PLL_DDR2_400MHZ (3)
548
549void cns3xxx_pwr_soft_rst(unsigned int block);
550void cns3xxx_pwr_clk_en(unsigned int block);
551int cns3xxx_cpu_clock(void);
552
553/*
554 * ARM11 MPCore interrupt sources (primary GIC)
555 */
Arnd Bergmann3f9fb2a2013-03-13 13:15:25 +0100556#define IRQ_TC11MP_GIC_START 32
557
Anton Vorontsovd94f9442010-03-25 17:12:41 +0300558#define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0)
559#define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1)
560#define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2)
561#define IRQ_CNS3XXX_RTC (IRQ_TC11MP_GIC_START + 3)
562#define IRQ_CNS3XXX_I2S (IRQ_TC11MP_GIC_START + 4)
563#define IRQ_CNS3XXX_PCM (IRQ_TC11MP_GIC_START + 5)
564#define IRQ_CNS3XXX_SPI (IRQ_TC11MP_GIC_START + 6)
565#define IRQ_CNS3XXX_I2C (IRQ_TC11MP_GIC_START + 7)
566#define IRQ_CNS3XXX_CIM (IRQ_TC11MP_GIC_START + 8)
567#define IRQ_CNS3XXX_GPU (IRQ_TC11MP_GIC_START + 9)
568#define IRQ_CNS3XXX_LCD (IRQ_TC11MP_GIC_START + 10)
569#define IRQ_CNS3XXX_GPIOA (IRQ_TC11MP_GIC_START + 11)
570#define IRQ_CNS3XXX_GPIOB (IRQ_TC11MP_GIC_START + 12)
571#define IRQ_CNS3XXX_UART0 (IRQ_TC11MP_GIC_START + 13)
572#define IRQ_CNS3XXX_UART1 (IRQ_TC11MP_GIC_START + 14)
573#define IRQ_CNS3XXX_UART2 (IRQ_TC11MP_GIC_START + 15)
574#define IRQ_CNS3XXX_ARM11 (IRQ_TC11MP_GIC_START + 16)
575
576#define IRQ_CNS3XXX_SW_STATUS (IRQ_TC11MP_GIC_START + 17)
577#define IRQ_CNS3XXX_SW_R0TXC (IRQ_TC11MP_GIC_START + 18)
578#define IRQ_CNS3XXX_SW_R0RXC (IRQ_TC11MP_GIC_START + 19)
579#define IRQ_CNS3XXX_SW_R0QE (IRQ_TC11MP_GIC_START + 20)
580#define IRQ_CNS3XXX_SW_R0QF (IRQ_TC11MP_GIC_START + 21)
581#define IRQ_CNS3XXX_SW_R1TXC (IRQ_TC11MP_GIC_START + 22)
582#define IRQ_CNS3XXX_SW_R1RXC (IRQ_TC11MP_GIC_START + 23)
583#define IRQ_CNS3XXX_SW_R1QE (IRQ_TC11MP_GIC_START + 24)
584#define IRQ_CNS3XXX_SW_R1QF (IRQ_TC11MP_GIC_START + 25)
585#define IRQ_CNS3XXX_SW_PPE (IRQ_TC11MP_GIC_START + 26)
586
587#define IRQ_CNS3XXX_CRYPTO (IRQ_TC11MP_GIC_START + 27)
588#define IRQ_CNS3XXX_HCIE (IRQ_TC11MP_GIC_START + 28)
589#define IRQ_CNS3XXX_PCIE0_DEVICE (IRQ_TC11MP_GIC_START + 29)
590#define IRQ_CNS3XXX_PCIE1_DEVICE (IRQ_TC11MP_GIC_START + 30)
591#define IRQ_CNS3XXX_USB_OTG (IRQ_TC11MP_GIC_START + 31)
592#define IRQ_CNS3XXX_USB_EHCI (IRQ_TC11MP_GIC_START + 32)
593#define IRQ_CNS3XXX_SATA (IRQ_TC11MP_GIC_START + 33)
594#define IRQ_CNS3XXX_RAID (IRQ_TC11MP_GIC_START + 34)
595#define IRQ_CNS3XXX_SMC (IRQ_TC11MP_GIC_START + 35)
596
597#define IRQ_CNS3XXX_DMAC_ABORT (IRQ_TC11MP_GIC_START + 36)
598#define IRQ_CNS3XXX_DMAC0 (IRQ_TC11MP_GIC_START + 37)
599#define IRQ_CNS3XXX_DMAC1 (IRQ_TC11MP_GIC_START + 38)
600#define IRQ_CNS3XXX_DMAC2 (IRQ_TC11MP_GIC_START + 39)
601#define IRQ_CNS3XXX_DMAC3 (IRQ_TC11MP_GIC_START + 40)
602#define IRQ_CNS3XXX_DMAC4 (IRQ_TC11MP_GIC_START + 41)
603#define IRQ_CNS3XXX_DMAC5 (IRQ_TC11MP_GIC_START + 42)
604#define IRQ_CNS3XXX_DMAC6 (IRQ_TC11MP_GIC_START + 43)
605#define IRQ_CNS3XXX_DMAC7 (IRQ_TC11MP_GIC_START + 44)
606#define IRQ_CNS3XXX_DMAC8 (IRQ_TC11MP_GIC_START + 45)
607#define IRQ_CNS3XXX_DMAC9 (IRQ_TC11MP_GIC_START + 46)
608#define IRQ_CNS3XXX_DMAC10 (IRQ_TC11MP_GIC_START + 47)
609#define IRQ_CNS3XXX_DMAC11 (IRQ_TC11MP_GIC_START + 48)
610#define IRQ_CNS3XXX_DMAC12 (IRQ_TC11MP_GIC_START + 49)
611#define IRQ_CNS3XXX_DMAC13 (IRQ_TC11MP_GIC_START + 50)
612#define IRQ_CNS3XXX_DMAC14 (IRQ_TC11MP_GIC_START + 51)
613#define IRQ_CNS3XXX_DMAC15 (IRQ_TC11MP_GIC_START + 52)
614#define IRQ_CNS3XXX_DMAC16 (IRQ_TC11MP_GIC_START + 53)
615#define IRQ_CNS3XXX_DMAC17 (IRQ_TC11MP_GIC_START + 54)
616
617#define IRQ_CNS3XXX_PCIE0_RC (IRQ_TC11MP_GIC_START + 55)
618#define IRQ_CNS3XXX_PCIE1_RC (IRQ_TC11MP_GIC_START + 56)
619#define IRQ_CNS3XXX_TIMER0 (IRQ_TC11MP_GIC_START + 57)
620#define IRQ_CNS3XXX_TIMER1 (IRQ_TC11MP_GIC_START + 58)
621#define IRQ_CNS3XXX_USB_OHCI (IRQ_TC11MP_GIC_START + 59)
622#define IRQ_CNS3XXX_TIMER2 (IRQ_TC11MP_GIC_START + 60)
623#define IRQ_CNS3XXX_EXTERNAL_PIN0 (IRQ_TC11MP_GIC_START + 61)
624#define IRQ_CNS3XXX_EXTERNAL_PIN1 (IRQ_TC11MP_GIC_START + 62)
625#define IRQ_CNS3XXX_EXTERNAL_PIN2 (IRQ_TC11MP_GIC_START + 63)
626
627#define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64)
628
Anton Vorontsovd94f9442010-03-25 17:12:41 +0300629#endif /* __MACH_BOARD_CNS3XXX_H */