Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family |
| 3 | * of PCI-SCSI IO processors. |
| 4 | * |
| 5 | * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> |
| 6 | * |
| 7 | * This driver is derived from the Linux sym53c8xx driver. |
| 8 | * Copyright (C) 1998-2000 Gerard Roudier |
| 9 | * |
| 10 | * The sym53c8xx driver is derived from the ncr53c8xx driver that had been |
| 11 | * a port of the FreeBSD ncr driver to Linux-1.2.13. |
| 12 | * |
| 13 | * The original ncr driver has been written for 386bsd and FreeBSD by |
| 14 | * Wolfgang Stanglmeier <wolf@cologne.de> |
| 15 | * Stefan Esser <se@mi.Uni-Koeln.de> |
| 16 | * Copyright (C) 1994 Wolfgang Stanglmeier |
| 17 | * |
| 18 | * Other major contributions: |
| 19 | * |
| 20 | * NVRAM detection and reading. |
| 21 | * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> |
| 22 | * |
| 23 | *----------------------------------------------------------------------------- |
| 24 | * |
| 25 | * This program is free software; you can redistribute it and/or modify |
| 26 | * it under the terms of the GNU General Public License as published by |
| 27 | * the Free Software Foundation; either version 2 of the License, or |
| 28 | * (at your option) any later version. |
| 29 | * |
| 30 | * This program is distributed in the hope that it will be useful, |
| 31 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 32 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 33 | * GNU General Public License for more details. |
| 34 | * |
| 35 | * You should have received a copy of the GNU General Public License |
| 36 | * along with this program; if not, write to the Free Software |
| 37 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 38 | */ |
| 39 | |
| 40 | /* |
| 41 | * Scripts for SYMBIOS-Processor |
| 42 | * |
| 43 | * We have to know the offsets of all labels before we reach |
| 44 | * them (for forward jumps). Therefore we declare a struct |
| 45 | * here. If you make changes inside the script, |
| 46 | * |
| 47 | * DONT FORGET TO CHANGE THE LENGTHS HERE! |
| 48 | */ |
| 49 | |
| 50 | /* |
| 51 | * Script fragments which are loaded into the on-chip RAM |
| 52 | * of 825A, 875, 876, 895, 895A, 896 and 1010 chips. |
| 53 | * Must not exceed 4K bytes. |
| 54 | */ |
| 55 | struct SYM_FWA_SCR { |
| 56 | u32 start [ 14]; |
| 57 | u32 getjob_begin [ 4]; |
| 58 | u32 getjob_end [ 4]; |
| 59 | #ifdef SYM_CONF_TARGET_ROLE_SUPPORT |
| 60 | u32 select [ 6]; |
| 61 | #else |
| 62 | u32 select [ 4]; |
| 63 | #endif |
| 64 | #if SYM_CONF_DMA_ADDRESSING_MODE == 2 |
| 65 | u32 is_dmap_dirty [ 4]; |
| 66 | #endif |
| 67 | u32 wf_sel_done [ 2]; |
| 68 | u32 sel_done [ 2]; |
| 69 | u32 send_ident [ 2]; |
| 70 | #ifdef SYM_CONF_IARB_SUPPORT |
| 71 | u32 select2 [ 8]; |
| 72 | #else |
| 73 | u32 select2 [ 2]; |
| 74 | #endif |
| 75 | u32 command [ 2]; |
| 76 | u32 dispatch [ 28]; |
| 77 | u32 sel_no_cmd [ 10]; |
| 78 | u32 init [ 6]; |
| 79 | u32 clrack [ 4]; |
| 80 | u32 datai_done [ 10]; |
| 81 | u32 datai_done_wsr [ 20]; |
| 82 | u32 datao_done [ 10]; |
| 83 | u32 datao_done_wss [ 6]; |
| 84 | u32 datai_phase [ 4]; |
| 85 | u32 datao_phase [ 6]; |
| 86 | u32 msg_in [ 2]; |
| 87 | u32 msg_in2 [ 10]; |
| 88 | #ifdef SYM_CONF_IARB_SUPPORT |
| 89 | u32 status [ 14]; |
| 90 | #else |
| 91 | u32 status [ 10]; |
| 92 | #endif |
| 93 | u32 complete [ 6]; |
| 94 | u32 complete2 [ 12]; |
| 95 | u32 done [ 14]; |
| 96 | u32 done_end [ 2]; |
| 97 | u32 complete_error [ 4]; |
| 98 | u32 save_dp [ 12]; |
| 99 | u32 restore_dp [ 8]; |
| 100 | u32 disconnect [ 12]; |
| 101 | #ifdef SYM_CONF_IARB_SUPPORT |
| 102 | u32 idle [ 4]; |
| 103 | #else |
| 104 | u32 idle [ 2]; |
| 105 | #endif |
| 106 | #ifdef SYM_CONF_IARB_SUPPORT |
| 107 | u32 ungetjob [ 6]; |
| 108 | #else |
| 109 | u32 ungetjob [ 4]; |
| 110 | #endif |
| 111 | #ifdef SYM_CONF_TARGET_ROLE_SUPPORT |
| 112 | u32 reselect [ 4]; |
| 113 | #else |
| 114 | u32 reselect [ 2]; |
| 115 | #endif |
| 116 | u32 reselected [ 22]; |
| 117 | u32 resel_scntl4 [ 20]; |
| 118 | u32 resel_lun0 [ 6]; |
| 119 | #if SYM_CONF_MAX_TASK*4 > 512 |
| 120 | u32 resel_tag [ 26]; |
| 121 | #elif SYM_CONF_MAX_TASK*4 > 256 |
| 122 | u32 resel_tag [ 20]; |
| 123 | #else |
| 124 | u32 resel_tag [ 16]; |
| 125 | #endif |
| 126 | u32 resel_dsa [ 2]; |
| 127 | u32 resel_dsa1 [ 4]; |
| 128 | u32 resel_no_tag [ 6]; |
| 129 | u32 data_in [SYM_CONF_MAX_SG * 2]; |
| 130 | u32 data_in2 [ 4]; |
| 131 | u32 data_out [SYM_CONF_MAX_SG * 2]; |
| 132 | u32 data_out2 [ 4]; |
| 133 | u32 pm0_data [ 12]; |
| 134 | u32 pm0_data_out [ 6]; |
| 135 | u32 pm0_data_end [ 6]; |
| 136 | u32 pm1_data [ 12]; |
| 137 | u32 pm1_data_out [ 6]; |
| 138 | u32 pm1_data_end [ 6]; |
| 139 | }; |
| 140 | |
| 141 | /* |
| 142 | * Script fragments which stay in main memory for all chips |
| 143 | * except for chips that support 8K on-chip RAM. |
| 144 | */ |
| 145 | struct SYM_FWB_SCR { |
| 146 | u32 start64 [ 2]; |
| 147 | u32 no_data [ 2]; |
| 148 | #ifdef SYM_CONF_TARGET_ROLE_SUPPORT |
| 149 | u32 sel_for_abort [ 18]; |
| 150 | #else |
| 151 | u32 sel_for_abort [ 16]; |
| 152 | #endif |
| 153 | u32 sel_for_abort_1 [ 2]; |
| 154 | u32 msg_in_etc [ 12]; |
| 155 | u32 msg_received [ 4]; |
| 156 | u32 msg_weird_seen [ 4]; |
| 157 | u32 msg_extended [ 20]; |
| 158 | u32 msg_bad [ 6]; |
| 159 | u32 msg_weird [ 4]; |
| 160 | u32 msg_weird1 [ 8]; |
| 161 | |
| 162 | u32 wdtr_resp [ 6]; |
| 163 | u32 send_wdtr [ 4]; |
| 164 | u32 sdtr_resp [ 6]; |
| 165 | u32 send_sdtr [ 4]; |
| 166 | u32 ppr_resp [ 6]; |
| 167 | u32 send_ppr [ 4]; |
| 168 | u32 nego_bad_phase [ 4]; |
| 169 | u32 msg_out [ 4]; |
| 170 | u32 msg_out_done [ 4]; |
| 171 | u32 data_ovrun [ 2]; |
| 172 | u32 data_ovrun1 [ 22]; |
| 173 | u32 data_ovrun2 [ 8]; |
| 174 | u32 abort_resel [ 16]; |
| 175 | u32 resend_ident [ 4]; |
| 176 | u32 ident_break [ 4]; |
| 177 | u32 ident_break_atn [ 4]; |
| 178 | u32 sdata_in [ 6]; |
| 179 | u32 resel_bad_lun [ 4]; |
| 180 | u32 bad_i_t_l [ 4]; |
| 181 | u32 bad_i_t_l_q [ 4]; |
| 182 | u32 bad_status [ 6]; |
| 183 | u32 pm_handle [ 20]; |
| 184 | u32 pm_handle1 [ 4]; |
| 185 | u32 pm_save [ 4]; |
| 186 | u32 pm0_save [ 12]; |
| 187 | u32 pm_save_end [ 4]; |
| 188 | u32 pm1_save [ 14]; |
| 189 | |
| 190 | /* WSR handling */ |
| 191 | u32 pm_wsr_handle [ 38]; |
| 192 | u32 wsr_ma_helper [ 4]; |
| 193 | |
| 194 | #ifdef SYM_OPT_HANDLE_DIR_UNKNOWN |
| 195 | /* Unknown direction handling */ |
| 196 | u32 data_io [ 2]; |
| 197 | u32 data_io_in [ 2]; |
| 198 | u32 data_io_com [ 6]; |
| 199 | u32 data_io_out [ 8]; |
| 200 | #endif |
| 201 | /* Data area */ |
| 202 | u32 zero [ 1]; |
| 203 | u32 scratch [ 1]; |
| 204 | u32 pm0_data_addr [ 1]; |
| 205 | u32 pm1_data_addr [ 1]; |
| 206 | u32 done_pos [ 1]; |
| 207 | u32 startpos [ 1]; |
| 208 | u32 targtbl [ 1]; |
| 209 | }; |
| 210 | |
| 211 | /* |
| 212 | * Script fragments used at initialisations. |
| 213 | * Only runs out of main memory. |
| 214 | */ |
| 215 | struct SYM_FWZ_SCR { |
| 216 | u32 snooptest [ 6]; |
| 217 | u32 snoopend [ 2]; |
| 218 | }; |
| 219 | |
| 220 | static struct SYM_FWA_SCR SYM_FWA_SCR = { |
| 221 | /*--------------------------< START >----------------------------*/ { |
| 222 | /* |
| 223 | * Switch the LED on. |
| 224 | * Will be patched with a NO_OP if LED |
| 225 | * not needed or not desired. |
| 226 | */ |
| 227 | SCR_REG_REG (gpreg, SCR_AND, 0xfe), |
| 228 | 0, |
| 229 | /* |
| 230 | * Clear SIGP. |
| 231 | */ |
| 232 | SCR_FROM_REG (ctest2), |
| 233 | 0, |
| 234 | /* |
| 235 | * Stop here if the C code wants to perform |
| 236 | * some error recovery procedure manually. |
| 237 | * (Indicate this by setting SEM in ISTAT) |
| 238 | */ |
| 239 | SCR_FROM_REG (istat), |
| 240 | 0, |
| 241 | /* |
| 242 | * Report to the C code the next position in |
| 243 | * the start queue the SCRIPTS will schedule. |
| 244 | * The C code must not change SCRATCHA. |
| 245 | */ |
| 246 | SCR_LOAD_ABS (scratcha, 4), |
| 247 | PADDR_B (startpos), |
| 248 | SCR_INT ^ IFTRUE (MASK (SEM, SEM)), |
| 249 | SIR_SCRIPT_STOPPED, |
| 250 | /* |
| 251 | * Start the next job. |
| 252 | * |
| 253 | * @DSA = start point for this job. |
| 254 | * SCRATCHA = address of this job in the start queue. |
| 255 | * |
| 256 | * We will restore startpos with SCRATCHA if we fails the |
| 257 | * arbitration or if it is the idle job. |
| 258 | * |
| 259 | * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS |
| 260 | * is a critical path. If it is partially executed, it then |
| 261 | * may happen that the job address is not yet in the DSA |
| 262 | * and the next queue position points to the next JOB. |
| 263 | */ |
| 264 | SCR_LOAD_ABS (dsa, 4), |
| 265 | PADDR_B (startpos), |
| 266 | SCR_LOAD_REL (temp, 4), |
| 267 | 4, |
| 268 | }/*-------------------------< GETJOB_BEGIN >---------------------*/,{ |
| 269 | SCR_STORE_ABS (temp, 4), |
| 270 | PADDR_B (startpos), |
| 271 | SCR_LOAD_REL (dsa, 4), |
| 272 | 0, |
| 273 | }/*-------------------------< GETJOB_END >-----------------------*/,{ |
| 274 | SCR_LOAD_REL (temp, 4), |
| 275 | 0, |
| 276 | SCR_RETURN, |
| 277 | 0, |
| 278 | }/*-------------------------< SELECT >---------------------------*/,{ |
| 279 | /* |
| 280 | * DSA contains the address of a scheduled |
| 281 | * data structure. |
| 282 | * |
| 283 | * SCRATCHA contains the address of the start queue |
| 284 | * entry which points to the next job. |
| 285 | * |
| 286 | * Set Initiator mode. |
| 287 | * |
| 288 | * (Target mode is left as an exercise for the reader) |
| 289 | */ |
| 290 | #ifdef SYM_CONF_TARGET_ROLE_SUPPORT |
| 291 | SCR_CLR (SCR_TRG), |
| 292 | 0, |
| 293 | #endif |
| 294 | /* |
| 295 | * And try to select this target. |
| 296 | */ |
| 297 | SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select), |
| 298 | PADDR_A (ungetjob), |
| 299 | /* |
| 300 | * Now there are 4 possibilities: |
| 301 | * |
| 302 | * (1) The chip loses arbitration. |
| 303 | * This is ok, because it will try again, |
| 304 | * when the bus becomes idle. |
| 305 | * (But beware of the timeout function!) |
| 306 | * |
| 307 | * (2) The chip is reselected. |
| 308 | * Then the script processor takes the jump |
| 309 | * to the RESELECT label. |
| 310 | * |
| 311 | * (3) The chip wins arbitration. |
| 312 | * Then it will execute SCRIPTS instruction until |
| 313 | * the next instruction that checks SCSI phase. |
| 314 | * Then will stop and wait for selection to be |
| 315 | * complete or selection time-out to occur. |
| 316 | * |
| 317 | * After having won arbitration, the SCRIPTS |
| 318 | * processor is able to execute instructions while |
| 319 | * the SCSI core is performing SCSI selection. |
| 320 | */ |
| 321 | /* |
| 322 | * Initialize the status registers |
| 323 | */ |
| 324 | SCR_LOAD_REL (scr0, 4), |
| 325 | offsetof (struct sym_ccb, phys.head.status), |
| 326 | /* |
| 327 | * We may need help from CPU if the DMA segment |
| 328 | * registers aren't up-to-date for this IO. |
| 329 | * Patched with NOOP for chips that donnot |
| 330 | * support DAC addressing. |
| 331 | */ |
| 332 | #if SYM_CONF_DMA_ADDRESSING_MODE == 2 |
| 333 | }/*-------------------------< IS_DMAP_DIRTY >--------------------*/,{ |
| 334 | SCR_FROM_REG (HX_REG), |
| 335 | 0, |
| 336 | SCR_INT ^ IFTRUE (MASK (HX_DMAP_DIRTY, HX_DMAP_DIRTY)), |
| 337 | SIR_DMAP_DIRTY, |
| 338 | #endif |
| 339 | }/*-------------------------< WF_SEL_DONE >----------------------*/,{ |
| 340 | SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)), |
| 341 | SIR_SEL_ATN_NO_MSG_OUT, |
| 342 | }/*-------------------------< SEL_DONE >-------------------------*/,{ |
| 343 | /* |
| 344 | * C1010-33 errata work-around. |
| 345 | * Due to a race, the SCSI core may not have |
| 346 | * loaded SCNTL3 on SEL_TBL instruction. |
| 347 | * We reload it once phase is stable. |
| 348 | * Patched with a NOOP for other chips. |
| 349 | */ |
| 350 | SCR_LOAD_REL (scntl3, 1), |
| 351 | offsetof(struct sym_dsb, select.sel_scntl3), |
| 352 | }/*-------------------------< SEND_IDENT >-----------------------*/,{ |
| 353 | /* |
| 354 | * Selection complete. |
| 355 | * Send the IDENTIFY and possibly the TAG message |
| 356 | * and negotiation message if present. |
| 357 | */ |
| 358 | SCR_MOVE_TBL ^ SCR_MSG_OUT, |
| 359 | offsetof (struct sym_dsb, smsg), |
| 360 | }/*-------------------------< SELECT2 >--------------------------*/,{ |
| 361 | #ifdef SYM_CONF_IARB_SUPPORT |
| 362 | /* |
| 363 | * Set IMMEDIATE ARBITRATION if we have been given |
| 364 | * a hint to do so. (Some job to do after this one). |
| 365 | */ |
| 366 | SCR_FROM_REG (HF_REG), |
| 367 | 0, |
| 368 | SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)), |
| 369 | 8, |
| 370 | SCR_REG_REG (scntl1, SCR_OR, IARB), |
| 371 | 0, |
| 372 | #endif |
| 373 | /* |
| 374 | * Anticipate the COMMAND phase. |
| 375 | * This is the PHASE we expect at this point. |
| 376 | */ |
| 377 | SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)), |
| 378 | PADDR_A (sel_no_cmd), |
| 379 | }/*-------------------------< COMMAND >--------------------------*/,{ |
| 380 | /* |
| 381 | * ... and send the command |
| 382 | */ |
| 383 | SCR_MOVE_TBL ^ SCR_COMMAND, |
| 384 | offsetof (struct sym_dsb, cmd), |
| 385 | }/*-------------------------< DISPATCH >-------------------------*/,{ |
| 386 | /* |
| 387 | * MSG_IN is the only phase that shall be |
| 388 | * entered at least once for each (re)selection. |
| 389 | * So we test it first. |
| 390 | */ |
| 391 | SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), |
| 392 | PADDR_A (msg_in), |
| 393 | SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)), |
| 394 | PADDR_A (datao_phase), |
| 395 | SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)), |
| 396 | PADDR_A (datai_phase), |
| 397 | SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)), |
| 398 | PADDR_A (status), |
| 399 | SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)), |
| 400 | PADDR_A (command), |
| 401 | SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)), |
| 402 | PADDR_B (msg_out), |
| 403 | /* |
| 404 | * Discard as many illegal phases as |
| 405 | * required and tell the C code about. |
| 406 | */ |
| 407 | SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)), |
| 408 | 16, |
| 409 | SCR_MOVE_ABS (1) ^ SCR_ILG_OUT, |
| 410 | HADDR_1 (scratch), |
| 411 | SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)), |
| 412 | -16, |
| 413 | SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)), |
| 414 | 16, |
| 415 | SCR_MOVE_ABS (1) ^ SCR_ILG_IN, |
| 416 | HADDR_1 (scratch), |
| 417 | SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)), |
| 418 | -16, |
| 419 | SCR_INT, |
| 420 | SIR_BAD_PHASE, |
| 421 | SCR_JUMP, |
| 422 | PADDR_A (dispatch), |
| 423 | }/*-------------------------< SEL_NO_CMD >-----------------------*/,{ |
| 424 | /* |
| 425 | * The target does not switch to command |
| 426 | * phase after IDENTIFY has been sent. |
| 427 | * |
| 428 | * If it stays in MSG OUT phase send it |
| 429 | * the IDENTIFY again. |
| 430 | */ |
| 431 | SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), |
| 432 | PADDR_B (resend_ident), |
| 433 | /* |
| 434 | * If target does not switch to MSG IN phase |
| 435 | * and we sent a negotiation, assert the |
| 436 | * failure immediately. |
| 437 | */ |
| 438 | SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), |
| 439 | PADDR_A (dispatch), |
| 440 | SCR_FROM_REG (HS_REG), |
| 441 | 0, |
| 442 | SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)), |
| 443 | SIR_NEGO_FAILED, |
| 444 | /* |
| 445 | * Jump to dispatcher. |
| 446 | */ |
| 447 | SCR_JUMP, |
| 448 | PADDR_A (dispatch), |
| 449 | }/*-------------------------< INIT >-----------------------------*/,{ |
| 450 | /* |
| 451 | * Wait for the SCSI RESET signal to be |
| 452 | * inactive before restarting operations, |
| 453 | * since the chip may hang on SEL_ATN |
| 454 | * if SCSI RESET is active. |
| 455 | */ |
| 456 | SCR_FROM_REG (sstat0), |
| 457 | 0, |
| 458 | SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)), |
| 459 | -16, |
| 460 | SCR_JUMP, |
| 461 | PADDR_A (start), |
| 462 | }/*-------------------------< CLRACK >---------------------------*/,{ |
| 463 | /* |
| 464 | * Terminate possible pending message phase. |
| 465 | */ |
| 466 | SCR_CLR (SCR_ACK), |
| 467 | 0, |
| 468 | SCR_JUMP, |
| 469 | PADDR_A (dispatch), |
| 470 | }/*-------------------------< DATAI_DONE >-----------------------*/,{ |
| 471 | /* |
| 472 | * Save current pointer to LASTP. |
| 473 | */ |
| 474 | SCR_STORE_REL (temp, 4), |
| 475 | offsetof (struct sym_ccb, phys.head.lastp), |
| 476 | /* |
| 477 | * If the SWIDE is not full, jump to dispatcher. |
| 478 | * We anticipate a STATUS phase. |
| 479 | */ |
| 480 | SCR_FROM_REG (scntl2), |
| 481 | 0, |
| 482 | SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)), |
| 483 | PADDR_A (datai_done_wsr), |
| 484 | SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)), |
| 485 | PADDR_A (status), |
| 486 | SCR_JUMP, |
| 487 | PADDR_A (dispatch), |
| 488 | }/*-------------------------< DATAI_DONE_WSR >-------------------*/,{ |
| 489 | /* |
| 490 | * The SWIDE is full. |
| 491 | * Clear this condition. |
| 492 | */ |
| 493 | SCR_REG_REG (scntl2, SCR_OR, WSR), |
| 494 | 0, |
| 495 | /* |
| 496 | * We are expecting an IGNORE RESIDUE message |
| 497 | * from the device, otherwise we are in data |
| 498 | * overrun condition. Check against MSG_IN phase. |
| 499 | */ |
| 500 | SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), |
| 501 | SIR_SWIDE_OVERRUN, |
| 502 | SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), |
| 503 | PADDR_A (dispatch), |
| 504 | /* |
| 505 | * We are in MSG_IN phase, |
| 506 | * Read the first byte of the message. |
| 507 | * If it is not an IGNORE RESIDUE message, |
| 508 | * signal overrun and jump to message |
| 509 | * processing. |
| 510 | */ |
| 511 | SCR_MOVE_ABS (1) ^ SCR_MSG_IN, |
| 512 | HADDR_1 (msgin[0]), |
| 513 | SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)), |
| 514 | SIR_SWIDE_OVERRUN, |
| 515 | SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)), |
| 516 | PADDR_A (msg_in2), |
| 517 | /* |
| 518 | * We got the message we expected. |
| 519 | * Read the 2nd byte, and jump to dispatcher. |
| 520 | */ |
| 521 | SCR_CLR (SCR_ACK), |
| 522 | 0, |
| 523 | SCR_MOVE_ABS (1) ^ SCR_MSG_IN, |
| 524 | HADDR_1 (msgin[1]), |
| 525 | SCR_CLR (SCR_ACK), |
| 526 | 0, |
| 527 | SCR_JUMP, |
| 528 | PADDR_A (dispatch), |
| 529 | }/*-------------------------< DATAO_DONE >-----------------------*/,{ |
| 530 | /* |
| 531 | * Save current pointer to LASTP. |
| 532 | */ |
| 533 | SCR_STORE_REL (temp, 4), |
| 534 | offsetof (struct sym_ccb, phys.head.lastp), |
| 535 | /* |
| 536 | * If the SODL is not full jump to dispatcher. |
| 537 | * We anticipate a STATUS phase. |
| 538 | */ |
| 539 | SCR_FROM_REG (scntl2), |
| 540 | 0, |
| 541 | SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)), |
| 542 | PADDR_A (datao_done_wss), |
| 543 | SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)), |
| 544 | PADDR_A (status), |
| 545 | SCR_JUMP, |
| 546 | PADDR_A (dispatch), |
| 547 | }/*-------------------------< DATAO_DONE_WSS >-------------------*/,{ |
| 548 | /* |
| 549 | * The SODL is full, clear this condition. |
| 550 | */ |
| 551 | SCR_REG_REG (scntl2, SCR_OR, WSS), |
| 552 | 0, |
| 553 | /* |
| 554 | * And signal a DATA UNDERRUN condition |
| 555 | * to the C code. |
| 556 | */ |
| 557 | SCR_INT, |
| 558 | SIR_SODL_UNDERRUN, |
| 559 | SCR_JUMP, |
| 560 | PADDR_A (dispatch), |
| 561 | }/*-------------------------< DATAI_PHASE >----------------------*/,{ |
| 562 | /* |
| 563 | * Jump to current pointer. |
| 564 | */ |
| 565 | SCR_LOAD_REL (temp, 4), |
| 566 | offsetof (struct sym_ccb, phys.head.lastp), |
| 567 | SCR_RETURN, |
| 568 | 0, |
| 569 | }/*-------------------------< DATAO_PHASE >----------------------*/,{ |
| 570 | /* |
| 571 | * C1010-66 errata work-around. |
| 572 | * Extra clocks of data hold must be inserted |
| 573 | * in DATA OUT phase on 33 MHz PCI BUS. |
| 574 | * Patched with a NOOP for other chips. |
| 575 | */ |
| 576 | SCR_REG_REG (scntl4, SCR_OR, (XCLKH_DT|XCLKH_ST)), |
| 577 | 0, |
| 578 | /* |
| 579 | * Jump to current pointer. |
| 580 | */ |
| 581 | SCR_LOAD_REL (temp, 4), |
| 582 | offsetof (struct sym_ccb, phys.head.lastp), |
| 583 | SCR_RETURN, |
| 584 | 0, |
| 585 | }/*-------------------------< MSG_IN >---------------------------*/,{ |
| 586 | /* |
| 587 | * Get the first byte of the message. |
| 588 | * |
| 589 | * The script processor doesn't negate the |
| 590 | * ACK signal after this transfer. |
| 591 | */ |
| 592 | SCR_MOVE_ABS (1) ^ SCR_MSG_IN, |
| 593 | HADDR_1 (msgin[0]), |
| 594 | }/*-------------------------< MSG_IN2 >--------------------------*/,{ |
| 595 | /* |
| 596 | * Check first against 1 byte messages |
| 597 | * that we handle from SCRIPTS. |
| 598 | */ |
| 599 | SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)), |
| 600 | PADDR_A (complete), |
| 601 | SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)), |
| 602 | PADDR_A (disconnect), |
| 603 | SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)), |
| 604 | PADDR_A (save_dp), |
| 605 | SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)), |
| 606 | PADDR_A (restore_dp), |
| 607 | /* |
| 608 | * We handle all other messages from the |
| 609 | * C code, so no need to waste on-chip RAM |
| 610 | * for those ones. |
| 611 | */ |
| 612 | SCR_JUMP, |
| 613 | PADDR_B (msg_in_etc), |
| 614 | }/*-------------------------< STATUS >---------------------------*/,{ |
| 615 | /* |
| 616 | * get the status |
| 617 | */ |
| 618 | SCR_MOVE_ABS (1) ^ SCR_STATUS, |
| 619 | HADDR_1 (scratch), |
| 620 | #ifdef SYM_CONF_IARB_SUPPORT |
| 621 | /* |
| 622 | * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION, |
| 623 | * since we may have to tamper the start queue from |
| 624 | * the C code. |
| 625 | */ |
| 626 | SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)), |
| 627 | 8, |
| 628 | SCR_REG_REG (scntl1, SCR_AND, ~IARB), |
| 629 | 0, |
| 630 | #endif |
| 631 | /* |
| 632 | * save status to scsi_status. |
| 633 | * mark as complete. |
| 634 | */ |
| 635 | SCR_TO_REG (SS_REG), |
| 636 | 0, |
| 637 | SCR_LOAD_REG (HS_REG, HS_COMPLETE), |
| 638 | 0, |
| 639 | /* |
| 640 | * Anticipate the MESSAGE PHASE for |
| 641 | * the TASK COMPLETE message. |
| 642 | */ |
| 643 | SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), |
| 644 | PADDR_A (msg_in), |
| 645 | SCR_JUMP, |
| 646 | PADDR_A (dispatch), |
| 647 | }/*-------------------------< COMPLETE >-------------------------*/,{ |
| 648 | /* |
| 649 | * Complete message. |
| 650 | * |
| 651 | * When we terminate the cycle by clearing ACK, |
| 652 | * the target may disconnect immediately. |
| 653 | * |
| 654 | * We don't want to be told of an "unexpected disconnect", |
| 655 | * so we disable this feature. |
| 656 | */ |
| 657 | SCR_REG_REG (scntl2, SCR_AND, 0x7f), |
| 658 | 0, |
| 659 | /* |
| 660 | * Terminate cycle ... |
| 661 | */ |
| 662 | SCR_CLR (SCR_ACK|SCR_ATN), |
| 663 | 0, |
| 664 | /* |
| 665 | * ... and wait for the disconnect. |
| 666 | */ |
| 667 | SCR_WAIT_DISC, |
| 668 | 0, |
| 669 | }/*-------------------------< COMPLETE2 >------------------------*/,{ |
| 670 | /* |
| 671 | * Save host status. |
| 672 | */ |
| 673 | SCR_STORE_REL (scr0, 4), |
| 674 | offsetof (struct sym_ccb, phys.head.status), |
| 675 | /* |
| 676 | * Some bridges may reorder DMA writes to memory. |
| 677 | * We donnot want the CPU to deal with completions |
| 678 | * without all the posted write having been flushed |
| 679 | * to memory. This DUMMY READ should flush posted |
| 680 | * buffers prior to the CPU having to deal with |
| 681 | * completions. |
| 682 | */ |
| 683 | SCR_LOAD_REL (scr0, 4), /* DUMMY READ */ |
| 684 | offsetof (struct sym_ccb, phys.head.status), |
| 685 | |
| 686 | /* |
| 687 | * If command resulted in not GOOD status, |
| 688 | * call the C code if needed. |
| 689 | */ |
| 690 | SCR_FROM_REG (SS_REG), |
| 691 | 0, |
| 692 | SCR_CALL ^ IFFALSE (DATA (S_GOOD)), |
| 693 | PADDR_B (bad_status), |
| 694 | /* |
| 695 | * If we performed an auto-sense, call |
| 696 | * the C code to synchronyze task aborts |
| 697 | * with UNIT ATTENTION conditions. |
| 698 | */ |
| 699 | SCR_FROM_REG (HF_REG), |
| 700 | 0, |
| 701 | SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))), |
| 702 | PADDR_A (complete_error), |
| 703 | }/*-------------------------< DONE >-----------------------------*/,{ |
| 704 | /* |
| 705 | * Copy the DSA to the DONE QUEUE and |
| 706 | * signal completion to the host. |
| 707 | * If we are interrupted between DONE |
| 708 | * and DONE_END, we must reset, otherwise |
| 709 | * the completed CCB may be lost. |
| 710 | */ |
| 711 | SCR_STORE_ABS (dsa, 4), |
| 712 | PADDR_B (scratch), |
| 713 | SCR_LOAD_ABS (dsa, 4), |
| 714 | PADDR_B (done_pos), |
| 715 | SCR_LOAD_ABS (scratcha, 4), |
| 716 | PADDR_B (scratch), |
| 717 | SCR_STORE_REL (scratcha, 4), |
| 718 | 0, |
| 719 | /* |
| 720 | * The instruction below reads the DONE QUEUE next |
| 721 | * free position from memory. |
| 722 | * In addition it ensures that all PCI posted writes |
| 723 | * are flushed and so the DSA value of the done |
| 724 | * CCB is visible by the CPU before INTFLY is raised. |
| 725 | */ |
| 726 | SCR_LOAD_REL (scratcha, 4), |
| 727 | 4, |
| 728 | SCR_INT_FLY, |
| 729 | 0, |
| 730 | SCR_STORE_ABS (scratcha, 4), |
| 731 | PADDR_B (done_pos), |
| 732 | }/*-------------------------< DONE_END >-------------------------*/,{ |
| 733 | SCR_JUMP, |
| 734 | PADDR_A (start), |
| 735 | }/*-------------------------< COMPLETE_ERROR >-------------------*/,{ |
| 736 | SCR_LOAD_ABS (scratcha, 4), |
| 737 | PADDR_B (startpos), |
| 738 | SCR_INT, |
| 739 | SIR_COMPLETE_ERROR, |
| 740 | }/*-------------------------< SAVE_DP >--------------------------*/,{ |
| 741 | /* |
| 742 | * Clear ACK immediately. |
| 743 | * No need to delay it. |
| 744 | */ |
| 745 | SCR_CLR (SCR_ACK), |
| 746 | 0, |
| 747 | /* |
| 748 | * Keep track we received a SAVE DP, so |
| 749 | * we will switch to the other PM context |
| 750 | * on the next PM since the DP may point |
| 751 | * to the current PM context. |
| 752 | */ |
| 753 | SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED), |
| 754 | 0, |
| 755 | /* |
| 756 | * SAVE_DP message: |
| 757 | * Copy LASTP to SAVEP. |
| 758 | */ |
| 759 | SCR_LOAD_REL (scratcha, 4), |
| 760 | offsetof (struct sym_ccb, phys.head.lastp), |
| 761 | SCR_STORE_REL (scratcha, 4), |
| 762 | offsetof (struct sym_ccb, phys.head.savep), |
| 763 | /* |
| 764 | * Anticipate the MESSAGE PHASE for |
| 765 | * the DISCONNECT message. |
| 766 | */ |
| 767 | SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)), |
| 768 | PADDR_A (msg_in), |
| 769 | SCR_JUMP, |
| 770 | PADDR_A (dispatch), |
| 771 | }/*-------------------------< RESTORE_DP >-----------------------*/,{ |
| 772 | /* |
| 773 | * Clear ACK immediately. |
| 774 | * No need to delay it. |
| 775 | */ |
| 776 | SCR_CLR (SCR_ACK), |
| 777 | 0, |
| 778 | /* |
| 779 | * Copy SAVEP to LASTP. |
| 780 | */ |
| 781 | SCR_LOAD_REL (scratcha, 4), |
| 782 | offsetof (struct sym_ccb, phys.head.savep), |
| 783 | SCR_STORE_REL (scratcha, 4), |
| 784 | offsetof (struct sym_ccb, phys.head.lastp), |
| 785 | SCR_JUMP, |
| 786 | PADDR_A (dispatch), |
| 787 | }/*-------------------------< DISCONNECT >-----------------------*/,{ |
| 788 | /* |
| 789 | * DISCONNECTing ... |
| 790 | * |
| 791 | * disable the "unexpected disconnect" feature, |
| 792 | * and remove the ACK signal. |
| 793 | */ |
| 794 | SCR_REG_REG (scntl2, SCR_AND, 0x7f), |
| 795 | 0, |
| 796 | SCR_CLR (SCR_ACK|SCR_ATN), |
| 797 | 0, |
| 798 | /* |
| 799 | * Wait for the disconnect. |
| 800 | */ |
| 801 | SCR_WAIT_DISC, |
| 802 | 0, |
| 803 | /* |
| 804 | * Status is: DISCONNECTED. |
| 805 | */ |
| 806 | SCR_LOAD_REG (HS_REG, HS_DISCONNECT), |
| 807 | 0, |
| 808 | /* |
| 809 | * Save host status. |
| 810 | */ |
| 811 | SCR_STORE_REL (scr0, 4), |
| 812 | offsetof (struct sym_ccb, phys.head.status), |
| 813 | SCR_JUMP, |
| 814 | PADDR_A (start), |
| 815 | }/*-------------------------< IDLE >-----------------------------*/,{ |
| 816 | /* |
| 817 | * Nothing to do? |
| 818 | * Switch the LED off and wait for reselect. |
| 819 | * Will be patched with a NO_OP if LED |
| 820 | * not needed or not desired. |
| 821 | */ |
| 822 | SCR_REG_REG (gpreg, SCR_OR, 0x01), |
| 823 | 0, |
| 824 | #ifdef SYM_CONF_IARB_SUPPORT |
| 825 | SCR_JUMPR, |
| 826 | 8, |
| 827 | #endif |
| 828 | }/*-------------------------< UNGETJOB >-------------------------*/,{ |
| 829 | #ifdef SYM_CONF_IARB_SUPPORT |
| 830 | /* |
| 831 | * Set IMMEDIATE ARBITRATION, for the next time. |
| 832 | * This will give us better chance to win arbitration |
| 833 | * for the job we just wanted to do. |
| 834 | */ |
| 835 | SCR_REG_REG (scntl1, SCR_OR, IARB), |
| 836 | 0, |
| 837 | #endif |
| 838 | /* |
| 839 | * We are not able to restart the SCRIPTS if we are |
| 840 | * interrupted and these instruction haven't been |
| 841 | * all executed. BTW, this is very unlikely to |
| 842 | * happen, but we check that from the C code. |
| 843 | */ |
| 844 | SCR_LOAD_REG (dsa, 0xff), |
| 845 | 0, |
| 846 | SCR_STORE_ABS (scratcha, 4), |
| 847 | PADDR_B (startpos), |
| 848 | }/*-------------------------< RESELECT >-------------------------*/,{ |
| 849 | #ifdef SYM_CONF_TARGET_ROLE_SUPPORT |
| 850 | /* |
| 851 | * Make sure we are in initiator mode. |
| 852 | */ |
| 853 | SCR_CLR (SCR_TRG), |
| 854 | 0, |
| 855 | #endif |
| 856 | /* |
| 857 | * Sleep waiting for a reselection. |
| 858 | */ |
| 859 | SCR_WAIT_RESEL, |
| 860 | PADDR_A(start), |
| 861 | }/*-------------------------< RESELECTED >-----------------------*/,{ |
| 862 | /* |
| 863 | * Switch the LED on. |
| 864 | * Will be patched with a NO_OP if LED |
| 865 | * not needed or not desired. |
| 866 | */ |
| 867 | SCR_REG_REG (gpreg, SCR_AND, 0xfe), |
| 868 | 0, |
| 869 | /* |
| 870 | * load the target id into the sdid |
| 871 | */ |
| 872 | SCR_REG_SFBR (ssid, SCR_AND, 0x8F), |
| 873 | 0, |
| 874 | SCR_TO_REG (sdid), |
| 875 | 0, |
| 876 | /* |
| 877 | * Load the target control block address |
| 878 | */ |
| 879 | SCR_LOAD_ABS (dsa, 4), |
| 880 | PADDR_B (targtbl), |
| 881 | SCR_SFBR_REG (dsa, SCR_SHL, 0), |
| 882 | 0, |
| 883 | SCR_REG_REG (dsa, SCR_SHL, 0), |
| 884 | 0, |
| 885 | SCR_REG_REG (dsa, SCR_AND, 0x3c), |
| 886 | 0, |
| 887 | SCR_LOAD_REL (dsa, 4), |
| 888 | 0, |
| 889 | /* |
| 890 | * We expect MESSAGE IN phase. |
| 891 | * If not, get help from the C code. |
| 892 | */ |
| 893 | SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)), |
| 894 | SIR_RESEL_NO_MSG_IN, |
| 895 | /* |
| 896 | * Load the legacy synchronous transfer registers. |
| 897 | */ |
| 898 | SCR_LOAD_REL (scntl3, 1), |
| 899 | offsetof(struct sym_tcb, head.wval), |
| 900 | SCR_LOAD_REL (sxfer, 1), |
| 901 | offsetof(struct sym_tcb, head.sval), |
| 902 | }/*-------------------------< RESEL_SCNTL4 >---------------------*/,{ |
| 903 | /* |
| 904 | * The C1010 uses a new synchronous timing scheme. |
| 905 | * Will be patched with a NO_OP if not a C1010. |
| 906 | */ |
| 907 | SCR_LOAD_REL (scntl4, 1), |
| 908 | offsetof(struct sym_tcb, head.uval), |
| 909 | /* |
| 910 | * Get the IDENTIFY message. |
| 911 | */ |
| 912 | SCR_MOVE_ABS (1) ^ SCR_MSG_IN, |
| 913 | HADDR_1 (msgin), |
| 914 | /* |
| 915 | * If IDENTIFY LUN #0, use a faster path |
| 916 | * to find the LCB structure. |
| 917 | */ |
| 918 | SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)), |
| 919 | PADDR_A (resel_lun0), |
| 920 | /* |
| 921 | * If message isn't an IDENTIFY, |
| 922 | * tell the C code about. |
| 923 | */ |
| 924 | SCR_INT ^ IFFALSE (MASK (0x80, 0x80)), |
| 925 | SIR_RESEL_NO_IDENTIFY, |
| 926 | /* |
| 927 | * It is an IDENTIFY message, |
| 928 | * Load the LUN control block address. |
| 929 | */ |
| 930 | SCR_LOAD_REL (dsa, 4), |
| 931 | offsetof(struct sym_tcb, head.luntbl_sa), |
| 932 | SCR_SFBR_REG (dsa, SCR_SHL, 0), |
| 933 | 0, |
| 934 | SCR_REG_REG (dsa, SCR_SHL, 0), |
| 935 | 0, |
| 936 | SCR_REG_REG (dsa, SCR_AND, 0xfc), |
| 937 | 0, |
| 938 | SCR_LOAD_REL (dsa, 4), |
| 939 | 0, |
| 940 | SCR_JUMPR, |
| 941 | 8, |
| 942 | }/*-------------------------< RESEL_LUN0 >-----------------------*/,{ |
| 943 | /* |
| 944 | * LUN 0 special case (but usual one :)) |
| 945 | */ |
| 946 | SCR_LOAD_REL (dsa, 4), |
| 947 | offsetof(struct sym_tcb, head.lun0_sa), |
| 948 | /* |
| 949 | * Jump indirectly to the reselect action for this LUN. |
| 950 | */ |
| 951 | SCR_LOAD_REL (temp, 4), |
| 952 | offsetof(struct sym_lcb, head.resel_sa), |
| 953 | SCR_RETURN, |
| 954 | 0, |
| 955 | /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */ |
| 956 | }/*-------------------------< RESEL_TAG >------------------------*/,{ |
| 957 | /* |
| 958 | * ACK the IDENTIFY previously received. |
| 959 | */ |
| 960 | SCR_CLR (SCR_ACK), |
| 961 | 0, |
| 962 | /* |
| 963 | * It shall be a tagged command. |
| 964 | * Read SIMPLE+TAG. |
| 965 | * The C code will deal with errors. |
| 966 | * Agressive optimization, is'nt it? :) |
| 967 | */ |
| 968 | SCR_MOVE_ABS (2) ^ SCR_MSG_IN, |
| 969 | HADDR_1 (msgin), |
| 970 | /* |
| 971 | * Load the pointer to the tagged task |
| 972 | * table for this LUN. |
| 973 | */ |
| 974 | SCR_LOAD_REL (dsa, 4), |
| 975 | offsetof(struct sym_lcb, head.itlq_tbl_sa), |
| 976 | /* |
| 977 | * The SIDL still contains the TAG value. |
| 978 | * Agressive optimization, isn't it? :):) |
| 979 | */ |
| 980 | SCR_REG_SFBR (sidl, SCR_SHL, 0), |
| 981 | 0, |
| 982 | #if SYM_CONF_MAX_TASK*4 > 512 |
| 983 | SCR_JUMPR ^ IFFALSE (CARRYSET), |
| 984 | 8, |
| 985 | SCR_REG_REG (dsa1, SCR_OR, 2), |
| 986 | 0, |
| 987 | SCR_REG_REG (sfbr, SCR_SHL, 0), |
| 988 | 0, |
| 989 | SCR_JUMPR ^ IFFALSE (CARRYSET), |
| 990 | 8, |
| 991 | SCR_REG_REG (dsa1, SCR_OR, 1), |
| 992 | 0, |
| 993 | #elif SYM_CONF_MAX_TASK*4 > 256 |
| 994 | SCR_JUMPR ^ IFFALSE (CARRYSET), |
| 995 | 8, |
| 996 | SCR_REG_REG (dsa1, SCR_OR, 1), |
| 997 | 0, |
| 998 | #endif |
| 999 | /* |
| 1000 | * Retrieve the DSA of this task. |
| 1001 | * JUMP indirectly to the restart point of the CCB. |
| 1002 | */ |
| 1003 | SCR_SFBR_REG (dsa, SCR_AND, 0xfc), |
| 1004 | 0, |
| 1005 | SCR_LOAD_REL (dsa, 4), |
| 1006 | 0, |
| 1007 | SCR_LOAD_REL (temp, 4), |
| 1008 | offsetof(struct sym_ccb, phys.head.go.restart), |
| 1009 | SCR_RETURN, |
| 1010 | 0, |
| 1011 | /* In normal situations we branch to RESEL_DSA */ |
| 1012 | }/*-------------------------< RESEL_DSA >------------------------*/,{ |
| 1013 | /* |
| 1014 | * ACK the IDENTIFY or TAG previously received. |
| 1015 | */ |
| 1016 | SCR_CLR (SCR_ACK), |
| 1017 | 0, |
| 1018 | }/*-------------------------< RESEL_DSA1 >-----------------------*/,{ |
| 1019 | /* |
| 1020 | * Initialize the status registers |
| 1021 | */ |
| 1022 | SCR_LOAD_REL (scr0, 4), |
| 1023 | offsetof (struct sym_ccb, phys.head.status), |
| 1024 | /* |
| 1025 | * Jump to dispatcher. |
| 1026 | */ |
| 1027 | SCR_JUMP, |
| 1028 | PADDR_A (dispatch), |
| 1029 | }/*-------------------------< RESEL_NO_TAG >---------------------*/,{ |
| 1030 | /* |
| 1031 | * Load the DSA with the unique ITL task. |
| 1032 | */ |
| 1033 | SCR_LOAD_REL (dsa, 4), |
| 1034 | offsetof(struct sym_lcb, head.itl_task_sa), |
| 1035 | /* |
| 1036 | * JUMP indirectly to the restart point of the CCB. |
| 1037 | */ |
| 1038 | SCR_LOAD_REL (temp, 4), |
| 1039 | offsetof(struct sym_ccb, phys.head.go.restart), |
| 1040 | SCR_RETURN, |
| 1041 | 0, |
| 1042 | /* In normal situations we branch to RESEL_DSA */ |
| 1043 | }/*-------------------------< DATA_IN >--------------------------*/,{ |
| 1044 | /* |
| 1045 | * Because the size depends on the |
| 1046 | * #define SYM_CONF_MAX_SG parameter, |
| 1047 | * it is filled in at runtime. |
| 1048 | * |
| 1049 | * ##===========< i=0; i<SYM_CONF_MAX_SG >========= |
| 1050 | * || SCR_CHMOV_TBL ^ SCR_DATA_IN, |
| 1051 | * || offsetof (struct sym_dsb, data[ i]), |
| 1052 | * ##========================================== |
| 1053 | */ |
| 1054 | 0 |
| 1055 | }/*-------------------------< DATA_IN2 >-------------------------*/,{ |
| 1056 | SCR_CALL, |
| 1057 | PADDR_A (datai_done), |
| 1058 | SCR_JUMP, |
| 1059 | PADDR_B (data_ovrun), |
| 1060 | }/*-------------------------< DATA_OUT >-------------------------*/,{ |
| 1061 | /* |
| 1062 | * Because the size depends on the |
| 1063 | * #define SYM_CONF_MAX_SG parameter, |
| 1064 | * it is filled in at runtime. |
| 1065 | * |
| 1066 | * ##===========< i=0; i<SYM_CONF_MAX_SG >========= |
| 1067 | * || SCR_CHMOV_TBL ^ SCR_DATA_OUT, |
| 1068 | * || offsetof (struct sym_dsb, data[ i]), |
| 1069 | * ##========================================== |
| 1070 | */ |
| 1071 | 0 |
| 1072 | }/*-------------------------< DATA_OUT2 >------------------------*/,{ |
| 1073 | SCR_CALL, |
| 1074 | PADDR_A (datao_done), |
| 1075 | SCR_JUMP, |
| 1076 | PADDR_B (data_ovrun), |
| 1077 | }/*-------------------------< PM0_DATA >-------------------------*/,{ |
| 1078 | /* |
| 1079 | * Read our host flags to SFBR, so we will be able |
| 1080 | * to check against the data direction we expect. |
| 1081 | */ |
| 1082 | SCR_FROM_REG (HF_REG), |
| 1083 | 0, |
| 1084 | /* |
| 1085 | * Check against actual DATA PHASE. |
| 1086 | */ |
| 1087 | SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), |
| 1088 | PADDR_A (pm0_data_out), |
| 1089 | /* |
| 1090 | * Actual phase is DATA IN. |
| 1091 | * Check against expected direction. |
| 1092 | */ |
| 1093 | SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), |
| 1094 | PADDR_B (data_ovrun), |
| 1095 | /* |
| 1096 | * Keep track we are moving data from the |
| 1097 | * PM0 DATA mini-script. |
| 1098 | */ |
| 1099 | SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), |
| 1100 | 0, |
| 1101 | /* |
| 1102 | * Move the data to memory. |
| 1103 | */ |
| 1104 | SCR_CHMOV_TBL ^ SCR_DATA_IN, |
| 1105 | offsetof (struct sym_ccb, phys.pm0.sg), |
| 1106 | SCR_JUMP, |
| 1107 | PADDR_A (pm0_data_end), |
| 1108 | }/*-------------------------< PM0_DATA_OUT >---------------------*/,{ |
| 1109 | /* |
| 1110 | * Actual phase is DATA OUT. |
| 1111 | * Check against expected direction. |
| 1112 | */ |
| 1113 | SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), |
| 1114 | PADDR_B (data_ovrun), |
| 1115 | /* |
| 1116 | * Keep track we are moving data from the |
| 1117 | * PM0 DATA mini-script. |
| 1118 | */ |
| 1119 | SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0), |
| 1120 | 0, |
| 1121 | /* |
| 1122 | * Move the data from memory. |
| 1123 | */ |
| 1124 | SCR_CHMOV_TBL ^ SCR_DATA_OUT, |
| 1125 | offsetof (struct sym_ccb, phys.pm0.sg), |
| 1126 | }/*-------------------------< PM0_DATA_END >---------------------*/,{ |
| 1127 | /* |
| 1128 | * Clear the flag that told we were moving |
| 1129 | * data from the PM0 DATA mini-script. |
| 1130 | */ |
| 1131 | SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)), |
| 1132 | 0, |
| 1133 | /* |
| 1134 | * Return to the previous DATA script which |
| 1135 | * is guaranteed by design (if no bug) to be |
| 1136 | * the main DATA script for this transfer. |
| 1137 | */ |
| 1138 | SCR_LOAD_REL (temp, 4), |
| 1139 | offsetof (struct sym_ccb, phys.pm0.ret), |
| 1140 | SCR_RETURN, |
| 1141 | 0, |
| 1142 | }/*-------------------------< PM1_DATA >-------------------------*/,{ |
| 1143 | /* |
| 1144 | * Read our host flags to SFBR, so we will be able |
| 1145 | * to check against the data direction we expect. |
| 1146 | */ |
| 1147 | SCR_FROM_REG (HF_REG), |
| 1148 | 0, |
| 1149 | /* |
| 1150 | * Check against actual DATA PHASE. |
| 1151 | */ |
| 1152 | SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)), |
| 1153 | PADDR_A (pm1_data_out), |
| 1154 | /* |
| 1155 | * Actual phase is DATA IN. |
| 1156 | * Check against expected direction. |
| 1157 | */ |
| 1158 | SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), |
| 1159 | PADDR_B (data_ovrun), |
| 1160 | /* |
| 1161 | * Keep track we are moving data from the |
| 1162 | * PM1 DATA mini-script. |
| 1163 | */ |
| 1164 | SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), |
| 1165 | 0, |
| 1166 | /* |
| 1167 | * Move the data to memory. |
| 1168 | */ |
| 1169 | SCR_CHMOV_TBL ^ SCR_DATA_IN, |
| 1170 | offsetof (struct sym_ccb, phys.pm1.sg), |
| 1171 | SCR_JUMP, |
| 1172 | PADDR_A (pm1_data_end), |
| 1173 | }/*-------------------------< PM1_DATA_OUT >---------------------*/,{ |
| 1174 | /* |
| 1175 | * Actual phase is DATA OUT. |
| 1176 | * Check against expected direction. |
| 1177 | */ |
| 1178 | SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), |
| 1179 | PADDR_B (data_ovrun), |
| 1180 | /* |
| 1181 | * Keep track we are moving data from the |
| 1182 | * PM1 DATA mini-script. |
| 1183 | */ |
| 1184 | SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1), |
| 1185 | 0, |
| 1186 | /* |
| 1187 | * Move the data from memory. |
| 1188 | */ |
| 1189 | SCR_CHMOV_TBL ^ SCR_DATA_OUT, |
| 1190 | offsetof (struct sym_ccb, phys.pm1.sg), |
| 1191 | }/*-------------------------< PM1_DATA_END >---------------------*/,{ |
| 1192 | /* |
| 1193 | * Clear the flag that told we were moving |
| 1194 | * data from the PM1 DATA mini-script. |
| 1195 | */ |
| 1196 | SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)), |
| 1197 | 0, |
| 1198 | /* |
| 1199 | * Return to the previous DATA script which |
| 1200 | * is guaranteed by design (if no bug) to be |
| 1201 | * the main DATA script for this transfer. |
| 1202 | */ |
| 1203 | SCR_LOAD_REL (temp, 4), |
| 1204 | offsetof (struct sym_ccb, phys.pm1.ret), |
| 1205 | SCR_RETURN, |
| 1206 | 0, |
| 1207 | }/*-------------------------<>-----------------------------------*/ |
| 1208 | }; |
| 1209 | |
| 1210 | static struct SYM_FWB_SCR SYM_FWB_SCR = { |
| 1211 | /*--------------------------< START64 >--------------------------*/ { |
| 1212 | /* |
| 1213 | * SCRIPT entry point for the 895A, 896 and 1010. |
| 1214 | * For now, there is no specific stuff for those |
| 1215 | * chips at this point, but this may come. |
| 1216 | */ |
| 1217 | SCR_JUMP, |
| 1218 | PADDR_A (init), |
| 1219 | }/*-------------------------< NO_DATA >--------------------------*/,{ |
| 1220 | SCR_JUMP, |
| 1221 | PADDR_B (data_ovrun), |
| 1222 | }/*-------------------------< SEL_FOR_ABORT >--------------------*/,{ |
| 1223 | /* |
| 1224 | * We are jumped here by the C code, if we have |
| 1225 | * some target to reset or some disconnected |
| 1226 | * job to abort. Since error recovery is a serious |
| 1227 | * busyness, we will really reset the SCSI BUS, if |
| 1228 | * case of a SCSI interrupt occurring in this path. |
| 1229 | */ |
| 1230 | #ifdef SYM_CONF_TARGET_ROLE_SUPPORT |
| 1231 | /* |
| 1232 | * Set initiator mode. |
| 1233 | */ |
| 1234 | SCR_CLR (SCR_TRG), |
| 1235 | 0, |
| 1236 | #endif |
| 1237 | /* |
| 1238 | * And try to select this target. |
| 1239 | */ |
| 1240 | SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel), |
| 1241 | PADDR_A (reselect), |
| 1242 | /* |
| 1243 | * Wait for the selection to complete or |
| 1244 | * the selection to time out. |
| 1245 | */ |
| 1246 | SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)), |
| 1247 | -8, |
| 1248 | /* |
| 1249 | * Call the C code. |
| 1250 | */ |
| 1251 | SCR_INT, |
| 1252 | SIR_TARGET_SELECTED, |
| 1253 | /* |
| 1254 | * The C code should let us continue here. |
| 1255 | * Send the 'kiss of death' message. |
| 1256 | * We expect an immediate disconnect once |
| 1257 | * the target has eaten the message. |
| 1258 | */ |
| 1259 | SCR_REG_REG (scntl2, SCR_AND, 0x7f), |
| 1260 | 0, |
| 1261 | SCR_MOVE_TBL ^ SCR_MSG_OUT, |
| 1262 | offsetof (struct sym_hcb, abrt_tbl), |
| 1263 | SCR_CLR (SCR_ACK|SCR_ATN), |
| 1264 | 0, |
| 1265 | SCR_WAIT_DISC, |
| 1266 | 0, |
| 1267 | /* |
| 1268 | * Tell the C code that we are done. |
| 1269 | */ |
| 1270 | SCR_INT, |
| 1271 | SIR_ABORT_SENT, |
| 1272 | }/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{ |
| 1273 | /* |
| 1274 | * Jump at scheduler. |
| 1275 | */ |
| 1276 | SCR_JUMP, |
| 1277 | PADDR_A (start), |
| 1278 | }/*-------------------------< MSG_IN_ETC >-----------------------*/,{ |
| 1279 | /* |
| 1280 | * If it is an EXTENDED (variable size message) |
| 1281 | * Handle it. |
| 1282 | */ |
| 1283 | SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)), |
| 1284 | PADDR_B (msg_extended), |
| 1285 | /* |
| 1286 | * Let the C code handle any other |
| 1287 | * 1 byte message. |
| 1288 | */ |
| 1289 | SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)), |
| 1290 | PADDR_B (msg_received), |
| 1291 | SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)), |
| 1292 | PADDR_B (msg_received), |
| 1293 | /* |
| 1294 | * We donnot handle 2 bytes messages from SCRIPTS. |
| 1295 | * So, let the C code deal with these ones too. |
| 1296 | */ |
| 1297 | SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)), |
| 1298 | PADDR_B (msg_weird_seen), |
| 1299 | SCR_CLR (SCR_ACK), |
| 1300 | 0, |
| 1301 | SCR_MOVE_ABS (1) ^ SCR_MSG_IN, |
| 1302 | HADDR_1 (msgin[1]), |
| 1303 | }/*-------------------------< MSG_RECEIVED >---------------------*/,{ |
| 1304 | SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */ |
| 1305 | 0, |
| 1306 | SCR_INT, |
| 1307 | SIR_MSG_RECEIVED, |
| 1308 | }/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{ |
| 1309 | SCR_LOAD_REL (scratcha, 4), /* DUMMY READ */ |
| 1310 | 0, |
| 1311 | SCR_INT, |
| 1312 | SIR_MSG_WEIRD, |
| 1313 | }/*-------------------------< MSG_EXTENDED >---------------------*/,{ |
| 1314 | /* |
| 1315 | * Clear ACK and get the next byte |
| 1316 | * assumed to be the message length. |
| 1317 | */ |
| 1318 | SCR_CLR (SCR_ACK), |
| 1319 | 0, |
| 1320 | SCR_MOVE_ABS (1) ^ SCR_MSG_IN, |
| 1321 | HADDR_1 (msgin[1]), |
| 1322 | /* |
| 1323 | * Try to catch some unlikely situations as 0 length |
| 1324 | * or too large the length. |
| 1325 | */ |
| 1326 | SCR_JUMP ^ IFTRUE (DATA (0)), |
| 1327 | PADDR_B (msg_weird_seen), |
| 1328 | SCR_TO_REG (scratcha), |
| 1329 | 0, |
| 1330 | SCR_REG_REG (sfbr, SCR_ADD, (256-8)), |
| 1331 | 0, |
| 1332 | SCR_JUMP ^ IFTRUE (CARRYSET), |
| 1333 | PADDR_B (msg_weird_seen), |
| 1334 | /* |
| 1335 | * We donnot handle extended messages from SCRIPTS. |
| 1336 | * Read the amount of data correponding to the |
| 1337 | * message length and call the C code. |
| 1338 | */ |
| 1339 | SCR_STORE_REL (scratcha, 1), |
| 1340 | offsetof (struct sym_dsb, smsg_ext.size), |
| 1341 | SCR_CLR (SCR_ACK), |
| 1342 | 0, |
| 1343 | SCR_MOVE_TBL ^ SCR_MSG_IN, |
| 1344 | offsetof (struct sym_dsb, smsg_ext), |
| 1345 | SCR_JUMP, |
| 1346 | PADDR_B (msg_received), |
| 1347 | }/*-------------------------< MSG_BAD >--------------------------*/,{ |
| 1348 | /* |
| 1349 | * unimplemented message - reject it. |
| 1350 | */ |
| 1351 | SCR_INT, |
| 1352 | SIR_REJECT_TO_SEND, |
| 1353 | SCR_SET (SCR_ATN), |
| 1354 | 0, |
| 1355 | SCR_JUMP, |
| 1356 | PADDR_A (clrack), |
| 1357 | }/*-------------------------< MSG_WEIRD >------------------------*/,{ |
| 1358 | /* |
| 1359 | * weird message received |
| 1360 | * ignore all MSG IN phases and reject it. |
| 1361 | */ |
| 1362 | SCR_INT, |
| 1363 | SIR_REJECT_TO_SEND, |
| 1364 | SCR_SET (SCR_ATN), |
| 1365 | 0, |
| 1366 | }/*-------------------------< MSG_WEIRD1 >-----------------------*/,{ |
| 1367 | SCR_CLR (SCR_ACK), |
| 1368 | 0, |
| 1369 | SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)), |
| 1370 | PADDR_A (dispatch), |
| 1371 | SCR_MOVE_ABS (1) ^ SCR_MSG_IN, |
| 1372 | HADDR_1 (scratch), |
| 1373 | SCR_JUMP, |
| 1374 | PADDR_B (msg_weird1), |
| 1375 | }/*-------------------------< WDTR_RESP >------------------------*/,{ |
| 1376 | /* |
| 1377 | * let the target fetch our answer. |
| 1378 | */ |
| 1379 | SCR_SET (SCR_ATN), |
| 1380 | 0, |
| 1381 | SCR_CLR (SCR_ACK), |
| 1382 | 0, |
| 1383 | SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), |
| 1384 | PADDR_B (nego_bad_phase), |
| 1385 | }/*-------------------------< SEND_WDTR >------------------------*/,{ |
| 1386 | /* |
| 1387 | * Send the M_X_WIDE_REQ |
| 1388 | */ |
| 1389 | SCR_MOVE_ABS (4) ^ SCR_MSG_OUT, |
| 1390 | HADDR_1 (msgout), |
| 1391 | SCR_JUMP, |
| 1392 | PADDR_B (msg_out_done), |
| 1393 | }/*-------------------------< SDTR_RESP >------------------------*/,{ |
| 1394 | /* |
| 1395 | * let the target fetch our answer. |
| 1396 | */ |
| 1397 | SCR_SET (SCR_ATN), |
| 1398 | 0, |
| 1399 | SCR_CLR (SCR_ACK), |
| 1400 | 0, |
| 1401 | SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), |
| 1402 | PADDR_B (nego_bad_phase), |
| 1403 | }/*-------------------------< SEND_SDTR >------------------------*/,{ |
| 1404 | /* |
| 1405 | * Send the M_X_SYNC_REQ |
| 1406 | */ |
| 1407 | SCR_MOVE_ABS (5) ^ SCR_MSG_OUT, |
| 1408 | HADDR_1 (msgout), |
| 1409 | SCR_JUMP, |
| 1410 | PADDR_B (msg_out_done), |
| 1411 | }/*-------------------------< PPR_RESP >-------------------------*/,{ |
| 1412 | /* |
| 1413 | * let the target fetch our answer. |
| 1414 | */ |
| 1415 | SCR_SET (SCR_ATN), |
| 1416 | 0, |
| 1417 | SCR_CLR (SCR_ACK), |
| 1418 | 0, |
| 1419 | SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)), |
| 1420 | PADDR_B (nego_bad_phase), |
| 1421 | }/*-------------------------< SEND_PPR >-------------------------*/,{ |
| 1422 | /* |
| 1423 | * Send the M_X_PPR_REQ |
| 1424 | */ |
| 1425 | SCR_MOVE_ABS (8) ^ SCR_MSG_OUT, |
| 1426 | HADDR_1 (msgout), |
| 1427 | SCR_JUMP, |
| 1428 | PADDR_B (msg_out_done), |
| 1429 | }/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{ |
| 1430 | SCR_INT, |
| 1431 | SIR_NEGO_PROTO, |
| 1432 | SCR_JUMP, |
| 1433 | PADDR_A (dispatch), |
| 1434 | }/*-------------------------< MSG_OUT >--------------------------*/,{ |
| 1435 | /* |
| 1436 | * The target requests a message. |
| 1437 | * We donnot send messages that may |
| 1438 | * require the device to go to bus free. |
| 1439 | */ |
| 1440 | SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, |
| 1441 | HADDR_1 (msgout), |
| 1442 | /* |
| 1443 | * ... wait for the next phase |
| 1444 | * if it's a message out, send it again, ... |
| 1445 | */ |
| 1446 | SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)), |
| 1447 | PADDR_B (msg_out), |
| 1448 | }/*-------------------------< MSG_OUT_DONE >---------------------*/,{ |
| 1449 | /* |
| 1450 | * Let the C code be aware of the |
| 1451 | * sent message and clear the message. |
| 1452 | */ |
| 1453 | SCR_INT, |
| 1454 | SIR_MSG_OUT_DONE, |
| 1455 | /* |
| 1456 | * ... and process the next phase |
| 1457 | */ |
| 1458 | SCR_JUMP, |
| 1459 | PADDR_A (dispatch), |
| 1460 | }/*-------------------------< DATA_OVRUN >-----------------------*/,{ |
| 1461 | /* |
| 1462 | * Use scratcha to count the extra bytes. |
| 1463 | */ |
| 1464 | SCR_LOAD_ABS (scratcha, 4), |
| 1465 | PADDR_B (zero), |
| 1466 | }/*-------------------------< DATA_OVRUN1 >----------------------*/,{ |
| 1467 | /* |
| 1468 | * The target may want to transfer too much data. |
| 1469 | * |
| 1470 | * If phase is DATA OUT write 1 byte and count it. |
| 1471 | */ |
| 1472 | SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)), |
| 1473 | 16, |
| 1474 | SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT, |
| 1475 | HADDR_1 (scratch), |
| 1476 | SCR_JUMP, |
| 1477 | PADDR_B (data_ovrun2), |
| 1478 | /* |
| 1479 | * If WSR is set, clear this condition, and |
| 1480 | * count this byte. |
| 1481 | */ |
| 1482 | SCR_FROM_REG (scntl2), |
| 1483 | 0, |
| 1484 | SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)), |
| 1485 | 16, |
| 1486 | SCR_REG_REG (scntl2, SCR_OR, WSR), |
| 1487 | 0, |
| 1488 | SCR_JUMP, |
| 1489 | PADDR_B (data_ovrun2), |
| 1490 | /* |
| 1491 | * Finally check against DATA IN phase. |
| 1492 | * Signal data overrun to the C code |
| 1493 | * and jump to dispatcher if not so. |
| 1494 | * Read 1 byte otherwise and count it. |
| 1495 | */ |
| 1496 | SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)), |
| 1497 | 16, |
| 1498 | SCR_INT, |
| 1499 | SIR_DATA_OVERRUN, |
| 1500 | SCR_JUMP, |
| 1501 | PADDR_A (dispatch), |
| 1502 | SCR_CHMOV_ABS (1) ^ SCR_DATA_IN, |
| 1503 | HADDR_1 (scratch), |
| 1504 | }/*-------------------------< DATA_OVRUN2 >----------------------*/,{ |
| 1505 | /* |
| 1506 | * Count this byte. |
| 1507 | * This will allow to return a negative |
| 1508 | * residual to user. |
| 1509 | */ |
| 1510 | SCR_REG_REG (scratcha, SCR_ADD, 0x01), |
| 1511 | 0, |
| 1512 | SCR_REG_REG (scratcha1, SCR_ADDC, 0), |
| 1513 | 0, |
| 1514 | SCR_REG_REG (scratcha2, SCR_ADDC, 0), |
| 1515 | 0, |
| 1516 | /* |
| 1517 | * .. and repeat as required. |
| 1518 | */ |
| 1519 | SCR_JUMP, |
| 1520 | PADDR_B (data_ovrun1), |
| 1521 | }/*-------------------------< ABORT_RESEL >----------------------*/,{ |
| 1522 | SCR_SET (SCR_ATN), |
| 1523 | 0, |
| 1524 | SCR_CLR (SCR_ACK), |
| 1525 | 0, |
| 1526 | /* |
| 1527 | * send the abort/abortag/reset message |
| 1528 | * we expect an immediate disconnect |
| 1529 | */ |
| 1530 | SCR_REG_REG (scntl2, SCR_AND, 0x7f), |
| 1531 | 0, |
| 1532 | SCR_MOVE_ABS (1) ^ SCR_MSG_OUT, |
| 1533 | HADDR_1 (msgout), |
| 1534 | SCR_CLR (SCR_ACK|SCR_ATN), |
| 1535 | 0, |
| 1536 | SCR_WAIT_DISC, |
| 1537 | 0, |
| 1538 | SCR_INT, |
| 1539 | SIR_RESEL_ABORTED, |
| 1540 | SCR_JUMP, |
| 1541 | PADDR_A (start), |
| 1542 | }/*-------------------------< RESEND_IDENT >---------------------*/,{ |
| 1543 | /* |
| 1544 | * The target stays in MSG OUT phase after having acked |
| 1545 | * Identify [+ Tag [+ Extended message ]]. Targets shall |
| 1546 | * behave this way on parity error. |
| 1547 | * We must send it again all the messages. |
| 1548 | */ |
| 1549 | SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */ |
| 1550 | 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */ |
| 1551 | SCR_JUMP, |
| 1552 | PADDR_A (send_ident), |
| 1553 | }/*-------------------------< IDENT_BREAK >----------------------*/,{ |
| 1554 | SCR_CLR (SCR_ATN), |
| 1555 | 0, |
| 1556 | SCR_JUMP, |
| 1557 | PADDR_A (select2), |
| 1558 | }/*-------------------------< IDENT_BREAK_ATN >------------------*/,{ |
| 1559 | SCR_SET (SCR_ATN), |
| 1560 | 0, |
| 1561 | SCR_JUMP, |
| 1562 | PADDR_A (select2), |
| 1563 | }/*-------------------------< SDATA_IN >-------------------------*/,{ |
| 1564 | SCR_CHMOV_TBL ^ SCR_DATA_IN, |
| 1565 | offsetof (struct sym_dsb, sense), |
| 1566 | SCR_CALL, |
| 1567 | PADDR_A (datai_done), |
| 1568 | SCR_JUMP, |
| 1569 | PADDR_B (data_ovrun), |
| 1570 | }/*-------------------------< RESEL_BAD_LUN >--------------------*/,{ |
| 1571 | /* |
| 1572 | * Message is an IDENTIFY, but lun is unknown. |
| 1573 | * Signal problem to C code for logging the event. |
| 1574 | * Send a M_ABORT to clear all pending tasks. |
| 1575 | */ |
| 1576 | SCR_INT, |
| 1577 | SIR_RESEL_BAD_LUN, |
| 1578 | SCR_JUMP, |
| 1579 | PADDR_B (abort_resel), |
| 1580 | }/*-------------------------< BAD_I_T_L >------------------------*/,{ |
| 1581 | /* |
| 1582 | * We donnot have a task for that I_T_L. |
| 1583 | * Signal problem to C code for logging the event. |
| 1584 | * Send a M_ABORT message. |
| 1585 | */ |
| 1586 | SCR_INT, |
| 1587 | SIR_RESEL_BAD_I_T_L, |
| 1588 | SCR_JUMP, |
| 1589 | PADDR_B (abort_resel), |
| 1590 | }/*-------------------------< BAD_I_T_L_Q >----------------------*/,{ |
| 1591 | /* |
| 1592 | * We donnot have a task that matches the tag. |
| 1593 | * Signal problem to C code for logging the event. |
| 1594 | * Send a M_ABORTTAG message. |
| 1595 | */ |
| 1596 | SCR_INT, |
| 1597 | SIR_RESEL_BAD_I_T_L_Q, |
| 1598 | SCR_JUMP, |
| 1599 | PADDR_B (abort_resel), |
| 1600 | }/*-------------------------< BAD_STATUS >-----------------------*/,{ |
| 1601 | /* |
| 1602 | * Anything different from INTERMEDIATE |
| 1603 | * CONDITION MET should be a bad SCSI status, |
| 1604 | * given that GOOD status has already been tested. |
| 1605 | * Call the C code. |
| 1606 | */ |
| 1607 | SCR_LOAD_ABS (scratcha, 4), |
| 1608 | PADDR_B (startpos), |
| 1609 | SCR_INT ^ IFFALSE (DATA (S_COND_MET)), |
| 1610 | SIR_BAD_SCSI_STATUS, |
| 1611 | SCR_RETURN, |
| 1612 | 0, |
| 1613 | }/*-------------------------< PM_HANDLE >------------------------*/,{ |
| 1614 | /* |
| 1615 | * Phase mismatch handling. |
| 1616 | * |
| 1617 | * Since we have to deal with 2 SCSI data pointers |
| 1618 | * (current and saved), we need at least 2 contexts. |
| 1619 | * Each context (pm0 and pm1) has a saved area, a |
| 1620 | * SAVE mini-script and a DATA phase mini-script. |
| 1621 | */ |
| 1622 | /* |
| 1623 | * Get the PM handling flags. |
| 1624 | */ |
| 1625 | SCR_FROM_REG (HF_REG), |
| 1626 | 0, |
| 1627 | /* |
| 1628 | * If no flags (1rst PM for example), avoid |
| 1629 | * all the below heavy flags testing. |
| 1630 | * This makes the normal case a bit faster. |
| 1631 | */ |
| 1632 | SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED))), |
| 1633 | PADDR_B (pm_handle1), |
| 1634 | /* |
| 1635 | * If we received a SAVE DP, switch to the |
| 1636 | * other PM context since the savep may point |
| 1637 | * to the current PM context. |
| 1638 | */ |
| 1639 | SCR_JUMPR ^ IFFALSE (MASK (HF_DP_SAVED, HF_DP_SAVED)), |
| 1640 | 8, |
| 1641 | SCR_REG_REG (sfbr, SCR_XOR, HF_ACT_PM), |
| 1642 | 0, |
| 1643 | /* |
| 1644 | * If we have been interrupt in a PM DATA mini-script, |
| 1645 | * we take the return address from the corresponding |
| 1646 | * saved area. |
| 1647 | * This ensure the return address always points to the |
| 1648 | * main DATA script for this transfer. |
| 1649 | */ |
| 1650 | SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1))), |
| 1651 | PADDR_B (pm_handle1), |
| 1652 | SCR_JUMPR ^ IFFALSE (MASK (HF_IN_PM0, HF_IN_PM0)), |
| 1653 | 16, |
| 1654 | SCR_LOAD_REL (ia, 4), |
| 1655 | offsetof(struct sym_ccb, phys.pm0.ret), |
| 1656 | SCR_JUMP, |
| 1657 | PADDR_B (pm_save), |
| 1658 | SCR_LOAD_REL (ia, 4), |
| 1659 | offsetof(struct sym_ccb, phys.pm1.ret), |
| 1660 | SCR_JUMP, |
| 1661 | PADDR_B (pm_save), |
| 1662 | }/*-------------------------< PM_HANDLE1 >-----------------------*/,{ |
| 1663 | /* |
| 1664 | * Normal case. |
| 1665 | * Update the return address so that it |
| 1666 | * will point after the interrupted MOVE. |
| 1667 | */ |
| 1668 | SCR_REG_REG (ia, SCR_ADD, 8), |
| 1669 | 0, |
| 1670 | SCR_REG_REG (ia1, SCR_ADDC, 0), |
| 1671 | 0, |
| 1672 | }/*-------------------------< PM_SAVE >--------------------------*/,{ |
| 1673 | /* |
| 1674 | * Clear all the flags that told us if we were |
| 1675 | * interrupted in a PM DATA mini-script and/or |
| 1676 | * we received a SAVE DP. |
| 1677 | */ |
| 1678 | SCR_SFBR_REG (HF_REG, SCR_AND, (~(HF_IN_PM0|HF_IN_PM1|HF_DP_SAVED))), |
| 1679 | 0, |
| 1680 | /* |
| 1681 | * Choose the current PM context. |
| 1682 | */ |
| 1683 | SCR_JUMP ^ IFTRUE (MASK (HF_ACT_PM, HF_ACT_PM)), |
| 1684 | PADDR_B (pm1_save), |
| 1685 | }/*-------------------------< PM0_SAVE >-------------------------*/,{ |
| 1686 | SCR_STORE_REL (ia, 4), |
| 1687 | offsetof(struct sym_ccb, phys.pm0.ret), |
| 1688 | /* |
| 1689 | * If WSR bit is set, either UA and RBC may |
| 1690 | * have to be changed whether the device wants |
| 1691 | * to ignore this residue or not. |
| 1692 | */ |
| 1693 | SCR_FROM_REG (scntl2), |
| 1694 | 0, |
| 1695 | SCR_CALL ^ IFTRUE (MASK (WSR, WSR)), |
| 1696 | PADDR_B (pm_wsr_handle), |
| 1697 | /* |
| 1698 | * Save the remaining byte count, the updated |
| 1699 | * address and the return address. |
| 1700 | */ |
| 1701 | SCR_STORE_REL (rbc, 4), |
| 1702 | offsetof(struct sym_ccb, phys.pm0.sg.size), |
| 1703 | SCR_STORE_REL (ua, 4), |
| 1704 | offsetof(struct sym_ccb, phys.pm0.sg.addr), |
| 1705 | /* |
| 1706 | * Set the current pointer at the PM0 DATA mini-script. |
| 1707 | */ |
| 1708 | SCR_LOAD_ABS (ia, 4), |
| 1709 | PADDR_B (pm0_data_addr), |
| 1710 | }/*-------------------------< PM_SAVE_END >----------------------*/,{ |
| 1711 | SCR_STORE_REL (ia, 4), |
| 1712 | offsetof(struct sym_ccb, phys.head.lastp), |
| 1713 | SCR_JUMP, |
| 1714 | PADDR_A (dispatch), |
| 1715 | }/*-------------------------< PM1_SAVE >-------------------------*/,{ |
| 1716 | SCR_STORE_REL (ia, 4), |
| 1717 | offsetof(struct sym_ccb, phys.pm1.ret), |
| 1718 | /* |
| 1719 | * If WSR bit is set, either UA and RBC may |
| 1720 | * have to be changed whether the device wants |
| 1721 | * to ignore this residue or not. |
| 1722 | */ |
| 1723 | SCR_FROM_REG (scntl2), |
| 1724 | 0, |
| 1725 | SCR_CALL ^ IFTRUE (MASK (WSR, WSR)), |
| 1726 | PADDR_B (pm_wsr_handle), |
| 1727 | /* |
| 1728 | * Save the remaining byte count, the updated |
| 1729 | * address and the return address. |
| 1730 | */ |
| 1731 | SCR_STORE_REL (rbc, 4), |
| 1732 | offsetof(struct sym_ccb, phys.pm1.sg.size), |
| 1733 | SCR_STORE_REL (ua, 4), |
| 1734 | offsetof(struct sym_ccb, phys.pm1.sg.addr), |
| 1735 | /* |
| 1736 | * Set the current pointer at the PM1 DATA mini-script. |
| 1737 | */ |
| 1738 | SCR_LOAD_ABS (ia, 4), |
| 1739 | PADDR_B (pm1_data_addr), |
| 1740 | SCR_JUMP, |
| 1741 | PADDR_B (pm_save_end), |
| 1742 | }/*-------------------------< PM_WSR_HANDLE >--------------------*/,{ |
| 1743 | /* |
| 1744 | * Phase mismatch handling from SCRIPT with WSR set. |
| 1745 | * Such a condition can occur if the chip wants to |
| 1746 | * execute a CHMOV(size > 1) when the WSR bit is |
| 1747 | * set and the target changes PHASE. |
| 1748 | * |
| 1749 | * We must move the residual byte to memory. |
| 1750 | * |
| 1751 | * UA contains bit 0..31 of the address to |
| 1752 | * move the residual byte. |
| 1753 | * Move it to the table indirect. |
| 1754 | */ |
| 1755 | SCR_STORE_REL (ua, 4), |
| 1756 | offsetof (struct sym_ccb, phys.wresid.addr), |
| 1757 | /* |
| 1758 | * Increment UA (move address to next position). |
| 1759 | */ |
| 1760 | SCR_REG_REG (ua, SCR_ADD, 1), |
| 1761 | 0, |
| 1762 | SCR_REG_REG (ua1, SCR_ADDC, 0), |
| 1763 | 0, |
| 1764 | SCR_REG_REG (ua2, SCR_ADDC, 0), |
| 1765 | 0, |
| 1766 | SCR_REG_REG (ua3, SCR_ADDC, 0), |
| 1767 | 0, |
| 1768 | /* |
| 1769 | * Compute SCRATCHA as: |
| 1770 | * - size to transfer = 1 byte. |
| 1771 | * - bit 24..31 = high address bit [32...39]. |
| 1772 | */ |
| 1773 | SCR_LOAD_ABS (scratcha, 4), |
| 1774 | PADDR_B (zero), |
| 1775 | SCR_REG_REG (scratcha, SCR_OR, 1), |
| 1776 | 0, |
| 1777 | SCR_FROM_REG (rbc3), |
| 1778 | 0, |
| 1779 | SCR_TO_REG (scratcha3), |
| 1780 | 0, |
| 1781 | /* |
| 1782 | * Move this value to the table indirect. |
| 1783 | */ |
| 1784 | SCR_STORE_REL (scratcha, 4), |
| 1785 | offsetof (struct sym_ccb, phys.wresid.size), |
| 1786 | /* |
| 1787 | * Wait for a valid phase. |
| 1788 | * While testing with bogus QUANTUM drives, the C1010 |
| 1789 | * sometimes raised a spurious phase mismatch with |
| 1790 | * WSR and the CHMOV(1) triggered another PM. |
| 1791 | * Waiting explicitely for the PHASE seemed to avoid |
| 1792 | * the nested phase mismatch. Btw, this didn't happen |
| 1793 | * using my IBM drives. |
| 1794 | */ |
| 1795 | SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_IN)), |
| 1796 | 0, |
| 1797 | /* |
| 1798 | * Perform the move of the residual byte. |
| 1799 | */ |
| 1800 | SCR_CHMOV_TBL ^ SCR_DATA_IN, |
| 1801 | offsetof (struct sym_ccb, phys.wresid), |
| 1802 | /* |
| 1803 | * We can now handle the phase mismatch with UA fixed. |
| 1804 | * RBC[0..23]=0 is a special case that does not require |
| 1805 | * a PM context. The C code also checks against this. |
| 1806 | */ |
| 1807 | SCR_FROM_REG (rbc), |
| 1808 | 0, |
| 1809 | SCR_RETURN ^ IFFALSE (DATA (0)), |
| 1810 | 0, |
| 1811 | SCR_FROM_REG (rbc1), |
| 1812 | 0, |
| 1813 | SCR_RETURN ^ IFFALSE (DATA (0)), |
| 1814 | 0, |
| 1815 | SCR_FROM_REG (rbc2), |
| 1816 | 0, |
| 1817 | SCR_RETURN ^ IFFALSE (DATA (0)), |
| 1818 | 0, |
| 1819 | /* |
| 1820 | * RBC[0..23]=0. |
| 1821 | * Not only we donnot need a PM context, but this would |
| 1822 | * lead to a bogus CHMOV(0). This condition means that |
| 1823 | * the residual was the last byte to move from this CHMOV. |
| 1824 | * So, we just have to move the current data script pointer |
| 1825 | * (i.e. TEMP) to the SCRIPTS address following the |
| 1826 | * interrupted CHMOV and jump to dispatcher. |
| 1827 | * IA contains the data pointer to save. |
| 1828 | */ |
| 1829 | SCR_JUMP, |
| 1830 | PADDR_B (pm_save_end), |
| 1831 | }/*-------------------------< WSR_MA_HELPER >--------------------*/,{ |
| 1832 | /* |
| 1833 | * Helper for the C code when WSR bit is set. |
| 1834 | * Perform the move of the residual byte. |
| 1835 | */ |
| 1836 | SCR_CHMOV_TBL ^ SCR_DATA_IN, |
| 1837 | offsetof (struct sym_ccb, phys.wresid), |
| 1838 | SCR_JUMP, |
| 1839 | PADDR_A (dispatch), |
| 1840 | |
| 1841 | #ifdef SYM_OPT_HANDLE_DIR_UNKNOWN |
| 1842 | }/*-------------------------< DATA_IO >--------------------------*/,{ |
| 1843 | /* |
| 1844 | * We jump here if the data direction was unknown at the |
| 1845 | * time we had to queue the command to the scripts processor. |
| 1846 | * Pointers had been set as follow in this situation: |
| 1847 | * savep --> DATA_IO |
| 1848 | * lastp --> start pointer when DATA_IN |
| 1849 | * wlastp --> start pointer when DATA_OUT |
| 1850 | * This script sets savep and lastp according to the |
| 1851 | * direction chosen by the target. |
| 1852 | */ |
| 1853 | SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_OUT)), |
| 1854 | PADDR_B (data_io_out), |
| 1855 | }/*-------------------------< DATA_IO_IN >-----------------------*/,{ |
| 1856 | /* |
| 1857 | * Direction is DATA IN. |
| 1858 | */ |
| 1859 | SCR_LOAD_REL (scratcha, 4), |
| 1860 | offsetof (struct sym_ccb, phys.head.lastp), |
| 1861 | }/*-------------------------< DATA_IO_COM >----------------------*/,{ |
| 1862 | SCR_STORE_REL (scratcha, 4), |
| 1863 | offsetof (struct sym_ccb, phys.head.savep), |
| 1864 | |
| 1865 | /* |
| 1866 | * Jump to the SCRIPTS according to actual direction. |
| 1867 | */ |
| 1868 | SCR_LOAD_REL (temp, 4), |
| 1869 | offsetof (struct sym_ccb, phys.head.savep), |
| 1870 | SCR_RETURN, |
| 1871 | 0, |
| 1872 | }/*-------------------------< DATA_IO_OUT >----------------------*/,{ |
| 1873 | /* |
| 1874 | * Direction is DATA OUT. |
| 1875 | */ |
| 1876 | SCR_REG_REG (HF_REG, SCR_AND, (~HF_DATA_IN)), |
| 1877 | 0, |
| 1878 | SCR_LOAD_REL (scratcha, 4), |
| 1879 | offsetof (struct sym_ccb, phys.head.wlastp), |
| 1880 | SCR_STORE_REL (scratcha, 4), |
| 1881 | offsetof (struct sym_ccb, phys.head.lastp), |
| 1882 | SCR_JUMP, |
| 1883 | PADDR_B(data_io_com), |
| 1884 | #endif /* SYM_OPT_HANDLE_DIR_UNKNOWN */ |
| 1885 | |
| 1886 | }/*-------------------------< ZERO >-----------------------------*/,{ |
| 1887 | SCR_DATA_ZERO, |
| 1888 | }/*-------------------------< SCRATCH >--------------------------*/,{ |
| 1889 | SCR_DATA_ZERO, |
| 1890 | }/*-------------------------< PM0_DATA_ADDR >--------------------*/,{ |
| 1891 | SCR_DATA_ZERO, |
| 1892 | }/*-------------------------< PM1_DATA_ADDR >--------------------*/,{ |
| 1893 | SCR_DATA_ZERO, |
| 1894 | }/*-------------------------< DONE_POS >-------------------------*/,{ |
| 1895 | SCR_DATA_ZERO, |
| 1896 | }/*-------------------------< STARTPOS >-------------------------*/,{ |
| 1897 | SCR_DATA_ZERO, |
| 1898 | }/*-------------------------< TARGTBL >--------------------------*/,{ |
| 1899 | SCR_DATA_ZERO, |
| 1900 | }/*-------------------------<>-----------------------------------*/ |
| 1901 | }; |
| 1902 | |
| 1903 | static struct SYM_FWZ_SCR SYM_FWZ_SCR = { |
| 1904 | /*-------------------------< SNOOPTEST >------------------------*/{ |
| 1905 | /* |
| 1906 | * Read the variable from memory. |
| 1907 | */ |
| 1908 | SCR_LOAD_REL (scratcha, 4), |
| 1909 | offsetof(struct sym_hcb, scratch), |
| 1910 | /* |
| 1911 | * Write the variable to memory. |
| 1912 | */ |
| 1913 | SCR_STORE_REL (temp, 4), |
| 1914 | offsetof(struct sym_hcb, scratch), |
| 1915 | /* |
| 1916 | * Read back the variable from memory. |
| 1917 | */ |
| 1918 | SCR_LOAD_REL (temp, 4), |
| 1919 | offsetof(struct sym_hcb, scratch), |
| 1920 | }/*-------------------------< SNOOPEND >-------------------------*/,{ |
| 1921 | /* |
| 1922 | * And stop. |
| 1923 | */ |
| 1924 | SCR_INT, |
| 1925 | 99, |
| 1926 | }/*-------------------------<>-----------------------------------*/ |
| 1927 | }; |