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gerrit-public.fairphone.software / kernel / msm-4.19 / 40c6d9f0e7745012c9e19c955e22d4809104359c / . / arch / arm / mach-omap2 / cm3xxx.h
blob: 7a16b5598127320b5f4b30d42b2ced459f4981ae [file] [log] [blame]
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame]1/*
2 * OMAP2/3 Clock Management (CM) register definitions
3 *
4 * Copyright (C) 2007-2009 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The CM hardware modules on the OMAP2/3 are quite similar to each
13 * other. The CM modules/instances on OMAP4 are quite different, so
14 * they are handled in a separate file.
15 */
16#ifndef __ARCH_ASM_MACH_OMAP2_CM3XXX_H
17#define __ARCH_ASM_MACH_OMAP2_CM3XXX_H
18
19#include "prcm-common.h"
20#include "cm2xxx_3xxx.h"
21
22#define OMAP34XX_CM_REGADDR(module, reg) \
23 OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
24
25
26/*
27 * OMAP3-specific global CM registers
28 * Use cm_{read,write}_reg() with these registers.
29 * These registers appear once per CM module.
30 */
31
Tero Kristob21be7b2014-03-04 18:19:01 +0200[diff] [blame]32#define OMAP3430_CM_SYSCONFIG 0x0010
33#define OMAP3430_CM_POLCTRL 0x009c
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame]34
35#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
36#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
37
38/*
39 * Module specific CM register offsets from CM_BASE + domain offset
40 * Use cm_{read,write}_mod_reg() with these registers.
41 * These register offsets generally appear in more than one PRCM submodule.
42 */
43
44/* OMAP3-specific register offsets */
45
46#define OMAP3430_CM_CLKEN_PLL 0x0004
47#define OMAP3430ES2_CM_CLKEN2 0x0004
48#define OMAP3430ES2_CM_FCLKEN3 0x0008
49#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
50#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
51#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2
52#define OMAP3430_CM_CLKSEL1 CM_CLKSEL
53#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
54#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
55#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
56#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL
57#define OMAP3430_CM_CLKSTST 0x004c
58#define OMAP3430ES2_CM_CLKSEL4 0x004c
59#define OMAP3430ES2_CM_CLKSEL5 0x0050
60#define OMAP3430_CM_CLKSEL2_EMU 0x0050
61#define OMAP3430_CM_CLKSEL3_EMU 0x0054
62
63
64/* CM_IDLEST bit field values to indicate deasserted IdleReq */
65
66#define OMAP34XX_CM_IDLEST_VAL 1
67
68
69#ifndef __ASSEMBLER__
70
71extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
72extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
73extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
74extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
75
76extern bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
77extern int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
78 u8 idlest_shift);
79
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]80extern int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
81 s16 *prcm_inst, u8 *idlest_reg_id);
82
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame]83extern void omap3_cm_save_context(void);
84extern void omap3_cm_restore_context(void);
Tero Kristoc6a2d832013-10-11 19:15:34 +0300[diff] [blame]85extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame]86
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]87extern int __init omap3xxx_cm_init(void);
88
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame]89#endif
90
91#endif