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gerrit-public.fairphone.software / kernel / msm-4.19 / 413879a10b0b0eb563a23c4df896773b2d9413f9 / . / include / linux / mlx5 / port.h
blob: 035f0d4dc9fec6abd202f989bd5371895e73bfcc [file] [log] [blame]
Achiad Shochatada68c32016-02-22 18:17:23 +0200[diff] [blame]1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef __MLX5_PORT_H__
34#define __MLX5_PORT_H__
35
36#include <linux/mlx5/driver.h>
37
Gal Pressmanda54d242016-04-24 22:51:53 +0300[diff] [blame]38enum mlx5_beacon_duration {
39 MLX5_BEACON_DURATION_OFF = 0x0,
40 MLX5_BEACON_DURATION_INF = 0xffff,
41};
42
Gal Pressmanbb641432016-04-24 22:51:54 +0300[diff] [blame]43enum mlx5_module_id {
44 MLX5_MODULE_ID_SFP = 0x3,
45 MLX5_MODULE_ID_QSFP = 0xC,
46 MLX5_MODULE_ID_QSFP_PLUS = 0xD,
47 MLX5_MODULE_ID_QSFP28 = 0x11,
48};
49
Gal Pressman52244d92016-06-23 17:02:46 +0300[diff] [blame]50enum mlx5_an_status {
51 MLX5_AN_UNAVAILABLE = 0,
52 MLX5_AN_COMPLETE = 1,
53 MLX5_AN_FAILED = 2,
54 MLX5_AN_LINK_UP = 3,
55 MLX5_AN_LINK_DOWN = 4,
56};
57
Gal Pressmanbb641432016-04-24 22:51:54 +0300[diff] [blame]58#define MLX5_EEPROM_MAX_BYTES 32
59#define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff
60#define MLX5_I2C_ADDR_LOW 0x50
61#define MLX5_I2C_ADDR_HIGH 0x51
62#define MLX5_EEPROM_PAGE_LENGTH 256
63
Noa Osherovich8cca30a2016-06-26 12:43:24 +0300[diff] [blame]64enum mlx5e_link_mode {
65 MLX5E_1000BASE_CX_SGMII = 0,
66 MLX5E_1000BASE_KX = 1,
67 MLX5E_10GBASE_CX4 = 2,
68 MLX5E_10GBASE_KX4 = 3,
69 MLX5E_10GBASE_KR = 4,
70 MLX5E_20GBASE_KR2 = 5,
71 MLX5E_40GBASE_CR4 = 6,
72 MLX5E_40GBASE_KR4 = 7,
73 MLX5E_56GBASE_R4 = 8,
74 MLX5E_10GBASE_CR = 12,
75 MLX5E_10GBASE_SR = 13,
76 MLX5E_10GBASE_ER = 14,
77 MLX5E_40GBASE_SR4 = 15,
78 MLX5E_40GBASE_LR4 = 16,
79 MLX5E_50GBASE_SR2 = 18,
80 MLX5E_100GBASE_CR4 = 20,
81 MLX5E_100GBASE_SR4 = 21,
82 MLX5E_100GBASE_KR4 = 22,
83 MLX5E_100GBASE_LR4 = 23,
84 MLX5E_100BASE_TX = 24,
85 MLX5E_1000BASE_T = 25,
86 MLX5E_10GBASE_T = 26,
87 MLX5E_25GBASE_CR = 27,
88 MLX5E_25GBASE_KR = 28,
89 MLX5E_25GBASE_SR = 29,
90 MLX5E_50GBASE_CR2 = 30,
91 MLX5E_50GBASE_KR2 = 31,
92 MLX5E_LINK_MODES_NUMBER,
93};
94
Eran Ben Elisha5b4793f2017-02-13 14:00:59 +0200[diff] [blame]95enum mlx5e_connector_type {
96 MLX5E_PORT_UNKNOWN = 0,
97 MLX5E_PORT_NONE = 1,
98 MLX5E_PORT_TP = 2,
99 MLX5E_PORT_AUI = 3,
100 MLX5E_PORT_BNC = 4,
101 MLX5E_PORT_MII = 5,
102 MLX5E_PORT_FIBRE = 6,
103 MLX5E_PORT_DA = 7,
104 MLX5E_PORT_OTHER = 8,
105 MLX5E_CONNECTOR_TYPE_NUMBER,
106};
107
Noa Osherovich8cca30a2016-06-26 12:43:24 +0300[diff] [blame]108#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
109
Huy Nguyen4ce3bf22016-11-17 13:45:56 +0200[diff] [blame]110#define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
111#define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
112
Achiad Shochatada68c32016-02-22 18:17:23 +0200[diff] [blame]113int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
114int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
115 int ptys_size, int proto_mask, u8 local_port);
116int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
117 u32 *proto_cap, int proto_mask);
118int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
119 u32 *proto_admin, int proto_mask);
120int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
121 u8 *link_width_oper, u8 local_port);
Noa Osherovichd5beb7f2016-06-02 10:47:53 +0300[diff] [blame]122int mlx5_query_port_ib_proto_oper(struct mlx5_core_dev *dev,
123 u8 *proto_oper, u8 local_port);
124int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev,
125 u32 *proto_oper, u8 local_port);
Gal Pressman52244d92016-06-23 17:02:46 +0300[diff] [blame]126int mlx5_set_port_ptys(struct mlx5_core_dev *dev, bool an_disable,
127 u32 proto_admin, int proto_mask);
Gal Pressman667daed2016-06-23 17:02:42 +0300[diff] [blame]128void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
Achiad Shochatada68c32016-02-22 18:17:23 +0200[diff] [blame]129int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
130 enum mlx5_port_status status);
131int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
132 enum mlx5_port_status *status);
Gal Pressmanda54d242016-04-24 22:51:53 +0300[diff] [blame]133int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration);
Gal Pressman52244d92016-06-23 17:02:46 +0300[diff] [blame]134void mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask,
135 u8 *an_status,
136 u8 *an_disable_cap, u8 *an_disable_admin);
Achiad Shochatada68c32016-02-22 18:17:23 +0200[diff] [blame]137
Saeed Mahameed046339e2016-04-22 00:33:03 +0300[diff] [blame]138int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port);
139void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port);
140void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
Achiad Shochatada68c32016-02-22 18:17:23 +0200[diff] [blame]141 u8 port);
142
143int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
144 u8 *vl_hw_cap, u8 local_port);
145
146int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
147int mlx5_query_port_pause(struct mlx5_core_dev *dev,
148 u32 *rx_pause, u32 *tx_pause);
149
Achiad Shochatad909eb2016-02-22 18:17:24 +0200[diff] [blame]150int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
151int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx,
152 u8 *pfc_en_rx);
153
Saeed Mahameed4f3961e2016-02-22 18:17:25 +0200[diff] [blame]154int mlx5_max_tc(struct mlx5_core_dev *mdev);
155
156int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc);
Huy Nguyen3a6a9312016-11-27 17:02:04 +0200[diff] [blame]157int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
158 u8 prio, u8 *tc);
Saeed Mahameed4f3961e2016-02-22 18:17:25 +0200[diff] [blame]159int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group);
Huy Nguyenbe0f1612017-09-28 15:33:50 -0500[diff] [blame]160int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
161 u8 tc, u8 *tc_group);
Saeed Mahameed4f3961e2016-02-22 18:17:25 +0200[diff] [blame]162int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw);
Huy Nguyen3a6a9312016-11-27 17:02:04 +0200[diff] [blame]163int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
164 u8 tc, u8 *bw_pct);
Tariq Toukand8880792016-02-22 18:17:28 +0200[diff] [blame]165int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
166 u8 *max_bw_value,
167 u8 *max_bw_unit);
168int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
169 u8 *max_bw_value,
170 u8 *max_bw_unit);
Tariq Toukan928cfe82016-02-22 18:17:29 +0200[diff] [blame]171int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode);
172int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode);
Saeed Mahameed4f3961e2016-02-22 18:17:25 +0200[diff] [blame]173
Eran Ben Elisha94cb1eb2016-04-24 22:51:52 +0300[diff] [blame]174int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable);
175void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
176 bool *enabled);
Gal Pressmanbb641432016-04-24 22:51:54 +0300[diff] [blame]177int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
178 u16 offset, u16 size, u8 *data);
Eran Ben Elisha94cb1eb2016-04-24 22:51:52 +0300[diff] [blame]179
Huy Nguyen341c5ee2016-11-27 17:02:06 +0200[diff] [blame]180int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out);
181int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in);
Huy Nguyen415a64a2017-07-18 16:08:46 -0500[diff] [blame]182
183int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
184int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
185int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio);
186int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);
Achiad Shochatada68c32016-02-22 18:17:23 +0200[diff] [blame]187#endif /* __MLX5_PORT_H__ */