Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved. |
| 3 | * |
| 4 | * Derived from Intel e1000 driver |
| 5 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the Free |
| 9 | * Software Foundation; either version 2 of the License, or (at your option) |
| 10 | * any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program; if not, write to the Free Software Foundation, Inc., 59 |
| 19 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 20 | */ |
| 21 | |
| 22 | #ifndef _ATL1C_H_ |
| 23 | #define _ATL1C_H_ |
| 24 | |
| 25 | #include <linux/version.h> |
| 26 | #include <linux/init.h> |
| 27 | #include <linux/types.h> |
| 28 | #include <linux/errno.h> |
| 29 | #include <linux/module.h> |
| 30 | #include <linux/pci.h> |
| 31 | #include <linux/netdevice.h> |
| 32 | #include <linux/etherdevice.h> |
| 33 | #include <linux/skbuff.h> |
| 34 | #include <linux/ioport.h> |
| 35 | #include <linux/slab.h> |
| 36 | #include <linux/list.h> |
| 37 | #include <linux/delay.h> |
| 38 | #include <linux/sched.h> |
| 39 | #include <linux/in.h> |
| 40 | #include <linux/ip.h> |
| 41 | #include <linux/ipv6.h> |
| 42 | #include <linux/udp.h> |
| 43 | #include <linux/mii.h> |
| 44 | #include <linux/io.h> |
| 45 | #include <linux/vmalloc.h> |
| 46 | #include <linux/pagemap.h> |
| 47 | #include <linux/tcp.h> |
| 48 | #include <linux/mii.h> |
| 49 | #include <linux/ethtool.h> |
| 50 | #include <linux/if_vlan.h> |
| 51 | #include <linux/workqueue.h> |
| 52 | #include <net/checksum.h> |
| 53 | #include <net/ip6_checksum.h> |
| 54 | |
| 55 | #include "atl1c_hw.h" |
| 56 | |
| 57 | /* Wake Up Filter Control */ |
| 58 | #define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ |
| 59 | #define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ |
| 60 | #define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ |
| 61 | #define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */ |
| 62 | #define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ |
| 63 | |
| 64 | #define AT_VLAN_TO_TAG(_vlan, _tag) \ |
| 65 | _tag = ((((_vlan) >> 8) & 0xFF) |\ |
| 66 | (((_vlan) & 0xFF) << 8)) |
| 67 | |
| 68 | #define AT_TAG_TO_VLAN(_tag, _vlan) \ |
| 69 | _vlan = ((((_tag) >> 8) & 0xFF) |\ |
| 70 | (((_tag) & 0xFF) << 8)) |
| 71 | |
| 72 | #define SPEED_0 0xffff |
| 73 | #define HALF_DUPLEX 1 |
| 74 | #define FULL_DUPLEX 2 |
| 75 | |
| 76 | #define AT_RX_BUF_SIZE (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN) |
| 77 | #define MAX_JUMBO_FRAME_SIZE (9*1024) |
| 78 | #define MAX_TX_OFFLOAD_THRESH (9*1024) |
| 79 | |
| 80 | #define AT_MAX_RECEIVE_QUEUE 4 |
| 81 | #define AT_DEF_RECEIVE_QUEUE 1 |
| 82 | #define AT_MAX_TRANSMIT_QUEUE 2 |
| 83 | |
| 84 | #define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL |
| 85 | #define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL |
| 86 | |
| 87 | #define AT_TX_WATCHDOG (5 * HZ) |
| 88 | #define AT_MAX_INT_WORK 5 |
| 89 | #define AT_TWSI_EEPROM_TIMEOUT 100 |
| 90 | #define AT_HW_MAX_IDLE_DELAY 10 |
| 91 | #define AT_SUSPEND_LINK_TIMEOUT 28 |
| 92 | |
| 93 | #define AT_ASPM_L0S_TIMER 6 |
| 94 | #define AT_ASPM_L1_TIMER 12 |
| 95 | |
| 96 | #define ATL1C_PCIE_L0S_L1_DISABLE 0x01 |
| 97 | #define ATL1C_PCIE_PHY_RESET 0x02 |
| 98 | |
| 99 | #define ATL1C_ASPM_L0s_ENABLE 0x0001 |
| 100 | #define ATL1C_ASPM_L1_ENABLE 0x0002 |
| 101 | |
| 102 | #define AT_REGS_LEN (75 * sizeof(u32)) |
| 103 | #define AT_EEPROM_LEN 512 |
| 104 | |
| 105 | #define ATL1C_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) |
| 106 | #define ATL1C_RFD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc) |
| 107 | #define ATL1C_TPD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc) |
| 108 | #define ATL1C_RRD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status) |
| 109 | |
| 110 | /* tpd word 1 bit 0:7 General Checksum task offload */ |
| 111 | #define TPD_L4HDR_OFFSET_MASK 0x00FF |
| 112 | #define TPD_L4HDR_OFFSET_SHIFT 0 |
| 113 | |
| 114 | /* tpd word 1 bit 0:7 Large Send task offload (IPv4/IPV6) */ |
| 115 | #define TPD_TCPHDR_OFFSET_MASK 0x00FF |
| 116 | #define TPD_TCPHDR_OFFSET_SHIFT 0 |
| 117 | |
| 118 | /* tpd word 1 bit 0:7 Custom Checksum task offload */ |
| 119 | #define TPD_PLOADOFFSET_MASK 0x00FF |
| 120 | #define TPD_PLOADOFFSET_SHIFT 0 |
| 121 | |
| 122 | /* tpd word 1 bit 8:17 */ |
| 123 | #define TPD_CCSUM_EN_MASK 0x0001 |
| 124 | #define TPD_CCSUM_EN_SHIFT 8 |
| 125 | #define TPD_IP_CSUM_MASK 0x0001 |
| 126 | #define TPD_IP_CSUM_SHIFT 9 |
| 127 | #define TPD_TCP_CSUM_MASK 0x0001 |
| 128 | #define TPD_TCP_CSUM_SHIFT 10 |
| 129 | #define TPD_UDP_CSUM_MASK 0x0001 |
| 130 | #define TPD_UDP_CSUM_SHIFT 11 |
| 131 | #define TPD_LSO_EN_MASK 0x0001 /* TCP Large Send Offload */ |
| 132 | #define TPD_LSO_EN_SHIFT 12 |
| 133 | #define TPD_LSO_VER_MASK 0x0001 |
| 134 | #define TPD_LSO_VER_SHIFT 13 /* 0 : ipv4; 1 : ipv4/ipv6 */ |
| 135 | #define TPD_CON_VTAG_MASK 0x0001 |
| 136 | #define TPD_CON_VTAG_SHIFT 14 |
| 137 | #define TPD_INS_VTAG_MASK 0x0001 |
| 138 | #define TPD_INS_VTAG_SHIFT 15 |
| 139 | #define TPD_IPV4_PACKET_MASK 0x0001 /* valid when LSO VER is 1 */ |
| 140 | #define TPD_IPV4_PACKET_SHIFT 16 |
| 141 | #define TPD_ETH_TYPE_MASK 0x0001 |
| 142 | #define TPD_ETH_TYPE_SHIFT 17 /* 0 : 802.3 frame; 1 : Ethernet */ |
| 143 | |
| 144 | /* tpd word 18:25 Custom Checksum task offload */ |
| 145 | #define TPD_CCSUM_OFFSET_MASK 0x00FF |
| 146 | #define TPD_CCSUM_OFFSET_SHIFT 18 |
| 147 | #define TPD_CCSUM_EPAD_MASK 0x0001 |
| 148 | #define TPD_CCSUM_EPAD_SHIFT 30 |
| 149 | |
| 150 | /* tpd word 18:30 Large Send task offload (IPv4/IPV6) */ |
| 151 | #define TPD_MSS_MASK 0x1FFF |
| 152 | #define TPD_MSS_SHIFT 18 |
| 153 | |
| 154 | #define TPD_EOP_MASK 0x0001 |
| 155 | #define TPD_EOP_SHIFT 31 |
| 156 | |
| 157 | struct atl1c_tpd_desc { |
| 158 | __le16 buffer_len; /* include 4-byte CRC */ |
| 159 | __le16 vlan_tag; |
| 160 | __le32 word1; |
| 161 | __le64 buffer_addr; |
| 162 | }; |
| 163 | |
| 164 | struct atl1c_tpd_ext_desc { |
| 165 | u32 reservd_0; |
| 166 | __le32 word1; |
| 167 | __le32 pkt_len; |
| 168 | u32 reservd_1; |
| 169 | }; |
| 170 | /* rrs word 0 bit 0:31 */ |
| 171 | #define RRS_RX_CSUM_MASK 0xFFFF |
| 172 | #define RRS_RX_CSUM_SHIFT 0 |
| 173 | #define RRS_RX_RFD_CNT_MASK 0x000F |
| 174 | #define RRS_RX_RFD_CNT_SHIFT 16 |
| 175 | #define RRS_RX_RFD_INDEX_MASK 0x0FFF |
| 176 | #define RRS_RX_RFD_INDEX_SHIFT 20 |
| 177 | |
| 178 | /* rrs flag bit 0:16 */ |
| 179 | #define RRS_HEAD_LEN_MASK 0x00FF |
| 180 | #define RRS_HEAD_LEN_SHIFT 0 |
| 181 | #define RRS_HDS_TYPE_MASK 0x0003 |
| 182 | #define RRS_HDS_TYPE_SHIFT 8 |
| 183 | #define RRS_CPU_NUM_MASK 0x0003 |
| 184 | #define RRS_CPU_NUM_SHIFT 10 |
| 185 | #define RRS_HASH_FLG_MASK 0x000F |
| 186 | #define RRS_HASH_FLG_SHIFT 12 |
| 187 | |
| 188 | #define RRS_HDS_TYPE_HEAD 1 |
| 189 | #define RRS_HDS_TYPE_DATA 2 |
| 190 | |
| 191 | #define RRS_IS_NO_HDS_TYPE(flag) \ |
| 192 | (((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == 0) |
| 193 | |
| 194 | #define RRS_IS_HDS_HEAD(flag) \ |
| 195 | (((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == \ |
| 196 | RRS_HDS_TYPE_HEAD) |
| 197 | |
| 198 | #define RRS_IS_HDS_DATA(flag) \ |
| 199 | (((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK == \ |
| 200 | RRS_HDS_TYPE_DATA) |
| 201 | |
| 202 | /* rrs word 3 bit 0:31 */ |
| 203 | #define RRS_PKT_SIZE_MASK 0x3FFF |
| 204 | #define RRS_PKT_SIZE_SHIFT 0 |
| 205 | #define RRS_ERR_L4_CSUM_MASK 0x0001 |
| 206 | #define RRS_ERR_L4_CSUM_SHIFT 14 |
| 207 | #define RRS_ERR_IP_CSUM_MASK 0x0001 |
| 208 | #define RRS_ERR_IP_CSUM_SHIFT 15 |
| 209 | #define RRS_VLAN_INS_MASK 0x0001 |
| 210 | #define RRS_VLAN_INS_SHIFT 16 |
| 211 | #define RRS_PROT_ID_MASK 0x0007 |
| 212 | #define RRS_PROT_ID_SHIFT 17 |
| 213 | #define RRS_RX_ERR_SUM_MASK 0x0001 |
| 214 | #define RRS_RX_ERR_SUM_SHIFT 20 |
| 215 | #define RRS_RX_ERR_CRC_MASK 0x0001 |
| 216 | #define RRS_RX_ERR_CRC_SHIFT 21 |
| 217 | #define RRS_RX_ERR_FAE_MASK 0x0001 |
| 218 | #define RRS_RX_ERR_FAE_SHIFT 22 |
| 219 | #define RRS_RX_ERR_TRUNC_MASK 0x0001 |
| 220 | #define RRS_RX_ERR_TRUNC_SHIFT 23 |
| 221 | #define RRS_RX_ERR_RUNC_MASK 0x0001 |
| 222 | #define RRS_RX_ERR_RUNC_SHIFT 24 |
| 223 | #define RRS_RX_ERR_ICMP_MASK 0x0001 |
| 224 | #define RRS_RX_ERR_ICMP_SHIFT 25 |
| 225 | #define RRS_PACKET_BCAST_MASK 0x0001 |
| 226 | #define RRS_PACKET_BCAST_SHIFT 26 |
| 227 | #define RRS_PACKET_MCAST_MASK 0x0001 |
| 228 | #define RRS_PACKET_MCAST_SHIFT 27 |
| 229 | #define RRS_PACKET_TYPE_MASK 0x0001 |
| 230 | #define RRS_PACKET_TYPE_SHIFT 28 |
| 231 | #define RRS_FIFO_FULL_MASK 0x0001 |
| 232 | #define RRS_FIFO_FULL_SHIFT 29 |
| 233 | #define RRS_802_3_LEN_ERR_MASK 0x0001 |
| 234 | #define RRS_802_3_LEN_ERR_SHIFT 30 |
| 235 | #define RRS_RXD_UPDATED_MASK 0x0001 |
| 236 | #define RRS_RXD_UPDATED_SHIFT 31 |
| 237 | |
| 238 | #define RRS_ERR_L4_CSUM 0x00004000 |
| 239 | #define RRS_ERR_IP_CSUM 0x00008000 |
| 240 | #define RRS_VLAN_INS 0x00010000 |
| 241 | #define RRS_RX_ERR_SUM 0x00100000 |
| 242 | #define RRS_RX_ERR_CRC 0x00200000 |
| 243 | #define RRS_802_3_LEN_ERR 0x40000000 |
| 244 | #define RRS_RXD_UPDATED 0x80000000 |
| 245 | |
| 246 | #define RRS_PACKET_TYPE_802_3 1 |
| 247 | #define RRS_PACKET_TYPE_ETH 0 |
| 248 | #define RRS_PACKET_IS_ETH(word) \ |
| 249 | (((word) >> RRS_PACKET_TYPE_SHIFT) & RRS_PACKET_TYPE_MASK == \ |
| 250 | RRS_PACKET_TYPE_ETH) |
| 251 | #define RRS_RXD_IS_VALID(word) \ |
| 252 | ((((word) >> RRS_RXD_UPDATED_SHIFT) & RRS_RXD_UPDATED_MASK) == 1) |
| 253 | |
| 254 | #define RRS_PACKET_PROT_IS_IPV4_ONLY(word) \ |
| 255 | ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 1) |
| 256 | #define RRS_PACKET_PROT_IS_IPV6_ONLY(word) \ |
| 257 | ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 6) |
| 258 | |
| 259 | struct atl1c_recv_ret_status { |
| 260 | __le32 word0; |
| 261 | __le32 rss_hash; |
| 262 | __le16 vlan_tag; |
| 263 | __le16 flag; |
| 264 | __le32 word3; |
| 265 | }; |
| 266 | |
| 267 | /* RFD desciptor */ |
| 268 | struct atl1c_rx_free_desc { |
| 269 | __le64 buffer_addr; |
| 270 | }; |
| 271 | |
| 272 | /* DMA Order Settings */ |
| 273 | enum atl1c_dma_order { |
| 274 | atl1c_dma_ord_in = 1, |
| 275 | atl1c_dma_ord_enh = 2, |
| 276 | atl1c_dma_ord_out = 4 |
| 277 | }; |
| 278 | |
| 279 | enum atl1c_dma_rcb { |
| 280 | atl1c_rcb_64 = 0, |
| 281 | atl1c_rcb_128 = 1 |
| 282 | }; |
| 283 | |
| 284 | enum atl1c_mac_speed { |
| 285 | atl1c_mac_speed_0 = 0, |
| 286 | atl1c_mac_speed_10_100 = 1, |
| 287 | atl1c_mac_speed_1000 = 2 |
| 288 | }; |
| 289 | |
| 290 | enum atl1c_dma_req_block { |
| 291 | atl1c_dma_req_128 = 0, |
| 292 | atl1c_dma_req_256 = 1, |
| 293 | atl1c_dma_req_512 = 2, |
| 294 | atl1c_dma_req_1024 = 3, |
| 295 | atl1c_dma_req_2048 = 4, |
| 296 | atl1c_dma_req_4096 = 5 |
| 297 | }; |
| 298 | |
| 299 | enum atl1c_rss_mode { |
| 300 | atl1c_rss_mode_disable = 0, |
| 301 | atl1c_rss_sig_que = 1, |
| 302 | atl1c_rss_mul_que_sig_int = 2, |
| 303 | atl1c_rss_mul_que_mul_int = 4, |
| 304 | }; |
| 305 | |
| 306 | enum atl1c_rss_type { |
| 307 | atl1c_rss_disable = 0, |
| 308 | atl1c_rss_ipv4 = 1, |
| 309 | atl1c_rss_ipv4_tcp = 2, |
| 310 | atl1c_rss_ipv6 = 4, |
| 311 | atl1c_rss_ipv6_tcp = 8 |
| 312 | }; |
| 313 | |
| 314 | enum atl1c_nic_type { |
| 315 | athr_l1c = 0, |
| 316 | athr_l2c = 1, |
| 317 | }; |
| 318 | |
| 319 | enum atl1c_trans_queue { |
| 320 | atl1c_trans_normal = 0, |
| 321 | atl1c_trans_high = 1 |
| 322 | }; |
| 323 | |
| 324 | struct atl1c_hw_stats { |
| 325 | /* rx */ |
| 326 | unsigned long rx_ok; /* The number of good packet received. */ |
| 327 | unsigned long rx_bcast; /* The number of good broadcast packet received. */ |
| 328 | unsigned long rx_mcast; /* The number of good multicast packet received. */ |
| 329 | unsigned long rx_pause; /* The number of Pause packet received. */ |
| 330 | unsigned long rx_ctrl; /* The number of Control packet received other than Pause frame. */ |
| 331 | unsigned long rx_fcs_err; /* The number of packets with bad FCS. */ |
| 332 | unsigned long rx_len_err; /* The number of packets with mismatch of length field and actual size. */ |
| 333 | unsigned long rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */ |
| 334 | unsigned long rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */ |
| 335 | unsigned long rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */ |
| 336 | unsigned long rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */ |
| 337 | unsigned long rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */ |
| 338 | unsigned long rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */ |
| 339 | unsigned long rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */ |
| 340 | unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */ |
| 341 | unsigned long rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */ |
| 342 | unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */ |
| 343 | unsigned long rx_sz_ov; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */ |
| 344 | unsigned long rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */ |
| 345 | unsigned long rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */ |
| 346 | unsigned long rx_align_err; /* Alignment Error */ |
| 347 | unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */ |
| 348 | unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */ |
| 349 | unsigned long rx_err_addr; /* The number of packets dropped due to address filtering. */ |
| 350 | |
| 351 | /* tx */ |
| 352 | unsigned long tx_ok; /* The number of good packet transmitted. */ |
| 353 | unsigned long tx_bcast; /* The number of good broadcast packet transmitted. */ |
| 354 | unsigned long tx_mcast; /* The number of good multicast packet transmitted. */ |
| 355 | unsigned long tx_pause; /* The number of Pause packet transmitted. */ |
| 356 | unsigned long tx_exc_defer; /* The number of packets transmitted with excessive deferral. */ |
| 357 | unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */ |
| 358 | unsigned long tx_defer; /* The number of packets transmitted that is deferred. */ |
| 359 | unsigned long tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */ |
| 360 | unsigned long tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */ |
| 361 | unsigned long tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */ |
| 362 | unsigned long tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */ |
| 363 | unsigned long tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */ |
| 364 | unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */ |
| 365 | unsigned long tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */ |
| 366 | unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */ |
| 367 | unsigned long tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */ |
| 368 | unsigned long tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */ |
| 369 | unsigned long tx_late_col; /* The number of packets transmitted with late collisions. */ |
| 370 | unsigned long tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */ |
| 371 | unsigned long tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */ |
| 372 | unsigned long tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */ |
| 373 | unsigned long tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */ |
| 374 | unsigned long tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */ |
| 375 | unsigned long tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */ |
| 376 | unsigned long tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */ |
| 377 | }; |
| 378 | |
| 379 | struct atl1c_hw { |
| 380 | u8 __iomem *hw_addr; /* inner register address */ |
| 381 | struct atl1c_adapter *adapter; |
| 382 | enum atl1c_nic_type nic_type; |
| 383 | enum atl1c_dma_order dma_order; |
| 384 | enum atl1c_dma_rcb rcb_value; |
| 385 | enum atl1c_dma_req_block dmar_block; |
| 386 | enum atl1c_dma_req_block dmaw_block; |
| 387 | |
| 388 | u16 device_id; |
| 389 | u16 vendor_id; |
| 390 | u16 subsystem_id; |
| 391 | u16 subsystem_vendor_id; |
| 392 | u8 revision_id; |
| 393 | |
| 394 | u32 intr_mask; |
| 395 | u8 dmaw_dly_cnt; |
| 396 | u8 dmar_dly_cnt; |
| 397 | |
| 398 | u8 preamble_len; |
| 399 | u16 max_frame_size; |
| 400 | u16 min_frame_size; |
| 401 | |
| 402 | enum atl1c_mac_speed mac_speed; |
| 403 | bool mac_duplex; |
| 404 | bool hibernate; |
| 405 | u16 media_type; |
| 406 | #define MEDIA_TYPE_AUTO_SENSOR 0 |
| 407 | #define MEDIA_TYPE_100M_FULL 1 |
| 408 | #define MEDIA_TYPE_100M_HALF 2 |
| 409 | #define MEDIA_TYPE_10M_FULL 3 |
| 410 | #define MEDIA_TYPE_10M_HALF 4 |
| 411 | |
| 412 | u16 autoneg_advertised; |
| 413 | u16 mii_autoneg_adv_reg; |
| 414 | u16 mii_1000t_ctrl_reg; |
| 415 | |
| 416 | u16 tx_imt; /* TX Interrupt Moderator timer ( 2us resolution) */ |
| 417 | u16 rx_imt; /* RX Interrupt Moderator timer ( 2us resolution) */ |
| 418 | u16 ict; /* Interrupt Clear timer (2us resolution) */ |
| 419 | u16 ctrl_flags; |
| 420 | #define ATL1C_INTR_CLEAR_ON_READ 0x0001 |
| 421 | #define ATL1C_INTR_MODRT_ENABLE 0x0002 |
| 422 | #define ATL1C_CMB_ENABLE 0x0004 |
| 423 | #define ATL1C_SMB_ENABLE 0x0010 |
| 424 | #define ATL1C_TXQ_MODE_ENHANCE 0x0020 |
| 425 | #define ATL1C_RX_IPV6_CHKSUM 0x0040 |
| 426 | #define ATL1C_ASPM_L0S_SUPPORT 0x0080 |
| 427 | #define ATL1C_ASPM_L1_SUPPORT 0x0100 |
| 428 | #define ATL1C_ASPM_CTRL_MON 0x0200 |
| 429 | #define ATL1C_HIB_DISABLE 0x0400 |
| 430 | #define ATL1C_LINK_CAP_1000M 0x0800 |
| 431 | #define ATL1C_FPGA_VERSION 0x8000 |
| 432 | u16 cmb_tpd; |
| 433 | u16 cmb_rrd; |
| 434 | u16 cmb_rx_timer; /* 2us resolution */ |
| 435 | u16 cmb_tx_timer; |
| 436 | u32 smb_timer; |
| 437 | |
| 438 | u16 rrd_thresh; /* Threshold of number of RRD produced to trigger |
| 439 | interrupt request */ |
| 440 | u16 tpd_thresh; |
| 441 | u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */ |
| 442 | u8 rfd_burst; |
| 443 | enum atl1c_rss_type rss_type; |
| 444 | enum atl1c_rss_mode rss_mode; |
| 445 | u8 rss_hash_bits; |
| 446 | u32 base_cpu; |
| 447 | u32 indirect_tab; |
| 448 | u8 mac_addr[ETH_ALEN]; |
| 449 | u8 perm_mac_addr[ETH_ALEN]; |
| 450 | |
| 451 | bool phy_configured; |
| 452 | bool re_autoneg; |
| 453 | bool emi_ca; |
| 454 | }; |
| 455 | |
| 456 | /* |
| 457 | * atl1c_ring_header represents a single, contiguous block of DMA space |
| 458 | * mapped for the three descriptor rings (tpd, rfd, rrd) and the two |
| 459 | * message blocks (cmb, smb) described below |
| 460 | */ |
| 461 | struct atl1c_ring_header { |
| 462 | void *desc; /* virtual address */ |
| 463 | dma_addr_t dma; /* physical address*/ |
| 464 | unsigned int size; /* length in bytes */ |
| 465 | }; |
| 466 | |
| 467 | /* |
| 468 | * atl1c_buffer is wrapper around a pointer to a socket buffer |
| 469 | * so a DMA handle can be stored along with the skb |
| 470 | */ |
| 471 | struct atl1c_buffer { |
| 472 | struct sk_buff *skb; /* socket buffer */ |
| 473 | u16 length; /* rx buffer length */ |
| 474 | u16 state; /* state of buffer */ |
| 475 | #define ATL1_BUFFER_FREE 0 |
| 476 | #define ATL1_BUFFER_BUSY 1 |
| 477 | dma_addr_t dma; |
| 478 | }; |
| 479 | |
| 480 | /* transimit packet descriptor (tpd) ring */ |
| 481 | struct atl1c_tpd_ring { |
| 482 | void *desc; /* descriptor ring virtual address */ |
| 483 | dma_addr_t dma; /* descriptor ring physical address */ |
| 484 | u16 size; /* descriptor ring length in bytes */ |
| 485 | u16 count; /* number of descriptors in the ring */ |
| 486 | u16 next_to_use; /* this is protectd by adapter->tx_lock */ |
| 487 | atomic_t next_to_clean; |
| 488 | struct atl1c_buffer *buffer_info; |
| 489 | }; |
| 490 | |
| 491 | /* receive free descriptor (rfd) ring */ |
| 492 | struct atl1c_rfd_ring { |
| 493 | void *desc; /* descriptor ring virtual address */ |
| 494 | dma_addr_t dma; /* descriptor ring physical address */ |
| 495 | u16 size; /* descriptor ring length in bytes */ |
| 496 | u16 count; /* number of descriptors in the ring */ |
| 497 | u16 next_to_use; |
| 498 | u16 next_to_clean; |
| 499 | struct atl1c_buffer *buffer_info; |
| 500 | }; |
| 501 | |
| 502 | /* receive return desciptor (rrd) ring */ |
| 503 | struct atl1c_rrd_ring { |
| 504 | void *desc; /* descriptor ring virtual address */ |
| 505 | dma_addr_t dma; /* descriptor ring physical address */ |
| 506 | u16 size; /* descriptor ring length in bytes */ |
| 507 | u16 count; /* number of descriptors in the ring */ |
| 508 | u16 next_to_use; |
| 509 | u16 next_to_clean; |
| 510 | }; |
| 511 | |
| 512 | struct atl1c_cmb { |
| 513 | void *cmb; |
| 514 | dma_addr_t dma; |
| 515 | }; |
| 516 | |
| 517 | struct atl1c_smb { |
| 518 | void *smb; |
| 519 | dma_addr_t dma; |
| 520 | }; |
| 521 | |
| 522 | /* board specific private data structure */ |
| 523 | struct atl1c_adapter { |
| 524 | struct net_device *netdev; |
| 525 | struct pci_dev *pdev; |
| 526 | struct vlan_group *vlgrp; |
| 527 | struct napi_struct napi; |
| 528 | struct atl1c_hw hw; |
| 529 | struct atl1c_hw_stats hw_stats; |
| 530 | struct net_device_stats net_stats; |
| 531 | struct mii_if_info mii; /* MII interface info */ |
| 532 | u16 rx_buffer_len; |
| 533 | |
| 534 | unsigned long flags; |
| 535 | #define __AT_TESTING 0x0001 |
| 536 | #define __AT_RESETTING 0x0002 |
| 537 | #define __AT_DOWN 0x0003 |
| 538 | u32 msg_enable; |
| 539 | |
| 540 | bool have_msi; |
| 541 | u32 wol; |
| 542 | u16 link_speed; |
| 543 | u16 link_duplex; |
| 544 | |
| 545 | spinlock_t mdio_lock; |
| 546 | spinlock_t tx_lock; |
| 547 | atomic_t irq_sem; |
| 548 | |
| 549 | struct work_struct reset_task; |
| 550 | struct work_struct link_chg_task; |
| 551 | struct timer_list watchdog_timer; |
| 552 | struct timer_list phy_config_timer; |
| 553 | |
| 554 | /* All Descriptor memory */ |
| 555 | struct atl1c_ring_header ring_header; |
| 556 | struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE]; |
| 557 | struct atl1c_rfd_ring rfd_ring[AT_MAX_RECEIVE_QUEUE]; |
| 558 | struct atl1c_rrd_ring rrd_ring[AT_MAX_RECEIVE_QUEUE]; |
| 559 | struct atl1c_cmb cmb; |
| 560 | struct atl1c_smb smb; |
| 561 | int num_rx_queues; |
| 562 | u32 bd_number; /* board number;*/ |
| 563 | }; |
| 564 | |
| 565 | #define AT_WRITE_REG(a, reg, value) ( \ |
| 566 | writel((value), ((a)->hw_addr + reg))) |
| 567 | |
| 568 | #define AT_WRITE_FLUSH(a) (\ |
| 569 | readl((a)->hw_addr)) |
| 570 | |
| 571 | #define AT_READ_REG(a, reg, pdata) do { \ |
| 572 | if (unlikely((a)->hibernate)) { \ |
| 573 | readl((a)->hw_addr + reg); \ |
| 574 | *(u32 *)pdata = readl((a)->hw_addr + reg); \ |
| 575 | } else { \ |
| 576 | *(u32 *)pdata = readl((a)->hw_addr + reg); \ |
| 577 | } \ |
| 578 | } while (0) |
| 579 | |
| 580 | #define AT_WRITE_REGB(a, reg, value) (\ |
| 581 | writeb((value), ((a)->hw_addr + reg))) |
| 582 | |
| 583 | #define AT_READ_REGB(a, reg) (\ |
| 584 | readb((a)->hw_addr + reg)) |
| 585 | |
| 586 | #define AT_WRITE_REGW(a, reg, value) (\ |
| 587 | writew((value), ((a)->hw_addr + reg))) |
| 588 | |
| 589 | #define AT_READ_REGW(a, reg) (\ |
| 590 | readw((a)->hw_addr + reg)) |
| 591 | |
| 592 | #define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \ |
| 593 | writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))) |
| 594 | |
| 595 | #define AT_READ_REG_ARRAY(a, reg, offset) ( \ |
| 596 | readl(((a)->hw_addr + reg) + ((offset) << 2))) |
| 597 | |
| 598 | extern char atl1c_driver_name[]; |
| 599 | extern char atl1c_driver_version[]; |
| 600 | |
| 601 | extern int atl1c_up(struct atl1c_adapter *adapter); |
| 602 | extern void atl1c_down(struct atl1c_adapter *adapter); |
| 603 | extern void atl1c_reinit_locked(struct atl1c_adapter *adapter); |
| 604 | extern s32 atl1c_reset_hw(struct atl1c_hw *hw); |
| 605 | extern void atl1c_set_ethtool_ops(struct net_device *netdev); |
| 606 | #endif /* _ATL1C_H_ */ |