Benjamin Herrenschmidt | 4350147 | 2005-11-07 14:27:33 +1100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org> |
| 3 | * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs, |
| 10 | * that is iMac G5 and latest single CPU desktop. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/config.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/types.h> |
| 16 | #include <linux/errno.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/sched.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <linux/cpufreq.h> |
| 22 | #include <linux/init.h> |
| 23 | #include <linux/completion.h> |
| 24 | #include <asm/prom.h> |
| 25 | #include <asm/machdep.h> |
| 26 | #include <asm/irq.h> |
| 27 | #include <asm/sections.h> |
| 28 | #include <asm/cputable.h> |
| 29 | #include <asm/time.h> |
| 30 | #include <asm/smu.h> |
| 31 | |
| 32 | #undef DEBUG |
| 33 | |
| 34 | #ifdef DEBUG |
| 35 | #define DBG(fmt...) printk(fmt) |
| 36 | #else |
| 37 | #define DBG(fmt...) |
| 38 | #endif |
| 39 | |
| 40 | /* see 970FX user manual */ |
| 41 | |
| 42 | #define SCOM_PCR 0x0aa001 /* PCR scom addr */ |
| 43 | |
| 44 | #define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */ |
| 45 | #define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */ |
| 46 | #define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */ |
| 47 | #define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */ |
| 48 | #define PCR_SPEED_MASK 0x000e0000U /* speed mask */ |
| 49 | #define PCR_SPEED_SHIFT 17 |
| 50 | #define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */ |
| 51 | #define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */ |
| 52 | #define PCR_TARGET_TIME_MASK 0x00006000U /* target time */ |
| 53 | #define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */ |
| 54 | #define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */ |
| 55 | #define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */ |
| 56 | |
| 57 | #define SCOM_PSR 0x408001 /* PSR scom addr */ |
| 58 | /* warning: PSR is a 64 bits register */ |
| 59 | #define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */ |
| 60 | #define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */ |
| 61 | #define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */ |
| 62 | #define PSR_CUR_SPEED_SHIFT (56) |
| 63 | |
| 64 | /* |
| 65 | * The G5 only supports two frequencies (Quarter speed is not supported) |
| 66 | */ |
| 67 | #define CPUFREQ_HIGH 0 |
| 68 | #define CPUFREQ_LOW 1 |
| 69 | |
| 70 | static struct cpufreq_frequency_table g5_cpu_freqs[] = { |
| 71 | {CPUFREQ_HIGH, 0}, |
| 72 | {CPUFREQ_LOW, 0}, |
| 73 | {0, CPUFREQ_TABLE_END}, |
| 74 | }; |
| 75 | |
| 76 | static struct freq_attr* g5_cpu_freqs_attr[] = { |
| 77 | &cpufreq_freq_attr_scaling_available_freqs, |
| 78 | NULL, |
| 79 | }; |
| 80 | |
| 81 | /* Power mode data is an array of the 32 bits PCR values to use for |
| 82 | * the various frequencies, retreived from the device-tree |
| 83 | */ |
| 84 | static u32 *g5_pmode_data; |
| 85 | static int g5_pmode_max; |
| 86 | static int g5_pmode_cur; |
| 87 | |
| 88 | static DECLARE_MUTEX(g5_switch_mutex); |
| 89 | |
| 90 | |
| 91 | static struct smu_sdbp_fvt *g5_fvt_table; /* table of op. points */ |
| 92 | static int g5_fvt_count; /* number of op. points */ |
| 93 | static int g5_fvt_cur; /* current op. point */ |
| 94 | |
| 95 | /* ----------------- real hardware interface */ |
| 96 | |
| 97 | static void g5_switch_volt(int speed_mode) |
| 98 | { |
| 99 | struct smu_simple_cmd cmd; |
| 100 | |
| 101 | DECLARE_COMPLETION(comp); |
| 102 | smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete, |
| 103 | &comp, 'V', 'S', 'L', 'E', 'W', |
| 104 | 0xff, g5_fvt_cur+1, speed_mode); |
| 105 | wait_for_completion(&comp); |
| 106 | } |
| 107 | |
| 108 | static int g5_switch_freq(int speed_mode) |
| 109 | { |
| 110 | struct cpufreq_freqs freqs; |
| 111 | int to; |
| 112 | |
| 113 | if (g5_pmode_cur == speed_mode) |
| 114 | return 0; |
| 115 | |
| 116 | down(&g5_switch_mutex); |
| 117 | |
| 118 | freqs.old = g5_cpu_freqs[g5_pmode_cur].frequency; |
| 119 | freqs.new = g5_cpu_freqs[speed_mode].frequency; |
| 120 | freqs.cpu = 0; |
| 121 | |
| 122 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); |
| 123 | |
| 124 | /* If frequency is going up, first ramp up the voltage */ |
| 125 | if (speed_mode < g5_pmode_cur) |
| 126 | g5_switch_volt(speed_mode); |
| 127 | |
| 128 | /* Clear PCR high */ |
| 129 | scom970_write(SCOM_PCR, 0); |
| 130 | /* Clear PCR low */ |
| 131 | scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0); |
| 132 | /* Set PCR low */ |
| 133 | scom970_write(SCOM_PCR, PCR_HILO_SELECT | |
| 134 | g5_pmode_data[speed_mode]); |
| 135 | |
| 136 | /* Wait for completion */ |
| 137 | for (to = 0; to < 10; to++) { |
| 138 | unsigned long psr = scom970_read(SCOM_PSR); |
| 139 | |
| 140 | if ((psr & PSR_CMD_RECEIVED) == 0 && |
| 141 | (((psr >> PSR_CUR_SPEED_SHIFT) ^ |
| 142 | (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3) |
| 143 | == 0) |
| 144 | break; |
| 145 | if (psr & PSR_CMD_COMPLETED) |
| 146 | break; |
| 147 | udelay(100); |
| 148 | } |
| 149 | |
| 150 | /* If frequency is going down, last ramp the voltage */ |
| 151 | if (speed_mode > g5_pmode_cur) |
| 152 | g5_switch_volt(speed_mode); |
| 153 | |
| 154 | g5_pmode_cur = speed_mode; |
| 155 | ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul; |
| 156 | |
| 157 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); |
| 158 | |
| 159 | up(&g5_switch_mutex); |
| 160 | |
| 161 | return 0; |
| 162 | } |
| 163 | |
| 164 | static int g5_query_freq(void) |
| 165 | { |
| 166 | unsigned long psr = scom970_read(SCOM_PSR); |
| 167 | int i; |
| 168 | |
| 169 | for (i = 0; i <= g5_pmode_max; i++) |
| 170 | if ((((psr >> PSR_CUR_SPEED_SHIFT) ^ |
| 171 | (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0) |
| 172 | break; |
| 173 | return i; |
| 174 | } |
| 175 | |
| 176 | /* ----------------- cpufreq bookkeeping */ |
| 177 | |
| 178 | static int g5_cpufreq_verify(struct cpufreq_policy *policy) |
| 179 | { |
| 180 | return cpufreq_frequency_table_verify(policy, g5_cpu_freqs); |
| 181 | } |
| 182 | |
| 183 | static int g5_cpufreq_target(struct cpufreq_policy *policy, |
| 184 | unsigned int target_freq, unsigned int relation) |
| 185 | { |
| 186 | unsigned int newstate = 0; |
| 187 | |
| 188 | if (cpufreq_frequency_table_target(policy, g5_cpu_freqs, |
| 189 | target_freq, relation, &newstate)) |
| 190 | return -EINVAL; |
| 191 | |
| 192 | return g5_switch_freq(newstate); |
| 193 | } |
| 194 | |
| 195 | static unsigned int g5_cpufreq_get_speed(unsigned int cpu) |
| 196 | { |
| 197 | return g5_cpu_freqs[g5_pmode_cur].frequency; |
| 198 | } |
| 199 | |
| 200 | static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy) |
| 201 | { |
| 202 | if (policy->cpu != 0) |
| 203 | return -ENODEV; |
| 204 | |
| 205 | policy->governor = CPUFREQ_DEFAULT_GOVERNOR; |
| 206 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; |
| 207 | policy->cur = g5_cpu_freqs[g5_query_freq()].frequency; |
| 208 | cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu); |
| 209 | |
| 210 | return cpufreq_frequency_table_cpuinfo(policy, |
| 211 | g5_cpu_freqs); |
| 212 | } |
| 213 | |
| 214 | |
| 215 | static struct cpufreq_driver g5_cpufreq_driver = { |
| 216 | .name = "powermac", |
| 217 | .owner = THIS_MODULE, |
| 218 | .flags = CPUFREQ_CONST_LOOPS, |
| 219 | .init = g5_cpufreq_cpu_init, |
| 220 | .verify = g5_cpufreq_verify, |
| 221 | .target = g5_cpufreq_target, |
| 222 | .get = g5_cpufreq_get_speed, |
| 223 | .attr = g5_cpu_freqs_attr, |
| 224 | }; |
| 225 | |
| 226 | |
| 227 | static int __init g5_cpufreq_init(void) |
| 228 | { |
| 229 | struct device_node *cpunode; |
| 230 | unsigned int psize, ssize; |
| 231 | struct smu_sdbp_header *shdr; |
| 232 | unsigned long max_freq; |
| 233 | u32 *valp; |
| 234 | int rc = -ENODEV; |
| 235 | |
| 236 | /* Look for CPU and SMU nodes */ |
| 237 | cpunode = of_find_node_by_type(NULL, "cpu"); |
| 238 | if (!cpunode) { |
| 239 | DBG("No CPU node !\n"); |
| 240 | return -ENODEV; |
| 241 | } |
| 242 | |
| 243 | /* Check 970FX for now */ |
| 244 | valp = (u32 *)get_property(cpunode, "cpu-version", NULL); |
| 245 | if (!valp) { |
| 246 | DBG("No cpu-version property !\n"); |
| 247 | goto bail_noprops; |
| 248 | } |
| 249 | if (((*valp) >> 16) != 0x3c) { |
| 250 | DBG("Wrong CPU version: %08x\n", *valp); |
| 251 | goto bail_noprops; |
| 252 | } |
| 253 | |
| 254 | /* Look for the powertune data in the device-tree */ |
| 255 | g5_pmode_data = (u32 *)get_property(cpunode, "power-mode-data",&psize); |
| 256 | if (!g5_pmode_data) { |
| 257 | DBG("No power-mode-data !\n"); |
| 258 | goto bail_noprops; |
| 259 | } |
| 260 | g5_pmode_max = psize / sizeof(u32) - 1; |
| 261 | |
| 262 | /* Look for the FVT table */ |
| 263 | shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL); |
| 264 | if (!shdr) |
| 265 | goto bail_noprops; |
| 266 | g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1]; |
| 267 | ssize = (shdr->len * sizeof(u32)) - sizeof(struct smu_sdbp_header); |
| 268 | g5_fvt_count = ssize / sizeof(struct smu_sdbp_fvt); |
| 269 | g5_fvt_cur = 0; |
| 270 | |
| 271 | /* Sanity checking */ |
| 272 | if (g5_fvt_count < 1 || g5_pmode_max < 1) |
| 273 | goto bail_noprops; |
| 274 | |
| 275 | /* |
| 276 | * From what I see, clock-frequency is always the maximal frequency. |
| 277 | * The current driver can not slew sysclk yet, so we really only deal |
| 278 | * with powertune steps for now. We also only implement full freq and |
| 279 | * half freq in this version. So far, I haven't yet seen a machine |
| 280 | * supporting anything else. |
| 281 | */ |
| 282 | valp = (u32 *)get_property(cpunode, "clock-frequency", NULL); |
| 283 | if (!valp) |
| 284 | return -ENODEV; |
| 285 | max_freq = (*valp)/1000; |
| 286 | g5_cpu_freqs[0].frequency = max_freq; |
| 287 | g5_cpu_freqs[1].frequency = max_freq/2; |
| 288 | |
| 289 | /* Check current frequency */ |
| 290 | g5_pmode_cur = g5_query_freq(); |
| 291 | if (g5_pmode_cur > 1) |
| 292 | /* We don't support anything but 1:1 and 1:2, fixup ... */ |
| 293 | g5_pmode_cur = 1; |
| 294 | |
| 295 | /* Force apply current frequency to make sure everything is in |
| 296 | * sync (voltage is right for example). Firmware may leave us with |
| 297 | * a strange setting ... |
| 298 | */ |
| 299 | g5_switch_freq(g5_pmode_cur); |
| 300 | |
| 301 | printk(KERN_INFO "Registering G5 CPU frequency driver\n"); |
| 302 | printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n", |
| 303 | g5_cpu_freqs[1].frequency/1000, |
| 304 | g5_cpu_freqs[0].frequency/1000, |
| 305 | g5_cpu_freqs[g5_pmode_cur].frequency/1000); |
| 306 | |
| 307 | rc = cpufreq_register_driver(&g5_cpufreq_driver); |
| 308 | |
| 309 | /* We keep the CPU node on hold... hopefully, Apple G5 don't have |
| 310 | * hotplug CPU with a dynamic device-tree ... |
| 311 | */ |
| 312 | return rc; |
| 313 | |
| 314 | bail_noprops: |
| 315 | of_node_put(cpunode); |
| 316 | |
| 317 | return rc; |
| 318 | } |
| 319 | |
| 320 | module_init(g5_cpufreq_init); |
| 321 | |
| 322 | |
| 323 | MODULE_LICENSE("GPL"); |