blob: b1c8ace5f0802c908ce653022bbe2921470c8e90 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "drm_sarea.h"
30#include "radeon.h"
31#include "radeon_drm.h"
32
Dave Airlie6a9ee8a2010-02-01 15:38:10 +100033#include <linux/vga_switcheroo.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090034#include <linux/slab.h>
Dave Airlie6a9ee8a2010-02-01 15:38:10 +100035
Jerome Glissecf0fe452009-12-09 18:21:55 +010036int radeon_driver_unload_kms(struct drm_device *dev)
37{
38 struct radeon_device *rdev = dev->dev_private;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020039
Jerome Glissecf0fe452009-12-09 18:21:55 +010040 if (rdev == NULL)
41 return 0;
42 radeon_modeset_fini(rdev);
43 radeon_device_fini(rdev);
44 kfree(rdev);
45 dev->dev_private = NULL;
46 return 0;
47}
48
Jerome Glisse771fe6b2009-06-05 14:42:42 +020049int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
50{
51 struct radeon_device *rdev;
Alberto Miloned7a29522010-07-06 11:40:24 -040052 int r, acpi_status;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020053
54 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
55 if (rdev == NULL) {
56 return -ENOMEM;
57 }
58 dev->dev_private = (void *)rdev;
59
60 /* update BUS flag */
61 if (drm_device_is_agp(dev)) {
62 flags |= RADEON_IS_AGP;
63 } else if (drm_device_is_pcie(dev)) {
64 flags |= RADEON_IS_PCIE;
65 } else {
66 flags |= RADEON_IS_PCI;
67 }
68
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +020069 /* radeon_device_init should report only fatal error
70 * like memory allocation failure or iomapping failure,
71 * or memory manager initialization failure, it must
72 * properly initialize the GPU MC controller and permit
73 * VRAM allocation
74 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +020075 r = radeon_device_init(rdev, dev, dev->pdev, flags);
76 if (r) {
Jerome Glissecf0fe452009-12-09 18:21:55 +010077 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
78 goto out;
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +020079 }
Alberto Miloned7a29522010-07-06 11:40:24 -040080
81 /* Call ACPI methods */
82 acpi_status = radeon_acpi_init(rdev);
83 if (acpi_status)
Dave Airliedc77de12010-08-04 11:16:56 +100084 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
Alberto Miloned7a29522010-07-06 11:40:24 -040085
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +020086 /* Again modeset_init should fail only on fatal error
87 * otherwise it should provide enough functionalities
88 * for shadowfb to run
89 */
90 r = radeon_modeset_init(rdev);
Jerome Glissecf0fe452009-12-09 18:21:55 +010091 if (r)
92 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
93out:
94 if (r)
95 radeon_driver_unload_kms(dev);
96 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020097}
98
99
100/*
101 * Userspace get informations ioctl
102 */
103int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
104{
105 struct radeon_device *rdev = dev->dev_private;
106 struct drm_radeon_info *info;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200107 struct radeon_mode_info *minfo = &rdev->mode_info;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200108 uint32_t *value_ptr;
109 uint32_t value;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200110 struct drm_crtc *crtc;
111 int i, found;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200112
113 info = data;
114 value_ptr = (uint32_t *)((unsigned long)info->value);
Dr. David Alan Gilbertd8ab3552010-08-02 09:43:52 +1000115 if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
116 return -EFAULT;
117
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200118 switch (info->request) {
119 case RADEON_INFO_DEVICE_ID:
120 value = dev->pci_device;
121 break;
122 case RADEON_INFO_NUM_GB_PIPES:
123 value = rdev->num_gb_pipes;
124 break;
Alex Deucherf779b3e2009-08-19 19:11:39 -0400125 case RADEON_INFO_NUM_Z_PIPES:
126 value = rdev->num_z_pipes;
127 break;
Jerome Glisse733289c2009-09-16 15:24:21 +0200128 case RADEON_INFO_ACCEL_WORKING:
Alex Deucher148a03b2010-06-03 19:00:03 -0400129 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
130 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
131 value = false;
132 else
133 value = rdev->accel_working;
Jerome Glisse733289c2009-09-16 15:24:21 +0200134 break;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200135 case RADEON_INFO_CRTC_FROM_ID:
136 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
137 crtc = (struct drm_crtc *)minfo->crtcs[i];
138 if (crtc && crtc->base.id == value) {
Alex Deucher0baf2d82010-07-21 14:05:35 -0400139 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
140 value = radeon_crtc->crtc_id;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200141 found = 1;
142 break;
143 }
144 }
145 if (!found) {
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000146 DRM_DEBUG_KMS("unknown crtc id %d\n", value);
Jerome Glissebc35afd2010-05-12 18:01:13 +0200147 return -EINVAL;
148 }
149 break;
Alex Deucher148a03b2010-06-03 19:00:03 -0400150 case RADEON_INFO_ACCEL_WORKING2:
151 value = rdev->accel_working;
152 break;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400153 case RADEON_INFO_TILING_CONFIG:
154 if (rdev->family >= CHIP_CEDAR)
155 value = rdev->config.evergreen.tile_config;
156 else if (rdev->family >= CHIP_RV770)
157 value = rdev->config.rv770.tile_config;
158 else if (rdev->family >= CHIP_R600)
159 value = rdev->config.r600.tile_config;
160 else {
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000161 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400162 return -EINVAL;
163 }
Dave Airlieab9e1f52010-07-13 11:11:11 +1000164 case RADEON_INFO_WANT_HYPERZ:
Marek Olšák43861f72010-08-07 03:36:34 +0200165 /* The "value" here is both an input and output parameter.
166 * If the input value is 1, filp requests hyper-z access.
167 * If the input value is 0, filp revokes its hyper-z access.
168 *
169 * When returning, the value is 1 if filp owns hyper-z access,
170 * 0 otherwise. */
171 if (value >= 2) {
172 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
173 return -EINVAL;
Dave Airlieab9e1f52010-07-13 11:11:11 +1000174 }
Marek Olšák43861f72010-08-07 03:36:34 +0200175 mutex_lock(&dev->struct_mutex);
176 if (value == 1) {
177 /* wants hyper-z */
178 if (!rdev->hyperz_filp)
179 rdev->hyperz_filp = filp;
180 } else if (value == 0) {
181 /* revokes hyper-z */
182 if (rdev->hyperz_filp == filp)
183 rdev->hyperz_filp = NULL;
184 }
185 value = rdev->hyperz_filp == filp ? 1 : 0;
Dave Airlieab9e1f52010-07-13 11:11:11 +1000186 mutex_unlock(&dev->struct_mutex);
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400187 break;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200188 default:
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000189 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200190 return -EINVAL;
191 }
192 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
193 DRM_ERROR("copy_to_user\n");
194 return -EFAULT;
195 }
196 return 0;
197}
198
199
200/*
201 * Outdated mess for old drm with Xorg being in charge (void function now).
202 */
203int radeon_driver_firstopen_kms(struct drm_device *dev)
204{
205 return 0;
206}
207
208
209void radeon_driver_lastclose_kms(struct drm_device *dev)
210{
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000211 vga_switcheroo_process_delayed_switch();
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200212}
213
214int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
215{
216 return 0;
217}
218
219void radeon_driver_postclose_kms(struct drm_device *dev,
220 struct drm_file *file_priv)
221{
222}
223
224void radeon_driver_preclose_kms(struct drm_device *dev,
225 struct drm_file *file_priv)
226{
Dave Airlieab9e1f52010-07-13 11:11:11 +1000227 struct radeon_device *rdev = dev->dev_private;
228 if (rdev->hyperz_filp == file_priv)
229 rdev->hyperz_filp = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200230}
231
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200232/*
233 * VBlank related functions.
234 */
235u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
236{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200237 struct radeon_device *rdev = dev->dev_private;
238
Dave Airlie9c950a42010-04-23 13:21:58 +1000239 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200240 DRM_ERROR("Invalid crtc %d\n", crtc);
241 return -EINVAL;
242 }
243
244 return radeon_get_vblank_counter(rdev, crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200245}
246
247int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
248{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200249 struct radeon_device *rdev = dev->dev_private;
250
Dave Airlie9c950a42010-04-23 13:21:58 +1000251 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200252 DRM_ERROR("Invalid crtc %d\n", crtc);
253 return -EINVAL;
254 }
255
256 rdev->irq.crtc_vblank_int[crtc] = true;
257
258 return radeon_irq_set(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200259}
260
261void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
262{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200263 struct radeon_device *rdev = dev->dev_private;
264
Dave Airlie9c950a42010-04-23 13:21:58 +1000265 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200266 DRM_ERROR("Invalid crtc %d\n", crtc);
267 return;
268 }
269
270 rdev->irq.crtc_vblank_int[crtc] = false;
271
272 radeon_irq_set(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200273}
274
275
276/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200277 * IOCTL.
278 */
279int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
280 struct drm_file *file_priv)
281{
282 /* Not valid in KMS. */
283 return -EINVAL;
284}
285
286#define KMS_INVALID_IOCTL(name) \
287int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
288{ \
289 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
290 return -EINVAL; \
291}
292
293/*
294 * All these ioctls are invalid in kms world.
295 */
296KMS_INVALID_IOCTL(radeon_cp_init_kms)
297KMS_INVALID_IOCTL(radeon_cp_start_kms)
298KMS_INVALID_IOCTL(radeon_cp_stop_kms)
299KMS_INVALID_IOCTL(radeon_cp_reset_kms)
300KMS_INVALID_IOCTL(radeon_cp_idle_kms)
301KMS_INVALID_IOCTL(radeon_cp_resume_kms)
302KMS_INVALID_IOCTL(radeon_engine_reset_kms)
303KMS_INVALID_IOCTL(radeon_fullscreen_kms)
304KMS_INVALID_IOCTL(radeon_cp_swap_kms)
305KMS_INVALID_IOCTL(radeon_cp_clear_kms)
306KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
307KMS_INVALID_IOCTL(radeon_cp_indices_kms)
308KMS_INVALID_IOCTL(radeon_cp_texture_kms)
309KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
310KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
311KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
312KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
313KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
314KMS_INVALID_IOCTL(radeon_cp_flip_kms)
315KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
316KMS_INVALID_IOCTL(radeon_mem_free_kms)
317KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
318KMS_INVALID_IOCTL(radeon_irq_emit_kms)
319KMS_INVALID_IOCTL(radeon_irq_wait_kms)
320KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
321KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
322KMS_INVALID_IOCTL(radeon_surface_free_kms)
323
324
325struct drm_ioctl_desc radeon_ioctls_kms[] = {
326 DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
327 DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
328 DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
329 DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
330 DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
331 DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
332 DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
333 DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
334 DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
335 DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
336 DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
337 DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
338 DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
339 DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
340 DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
341 DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
342 DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
343 DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
344 DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
345 DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
346 DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
347 DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
348 DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
349 DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
350 DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
351 DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
352 DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
353 /* KMS */
Dave Airliea0c07a62010-02-03 19:17:14 +1000354 DRM_IOCTL_DEF(DRM_RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
355 DRM_IOCTL_DEF(DRM_RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
356 DRM_IOCTL_DEF(DRM_RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
357 DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
358 DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
359 DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
360 DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
361 DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
362 DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
363 DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
364 DRM_IOCTL_DEF(DRM_RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
365 DRM_IOCTL_DEF(DRM_RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200366};
367int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);