Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Intel 5100 Memory Controllers kernel module |
| 3 | * |
| 4 | * This file may be distributed under the terms of the |
| 5 | * GNU General Public License. |
| 6 | * |
| 7 | * This module is based on the following document: |
| 8 | * |
| 9 | * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet |
| 10 | * http://download.intel.com/design/chipsets/datashts/318378.pdf |
| 11 | * |
| 12 | */ |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/pci.h> |
| 16 | #include <linux/pci_ids.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/edac.h> |
| 19 | #include <linux/delay.h> |
| 20 | #include <linux/mmzone.h> |
| 21 | |
| 22 | #include "edac_core.h" |
| 23 | |
| 24 | /* register addresses and bit field accessors... */ |
| 25 | |
| 26 | /* device 16, func 1 */ |
Arthur Jones | 43920a5 | 2008-07-25 01:49:06 -0700 | [diff] [blame^] | 27 | #define I5100_MC 0x40 /* Memory Control Register */ |
| 28 | #define I5100_MC_ERRDETEN(a) ((a) >> 5 & 1) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 29 | #define I5100_MS 0x44 /* Memory Status Register */ |
| 30 | #define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */ |
| 31 | #define I5100_SPDDATA_RDO(a) ((a) >> 15 & 1) |
| 32 | #define I5100_SPDDATA_SBE(a) ((a) >> 13 & 1) |
| 33 | #define I5100_SPDDATA_BUSY(a) ((a) >> 12 & 1) |
| 34 | #define I5100_SPDDATA_DATA(a) ((a) & ((1 << 8) - 1)) |
| 35 | #define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */ |
| 36 | #define I5100_SPDCMD_DTI(a) (((a) & ((1 << 4) - 1)) << 28) |
| 37 | #define I5100_SPDCMD_CKOVRD(a) (((a) & 1) << 27) |
| 38 | #define I5100_SPDCMD_SA(a) (((a) & ((1 << 3) - 1)) << 24) |
| 39 | #define I5100_SPDCMD_BA(a) (((a) & ((1 << 8) - 1)) << 16) |
| 40 | #define I5100_SPDCMD_DATA(a) (((a) & ((1 << 8) - 1)) << 8) |
| 41 | #define I5100_SPDCMD_CMD(a) ((a) & 1) |
| 42 | #define I5100_TOLM 0x6c /* Top of Low Memory */ |
| 43 | #define I5100_TOLM_TOLM(a) ((a) >> 12 & ((1 << 4) - 1)) |
| 44 | #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */ |
| 45 | #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */ |
| 46 | #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */ |
| 47 | #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */ |
| 48 | #define I5100_MIR_LIMIT(a) ((a) >> 4 & ((1 << 12) - 1)) |
| 49 | #define I5100_MIR_WAY1(a) ((a) >> 1 & 1) |
| 50 | #define I5100_MIR_WAY0(a) ((a) & 1) |
| 51 | #define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */ |
| 52 | #define I5100_FERR_NF_MEM_CHAN_INDX(a) ((a) >> 28 & 1) |
| 53 | #define I5100_FERR_NF_MEM_SPD_MASK (1 << 18) |
| 54 | #define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16) |
| 55 | #define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15) |
| 56 | #define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14) |
Arthur Jones | f7952ff | 2008-07-25 01:49:05 -0700 | [diff] [blame] | 57 | #define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12) |
| 58 | #define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11) |
| 59 | #define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10) |
| 60 | #define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6) |
| 61 | #define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5) |
| 62 | #define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4) |
| 63 | #define I5100_FERR_NF_MEM_M1ERR_MASK 1 |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 64 | #define I5100_FERR_NF_MEM_ANY_MASK \ |
| 65 | (I5100_FERR_NF_MEM_M16ERR_MASK | \ |
| 66 | I5100_FERR_NF_MEM_M15ERR_MASK | \ |
Arthur Jones | f7952ff | 2008-07-25 01:49:05 -0700 | [diff] [blame] | 67 | I5100_FERR_NF_MEM_M14ERR_MASK | \ |
| 68 | I5100_FERR_NF_MEM_M12ERR_MASK | \ |
| 69 | I5100_FERR_NF_MEM_M11ERR_MASK | \ |
| 70 | I5100_FERR_NF_MEM_M10ERR_MASK | \ |
| 71 | I5100_FERR_NF_MEM_M6ERR_MASK | \ |
| 72 | I5100_FERR_NF_MEM_M5ERR_MASK | \ |
| 73 | I5100_FERR_NF_MEM_M4ERR_MASK | \ |
| 74 | I5100_FERR_NF_MEM_M1ERR_MASK) |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 75 | #define I5100_FERR_NF_MEM_ANY(a) ((a) & I5100_FERR_NF_MEM_ANY_MASK) |
| 76 | #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */ |
| 77 | #define I5100_NERR_NF_MEM_ANY(a) I5100_FERR_NF_MEM_ANY(a) |
| 78 | |
| 79 | /* device 21 and 22, func 0 */ |
| 80 | #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */ |
| 81 | #define I5100_DMIR 0x15c /* DIMM Interleave Range */ |
| 82 | #define I5100_DMIR_LIMIT(a) ((a) >> 16 & ((1 << 11) - 1)) |
| 83 | #define I5100_DMIR_RANK(a, i) ((a) >> (4 * i) & ((1 << 2) - 1)) |
| 84 | #define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */ |
| 85 | #define I5100_MTR_PRESENT(a) ((a) >> 10 & 1) |
| 86 | #define I5100_MTR_ETHROTTLE(a) ((a) >> 9 & 1) |
| 87 | #define I5100_MTR_WIDTH(a) ((a) >> 8 & 1) |
| 88 | #define I5100_MTR_NUMBANK(a) ((a) >> 6 & 1) |
| 89 | #define I5100_MTR_NUMROW(a) ((a) >> 2 & ((1 << 2) - 1)) |
| 90 | #define I5100_MTR_NUMCOL(a) ((a) & ((1 << 2) - 1)) |
| 91 | #define I5100_VALIDLOG 0x18c /* Valid Log Markers */ |
| 92 | #define I5100_VALIDLOG_REDMEMVALID(a) ((a) >> 2 & 1) |
| 93 | #define I5100_VALIDLOG_RECMEMVALID(a) ((a) >> 1 & 1) |
| 94 | #define I5100_VALIDLOG_NRECMEMVALID(a) ((a) & 1) |
| 95 | #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */ |
| 96 | #define I5100_NRECMEMA_MERR(a) ((a) >> 15 & ((1 << 5) - 1)) |
| 97 | #define I5100_NRECMEMA_BANK(a) ((a) >> 12 & ((1 << 3) - 1)) |
| 98 | #define I5100_NRECMEMA_RANK(a) ((a) >> 8 & ((1 << 3) - 1)) |
| 99 | #define I5100_NRECMEMA_DM_BUF_ID(a) ((a) & ((1 << 8) - 1)) |
| 100 | #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */ |
| 101 | #define I5100_NRECMEMB_CAS(a) ((a) >> 16 & ((1 << 13) - 1)) |
| 102 | #define I5100_NRECMEMB_RAS(a) ((a) & ((1 << 16) - 1)) |
| 103 | #define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */ |
| 104 | #define I5100_REDMEMA_SYNDROME(a) (a) |
| 105 | #define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */ |
| 106 | #define I5100_REDMEMB_ECC_LOCATOR(a) ((a) & ((1 << 18) - 1)) |
| 107 | #define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */ |
| 108 | #define I5100_RECMEMA_MERR(a) I5100_NRECMEMA_MERR(a) |
| 109 | #define I5100_RECMEMA_BANK(a) I5100_NRECMEMA_BANK(a) |
| 110 | #define I5100_RECMEMA_RANK(a) I5100_NRECMEMA_RANK(a) |
| 111 | #define I5100_RECMEMA_DM_BUF_ID(a) I5100_NRECMEMA_DM_BUF_ID(a) |
| 112 | #define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */ |
| 113 | #define I5100_RECMEMB_CAS(a) I5100_NRECMEMB_CAS(a) |
| 114 | #define I5100_RECMEMB_RAS(a) I5100_NRECMEMB_RAS(a) |
| 115 | |
| 116 | /* some generic limits */ |
| 117 | #define I5100_MAX_RANKS_PER_CTLR 6 |
| 118 | #define I5100_MAX_CTLRS 2 |
| 119 | #define I5100_MAX_RANKS_PER_DIMM 4 |
| 120 | #define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */ |
| 121 | #define I5100_MAX_DIMM_SLOTS_PER_CTLR 4 |
| 122 | #define I5100_MAX_RANK_INTERLEAVE 4 |
| 123 | #define I5100_MAX_DMIRS 5 |
| 124 | |
| 125 | struct i5100_priv { |
| 126 | /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */ |
| 127 | int dimm_numrank[I5100_MAX_CTLRS][I5100_MAX_DIMM_SLOTS_PER_CTLR]; |
| 128 | |
| 129 | /* |
| 130 | * mainboard chip select map -- maps i5100 chip selects to |
| 131 | * DIMM slot chip selects. In the case of only 4 ranks per |
| 132 | * controller, the mapping is fairly obvious but not unique. |
| 133 | * we map -1 -> NC and assume both controllers use the same |
| 134 | * map... |
| 135 | * |
| 136 | */ |
| 137 | int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CTLR][I5100_MAX_RANKS_PER_DIMM]; |
| 138 | |
| 139 | /* memory interleave range */ |
| 140 | struct { |
| 141 | u64 limit; |
| 142 | unsigned way[2]; |
| 143 | } mir[I5100_MAX_CTLRS]; |
| 144 | |
| 145 | /* adjusted memory interleave range register */ |
| 146 | unsigned amir[I5100_MAX_CTLRS]; |
| 147 | |
| 148 | /* dimm interleave range */ |
| 149 | struct { |
| 150 | unsigned rank[I5100_MAX_RANK_INTERLEAVE]; |
| 151 | u64 limit; |
| 152 | } dmir[I5100_MAX_CTLRS][I5100_MAX_DMIRS]; |
| 153 | |
| 154 | /* memory technology registers... */ |
| 155 | struct { |
| 156 | unsigned present; /* 0 or 1 */ |
| 157 | unsigned ethrottle; /* 0 or 1 */ |
| 158 | unsigned width; /* 4 or 8 bits */ |
| 159 | unsigned numbank; /* 2 or 3 lines */ |
| 160 | unsigned numrow; /* 13 .. 16 lines */ |
| 161 | unsigned numcol; /* 11 .. 12 lines */ |
| 162 | } mtr[I5100_MAX_CTLRS][I5100_MAX_RANKS_PER_CTLR]; |
| 163 | |
| 164 | u64 tolm; /* top of low memory in bytes */ |
| 165 | unsigned ranksperctlr; /* number of ranks per controller */ |
| 166 | |
| 167 | struct pci_dev *mc; /* device 16 func 1 */ |
| 168 | struct pci_dev *ch0mm; /* device 21 func 0 */ |
| 169 | struct pci_dev *ch1mm; /* device 22 func 0 */ |
| 170 | }; |
| 171 | |
| 172 | /* map a rank/ctlr to a slot number on the mainboard */ |
| 173 | static int i5100_rank_to_slot(const struct mem_ctl_info *mci, |
| 174 | int ctlr, int rank) |
| 175 | { |
| 176 | const struct i5100_priv *priv = mci->pvt_info; |
| 177 | int i; |
| 178 | |
| 179 | for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CTLR; i++) { |
| 180 | int j; |
| 181 | const int numrank = priv->dimm_numrank[ctlr][i]; |
| 182 | |
| 183 | for (j = 0; j < numrank; j++) |
| 184 | if (priv->dimm_csmap[i][j] == rank) |
| 185 | return i * 2 + ctlr; |
| 186 | } |
| 187 | |
| 188 | return -1; |
| 189 | } |
| 190 | |
| 191 | /* |
| 192 | * The processor bus memory addresses are broken into three |
| 193 | * pieces, whereas the controller addresses are contiguous. |
| 194 | * |
| 195 | * here we map from the controller address space to the |
| 196 | * processor address space: |
| 197 | * |
| 198 | * Processor Address Space |
| 199 | * +-----------------------------+ |
| 200 | * | | |
| 201 | * | "high" memory addresses | |
| 202 | * | | |
| 203 | * +-----------------------------+ <- 4GB on the i5100 |
| 204 | * | | |
| 205 | * | other non-memory addresses | |
| 206 | * | | |
| 207 | * +-----------------------------+ <- top of low memory |
| 208 | * | | |
| 209 | * | "low" memory addresses | |
| 210 | * | | |
| 211 | * +-----------------------------+ |
| 212 | */ |
| 213 | static unsigned long i5100_ctl_page_to_phys(struct mem_ctl_info *mci, |
| 214 | unsigned long cntlr_addr) |
| 215 | { |
| 216 | const struct i5100_priv *priv = mci->pvt_info; |
| 217 | |
| 218 | if (cntlr_addr < priv->tolm) |
| 219 | return cntlr_addr; |
| 220 | |
| 221 | return (1ULL << 32) + (cntlr_addr - priv->tolm); |
| 222 | } |
| 223 | |
| 224 | static const char *i5100_err_msg(unsigned err) |
| 225 | { |
| 226 | const char *merrs[] = { |
| 227 | "unknown", /* 0 */ |
| 228 | "uncorrectable data ECC on replay", /* 1 */ |
| 229 | "unknown", /* 2 */ |
| 230 | "unknown", /* 3 */ |
| 231 | "aliased uncorrectable demand data ECC", /* 4 */ |
| 232 | "aliased uncorrectable spare-copy data ECC", /* 5 */ |
| 233 | "aliased uncorrectable patrol data ECC", /* 6 */ |
| 234 | "unknown", /* 7 */ |
| 235 | "unknown", /* 8 */ |
| 236 | "unknown", /* 9 */ |
| 237 | "non-aliased uncorrectable demand data ECC", /* 10 */ |
| 238 | "non-aliased uncorrectable spare-copy data ECC", /* 11 */ |
| 239 | "non-aliased uncorrectable patrol data ECC", /* 12 */ |
| 240 | "unknown", /* 13 */ |
| 241 | "correctable demand data ECC", /* 14 */ |
| 242 | "correctable spare-copy data ECC", /* 15 */ |
| 243 | "correctable patrol data ECC", /* 16 */ |
| 244 | "unknown", /* 17 */ |
| 245 | "SPD protocol error", /* 18 */ |
| 246 | "unknown", /* 19 */ |
| 247 | "spare copy initiated", /* 20 */ |
| 248 | "spare copy completed", /* 21 */ |
| 249 | }; |
| 250 | unsigned i; |
| 251 | |
| 252 | for (i = 0; i < ARRAY_SIZE(merrs); i++) |
| 253 | if (1 << i & err) |
| 254 | return merrs[i]; |
| 255 | |
| 256 | return "none"; |
| 257 | } |
| 258 | |
| 259 | /* convert csrow index into a rank (per controller -- 0..5) */ |
| 260 | static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow) |
| 261 | { |
| 262 | const struct i5100_priv *priv = mci->pvt_info; |
| 263 | |
| 264 | return csrow % priv->ranksperctlr; |
| 265 | } |
| 266 | |
| 267 | /* convert csrow index into a controller (0..1) */ |
| 268 | static int i5100_csrow_to_cntlr(const struct mem_ctl_info *mci, int csrow) |
| 269 | { |
| 270 | const struct i5100_priv *priv = mci->pvt_info; |
| 271 | |
| 272 | return csrow / priv->ranksperctlr; |
| 273 | } |
| 274 | |
| 275 | static unsigned i5100_rank_to_csrow(const struct mem_ctl_info *mci, |
| 276 | int ctlr, int rank) |
| 277 | { |
| 278 | const struct i5100_priv *priv = mci->pvt_info; |
| 279 | |
| 280 | return ctlr * priv->ranksperctlr + rank; |
| 281 | } |
| 282 | |
| 283 | static void i5100_handle_ce(struct mem_ctl_info *mci, |
| 284 | int ctlr, |
| 285 | unsigned bank, |
| 286 | unsigned rank, |
| 287 | unsigned long syndrome, |
| 288 | unsigned cas, |
| 289 | unsigned ras, |
| 290 | const char *msg) |
| 291 | { |
| 292 | const int csrow = i5100_rank_to_csrow(mci, ctlr, rank); |
| 293 | |
| 294 | printk(KERN_ERR |
| 295 | "CE ctlr %d, bank %u, rank %u, syndrome 0x%lx, " |
| 296 | "cas %u, ras %u, csrow %u, label \"%s\": %s\n", |
| 297 | ctlr, bank, rank, syndrome, cas, ras, |
| 298 | csrow, mci->csrows[csrow].channels[0].label, msg); |
| 299 | |
| 300 | mci->ce_count++; |
| 301 | mci->csrows[csrow].ce_count++; |
| 302 | mci->csrows[csrow].channels[0].ce_count++; |
| 303 | } |
| 304 | |
| 305 | static void i5100_handle_ue(struct mem_ctl_info *mci, |
| 306 | int ctlr, |
| 307 | unsigned bank, |
| 308 | unsigned rank, |
| 309 | unsigned long syndrome, |
| 310 | unsigned cas, |
| 311 | unsigned ras, |
| 312 | const char *msg) |
| 313 | { |
| 314 | const int csrow = i5100_rank_to_csrow(mci, ctlr, rank); |
| 315 | |
| 316 | printk(KERN_ERR |
| 317 | "UE ctlr %d, bank %u, rank %u, syndrome 0x%lx, " |
| 318 | "cas %u, ras %u, csrow %u, label \"%s\": %s\n", |
| 319 | ctlr, bank, rank, syndrome, cas, ras, |
| 320 | csrow, mci->csrows[csrow].channels[0].label, msg); |
| 321 | |
| 322 | mci->ue_count++; |
| 323 | mci->csrows[csrow].ue_count++; |
| 324 | } |
| 325 | |
| 326 | static void i5100_read_log(struct mem_ctl_info *mci, int ctlr, |
| 327 | u32 ferr, u32 nerr) |
| 328 | { |
| 329 | struct i5100_priv *priv = mci->pvt_info; |
| 330 | struct pci_dev *pdev = (ctlr) ? priv->ch1mm : priv->ch0mm; |
| 331 | u32 dw; |
| 332 | u32 dw2; |
| 333 | unsigned syndrome = 0; |
| 334 | unsigned ecc_loc = 0; |
| 335 | unsigned merr; |
| 336 | unsigned bank; |
| 337 | unsigned rank; |
| 338 | unsigned cas; |
| 339 | unsigned ras; |
| 340 | |
| 341 | pci_read_config_dword(pdev, I5100_VALIDLOG, &dw); |
| 342 | |
| 343 | if (I5100_VALIDLOG_REDMEMVALID(dw)) { |
| 344 | pci_read_config_dword(pdev, I5100_REDMEMA, &dw2); |
| 345 | syndrome = I5100_REDMEMA_SYNDROME(dw2); |
| 346 | pci_read_config_dword(pdev, I5100_REDMEMB, &dw2); |
| 347 | ecc_loc = I5100_REDMEMB_ECC_LOCATOR(dw2); |
| 348 | } |
| 349 | |
| 350 | if (I5100_VALIDLOG_RECMEMVALID(dw)) { |
| 351 | const char *msg; |
| 352 | |
| 353 | pci_read_config_dword(pdev, I5100_RECMEMA, &dw2); |
| 354 | merr = I5100_RECMEMA_MERR(dw2); |
| 355 | bank = I5100_RECMEMA_BANK(dw2); |
| 356 | rank = I5100_RECMEMA_RANK(dw2); |
| 357 | |
| 358 | pci_read_config_dword(pdev, I5100_RECMEMB, &dw2); |
| 359 | cas = I5100_RECMEMB_CAS(dw2); |
| 360 | ras = I5100_RECMEMB_RAS(dw2); |
| 361 | |
| 362 | /* FIXME: not really sure if this is what merr is... |
| 363 | */ |
| 364 | if (!merr) |
| 365 | msg = i5100_err_msg(ferr); |
| 366 | else |
| 367 | msg = i5100_err_msg(nerr); |
| 368 | |
| 369 | i5100_handle_ce(mci, ctlr, bank, rank, syndrome, cas, ras, msg); |
| 370 | } |
| 371 | |
| 372 | if (I5100_VALIDLOG_NRECMEMVALID(dw)) { |
| 373 | const char *msg; |
| 374 | |
| 375 | pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2); |
| 376 | merr = I5100_NRECMEMA_MERR(dw2); |
| 377 | bank = I5100_NRECMEMA_BANK(dw2); |
| 378 | rank = I5100_NRECMEMA_RANK(dw2); |
| 379 | |
| 380 | pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2); |
| 381 | cas = I5100_NRECMEMB_CAS(dw2); |
| 382 | ras = I5100_NRECMEMB_RAS(dw2); |
| 383 | |
| 384 | /* FIXME: not really sure if this is what merr is... |
| 385 | */ |
| 386 | if (!merr) |
| 387 | msg = i5100_err_msg(ferr); |
| 388 | else |
| 389 | msg = i5100_err_msg(nerr); |
| 390 | |
| 391 | i5100_handle_ue(mci, ctlr, bank, rank, syndrome, cas, ras, msg); |
| 392 | } |
| 393 | |
| 394 | pci_write_config_dword(pdev, I5100_VALIDLOG, dw); |
| 395 | } |
| 396 | |
| 397 | static void i5100_check_error(struct mem_ctl_info *mci) |
| 398 | { |
| 399 | struct i5100_priv *priv = mci->pvt_info; |
| 400 | u32 dw; |
| 401 | |
| 402 | |
| 403 | pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw); |
| 404 | if (I5100_FERR_NF_MEM_ANY(dw)) { |
| 405 | u32 dw2; |
| 406 | |
| 407 | pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2); |
| 408 | if (dw2) |
| 409 | pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, |
| 410 | dw2); |
| 411 | pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw); |
| 412 | |
| 413 | i5100_read_log(mci, I5100_FERR_NF_MEM_CHAN_INDX(dw), |
| 414 | I5100_FERR_NF_MEM_ANY(dw), |
| 415 | I5100_NERR_NF_MEM_ANY(dw2)); |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | static struct pci_dev *pci_get_device_func(unsigned vendor, |
| 420 | unsigned device, |
| 421 | unsigned func) |
| 422 | { |
| 423 | struct pci_dev *ret = NULL; |
| 424 | |
| 425 | while (1) { |
| 426 | ret = pci_get_device(vendor, device, ret); |
| 427 | |
| 428 | if (!ret) |
| 429 | break; |
| 430 | |
| 431 | if (PCI_FUNC(ret->devfn) == func) |
| 432 | break; |
| 433 | } |
| 434 | |
| 435 | return ret; |
| 436 | } |
| 437 | |
| 438 | static unsigned long __devinit i5100_npages(struct mem_ctl_info *mci, |
| 439 | int csrow) |
| 440 | { |
| 441 | struct i5100_priv *priv = mci->pvt_info; |
| 442 | const unsigned ctlr_rank = i5100_csrow_to_rank(mci, csrow); |
| 443 | const unsigned ctlr = i5100_csrow_to_cntlr(mci, csrow); |
| 444 | unsigned addr_lines; |
| 445 | |
| 446 | /* dimm present? */ |
| 447 | if (!priv->mtr[ctlr][ctlr_rank].present) |
| 448 | return 0ULL; |
| 449 | |
| 450 | addr_lines = |
| 451 | I5100_DIMM_ADDR_LINES + |
| 452 | priv->mtr[ctlr][ctlr_rank].numcol + |
| 453 | priv->mtr[ctlr][ctlr_rank].numrow + |
| 454 | priv->mtr[ctlr][ctlr_rank].numbank; |
| 455 | |
| 456 | return (unsigned long) |
| 457 | ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE); |
| 458 | } |
| 459 | |
| 460 | static void __devinit i5100_init_mtr(struct mem_ctl_info *mci) |
| 461 | { |
| 462 | struct i5100_priv *priv = mci->pvt_info; |
| 463 | struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; |
| 464 | int i; |
| 465 | |
| 466 | for (i = 0; i < I5100_MAX_CTLRS; i++) { |
| 467 | int j; |
| 468 | struct pci_dev *pdev = mms[i]; |
| 469 | |
| 470 | for (j = 0; j < I5100_MAX_RANKS_PER_CTLR; j++) { |
| 471 | const unsigned addr = |
| 472 | (j < 4) ? I5100_MTR_0 + j * 2 : |
| 473 | I5100_MTR_4 + (j - 4) * 2; |
| 474 | u16 w; |
| 475 | |
| 476 | pci_read_config_word(pdev, addr, &w); |
| 477 | |
| 478 | priv->mtr[i][j].present = I5100_MTR_PRESENT(w); |
| 479 | priv->mtr[i][j].ethrottle = I5100_MTR_ETHROTTLE(w); |
| 480 | priv->mtr[i][j].width = 4 + 4 * I5100_MTR_WIDTH(w); |
| 481 | priv->mtr[i][j].numbank = 2 + I5100_MTR_NUMBANK(w); |
| 482 | priv->mtr[i][j].numrow = 13 + I5100_MTR_NUMROW(w); |
| 483 | priv->mtr[i][j].numcol = 10 + I5100_MTR_NUMCOL(w); |
| 484 | } |
| 485 | } |
| 486 | } |
| 487 | |
| 488 | /* |
| 489 | * FIXME: make this into a real i2c adapter (so that dimm-decode |
| 490 | * will work)? |
| 491 | */ |
| 492 | static int i5100_read_spd_byte(const struct mem_ctl_info *mci, |
| 493 | u8 ch, u8 slot, u8 addr, u8 *byte) |
| 494 | { |
| 495 | struct i5100_priv *priv = mci->pvt_info; |
| 496 | u16 w; |
| 497 | u32 dw; |
| 498 | unsigned long et; |
| 499 | |
| 500 | pci_read_config_word(priv->mc, I5100_SPDDATA, &w); |
| 501 | if (I5100_SPDDATA_BUSY(w)) |
| 502 | return -1; |
| 503 | |
| 504 | dw = I5100_SPDCMD_DTI(0xa) | |
| 505 | I5100_SPDCMD_CKOVRD(1) | |
| 506 | I5100_SPDCMD_SA(ch * 4 + slot) | |
| 507 | I5100_SPDCMD_BA(addr) | |
| 508 | I5100_SPDCMD_DATA(0) | |
| 509 | I5100_SPDCMD_CMD(0); |
| 510 | pci_write_config_dword(priv->mc, I5100_SPDCMD, dw); |
| 511 | |
| 512 | /* wait up to 100ms */ |
| 513 | et = jiffies + HZ / 10; |
| 514 | udelay(100); |
| 515 | while (1) { |
| 516 | pci_read_config_word(priv->mc, I5100_SPDDATA, &w); |
| 517 | if (!I5100_SPDDATA_BUSY(w)) |
| 518 | break; |
| 519 | udelay(100); |
| 520 | } |
| 521 | |
| 522 | if (!I5100_SPDDATA_RDO(w) || I5100_SPDDATA_SBE(w)) |
| 523 | return -1; |
| 524 | |
| 525 | *byte = I5100_SPDDATA_DATA(w); |
| 526 | |
| 527 | return 0; |
| 528 | } |
| 529 | |
| 530 | /* |
| 531 | * fill dimm chip select map |
| 532 | * |
| 533 | * FIXME: |
| 534 | * o only valid for 4 ranks per controller |
| 535 | * o not the only way to may chip selects to dimm slots |
| 536 | * o investigate if there is some way to obtain this map from the bios |
| 537 | */ |
| 538 | static void __devinit i5100_init_dimm_csmap(struct mem_ctl_info *mci) |
| 539 | { |
| 540 | struct i5100_priv *priv = mci->pvt_info; |
| 541 | int i; |
| 542 | |
| 543 | WARN_ON(priv->ranksperctlr != 4); |
| 544 | |
| 545 | for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CTLR; i++) { |
| 546 | int j; |
| 547 | |
| 548 | for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++) |
| 549 | priv->dimm_csmap[i][j] = -1; /* default NC */ |
| 550 | } |
| 551 | |
| 552 | /* only 2 chip selects per slot... */ |
| 553 | priv->dimm_csmap[0][0] = 0; |
| 554 | priv->dimm_csmap[0][1] = 3; |
| 555 | priv->dimm_csmap[1][0] = 1; |
| 556 | priv->dimm_csmap[1][1] = 2; |
| 557 | priv->dimm_csmap[2][0] = 2; |
| 558 | priv->dimm_csmap[3][0] = 3; |
| 559 | } |
| 560 | |
| 561 | static void __devinit i5100_init_dimm_layout(struct pci_dev *pdev, |
| 562 | struct mem_ctl_info *mci) |
| 563 | { |
| 564 | struct i5100_priv *priv = mci->pvt_info; |
| 565 | int i; |
| 566 | |
| 567 | for (i = 0; i < I5100_MAX_CTLRS; i++) { |
| 568 | int j; |
| 569 | |
| 570 | for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CTLR; j++) { |
| 571 | u8 rank; |
| 572 | |
| 573 | if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0) |
| 574 | priv->dimm_numrank[i][j] = 0; |
| 575 | else |
| 576 | priv->dimm_numrank[i][j] = (rank & 3) + 1; |
| 577 | } |
| 578 | } |
| 579 | |
| 580 | i5100_init_dimm_csmap(mci); |
| 581 | } |
| 582 | |
| 583 | static void __devinit i5100_init_interleaving(struct pci_dev *pdev, |
| 584 | struct mem_ctl_info *mci) |
| 585 | { |
| 586 | u16 w; |
| 587 | u32 dw; |
| 588 | struct i5100_priv *priv = mci->pvt_info; |
| 589 | struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; |
| 590 | int i; |
| 591 | |
| 592 | pci_read_config_word(pdev, I5100_TOLM, &w); |
| 593 | priv->tolm = (u64) I5100_TOLM_TOLM(w) * 256 * 1024 * 1024; |
| 594 | |
| 595 | pci_read_config_word(pdev, I5100_MIR0, &w); |
| 596 | priv->mir[0].limit = (u64) I5100_MIR_LIMIT(w) << 28; |
| 597 | priv->mir[0].way[1] = I5100_MIR_WAY1(w); |
| 598 | priv->mir[0].way[0] = I5100_MIR_WAY0(w); |
| 599 | |
| 600 | pci_read_config_word(pdev, I5100_MIR1, &w); |
| 601 | priv->mir[1].limit = (u64) I5100_MIR_LIMIT(w) << 28; |
| 602 | priv->mir[1].way[1] = I5100_MIR_WAY1(w); |
| 603 | priv->mir[1].way[0] = I5100_MIR_WAY0(w); |
| 604 | |
| 605 | pci_read_config_word(pdev, I5100_AMIR_0, &w); |
| 606 | priv->amir[0] = w; |
| 607 | pci_read_config_word(pdev, I5100_AMIR_1, &w); |
| 608 | priv->amir[1] = w; |
| 609 | |
| 610 | for (i = 0; i < I5100_MAX_CTLRS; i++) { |
| 611 | int j; |
| 612 | |
| 613 | for (j = 0; j < 5; j++) { |
| 614 | int k; |
| 615 | |
| 616 | pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw); |
| 617 | |
| 618 | priv->dmir[i][j].limit = |
| 619 | (u64) I5100_DMIR_LIMIT(dw) << 28; |
| 620 | for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++) |
| 621 | priv->dmir[i][j].rank[k] = |
| 622 | I5100_DMIR_RANK(dw, k); |
| 623 | } |
| 624 | } |
| 625 | |
| 626 | i5100_init_mtr(mci); |
| 627 | } |
| 628 | |
| 629 | static void __devinit i5100_init_csrows(struct mem_ctl_info *mci) |
| 630 | { |
| 631 | int i; |
| 632 | unsigned long total_pages = 0UL; |
| 633 | struct i5100_priv *priv = mci->pvt_info; |
| 634 | |
| 635 | for (i = 0; i < mci->nr_csrows; i++) { |
| 636 | const unsigned long npages = i5100_npages(mci, i); |
| 637 | const unsigned cntlr = i5100_csrow_to_cntlr(mci, i); |
| 638 | const unsigned rank = i5100_csrow_to_rank(mci, i); |
| 639 | |
| 640 | if (!npages) |
| 641 | continue; |
| 642 | |
| 643 | /* |
| 644 | * FIXME: these two are totally bogus -- I don't see how to |
| 645 | * map them correctly to this structure... |
| 646 | */ |
| 647 | mci->csrows[i].first_page = total_pages; |
| 648 | mci->csrows[i].last_page = total_pages + npages - 1; |
| 649 | mci->csrows[i].page_mask = 0UL; |
| 650 | |
| 651 | mci->csrows[i].nr_pages = npages; |
| 652 | mci->csrows[i].grain = 32; |
| 653 | mci->csrows[i].csrow_idx = i; |
| 654 | mci->csrows[i].dtype = |
| 655 | (priv->mtr[cntlr][rank].width == 4) ? DEV_X4 : DEV_X8; |
| 656 | mci->csrows[i].ue_count = 0; |
| 657 | mci->csrows[i].ce_count = 0; |
| 658 | mci->csrows[i].mtype = MEM_RDDR2; |
| 659 | mci->csrows[i].edac_mode = EDAC_SECDED; |
| 660 | mci->csrows[i].mci = mci; |
| 661 | mci->csrows[i].nr_channels = 1; |
| 662 | mci->csrows[i].channels[0].chan_idx = 0; |
| 663 | mci->csrows[i].channels[0].ce_count = 0; |
| 664 | mci->csrows[i].channels[0].csrow = mci->csrows + i; |
| 665 | snprintf(mci->csrows[i].channels[0].label, |
| 666 | sizeof(mci->csrows[i].channels[0].label), |
| 667 | "DIMM%u", i5100_rank_to_slot(mci, cntlr, rank)); |
| 668 | |
| 669 | total_pages += npages; |
| 670 | } |
| 671 | } |
| 672 | |
| 673 | static int __devinit i5100_init_one(struct pci_dev *pdev, |
| 674 | const struct pci_device_id *id) |
| 675 | { |
| 676 | int rc; |
| 677 | struct mem_ctl_info *mci; |
| 678 | struct i5100_priv *priv; |
| 679 | struct pci_dev *ch0mm, *ch1mm; |
| 680 | int ret = 0; |
| 681 | u32 dw; |
| 682 | int ranksperch; |
| 683 | |
| 684 | if (PCI_FUNC(pdev->devfn) != 1) |
| 685 | return -ENODEV; |
| 686 | |
| 687 | rc = pci_enable_device(pdev); |
| 688 | if (rc < 0) { |
| 689 | ret = rc; |
| 690 | goto bail; |
| 691 | } |
| 692 | |
Arthur Jones | 43920a5 | 2008-07-25 01:49:06 -0700 | [diff] [blame^] | 693 | /* ECC enabled? */ |
| 694 | pci_read_config_dword(pdev, I5100_MC, &dw); |
| 695 | if (!I5100_MC_ERRDETEN(dw)) { |
| 696 | printk(KERN_INFO "i5100_edac: ECC not enabled.\n"); |
| 697 | ret = -ENODEV; |
| 698 | goto bail; |
| 699 | } |
| 700 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 701 | /* figure out how many ranks, from strapped state of 48GB_Mode input */ |
| 702 | pci_read_config_dword(pdev, I5100_MS, &dw); |
| 703 | ranksperch = !!(dw & (1 << 8)) * 2 + 4; |
| 704 | |
| 705 | if (ranksperch != 4) { |
| 706 | /* FIXME: get 6 ranks / controller to work - need hw... */ |
| 707 | printk(KERN_INFO "i5100_edac: unsupported configuration.\n"); |
| 708 | ret = -ENODEV; |
| 709 | goto bail; |
| 710 | } |
| 711 | |
| 712 | /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */ |
| 713 | ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, |
| 714 | PCI_DEVICE_ID_INTEL_5100_21, 0); |
| 715 | if (!ch0mm) |
| 716 | return -ENODEV; |
| 717 | |
| 718 | rc = pci_enable_device(ch0mm); |
| 719 | if (rc < 0) { |
| 720 | ret = rc; |
| 721 | goto bail_ch0; |
| 722 | } |
| 723 | |
| 724 | /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */ |
| 725 | ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, |
| 726 | PCI_DEVICE_ID_INTEL_5100_22, 0); |
| 727 | if (!ch1mm) { |
| 728 | ret = -ENODEV; |
| 729 | goto bail_ch0; |
| 730 | } |
| 731 | |
| 732 | rc = pci_enable_device(ch1mm); |
| 733 | if (rc < 0) { |
| 734 | ret = rc; |
| 735 | goto bail_ch1; |
| 736 | } |
| 737 | |
| 738 | mci = edac_mc_alloc(sizeof(*priv), ranksperch * 2, 1, 0); |
| 739 | if (!mci) { |
| 740 | ret = -ENOMEM; |
| 741 | goto bail_ch1; |
| 742 | } |
| 743 | |
| 744 | mci->dev = &pdev->dev; |
| 745 | |
| 746 | priv = mci->pvt_info; |
| 747 | priv->ranksperctlr = ranksperch; |
| 748 | priv->mc = pdev; |
| 749 | priv->ch0mm = ch0mm; |
| 750 | priv->ch1mm = ch1mm; |
| 751 | |
| 752 | i5100_init_dimm_layout(pdev, mci); |
| 753 | i5100_init_interleaving(pdev, mci); |
| 754 | |
| 755 | mci->mtype_cap = MEM_FLAG_FB_DDR2; |
| 756 | mci->edac_ctl_cap = EDAC_FLAG_SECDED; |
| 757 | mci->edac_cap = EDAC_FLAG_SECDED; |
| 758 | mci->mod_name = "i5100_edac.c"; |
| 759 | mci->mod_ver = "not versioned"; |
| 760 | mci->ctl_name = "i5100"; |
| 761 | mci->dev_name = pci_name(pdev); |
| 762 | mci->ctl_page_to_phys = i5100_ctl_page_to_phys; |
| 763 | |
| 764 | mci->edac_check = i5100_check_error; |
| 765 | |
| 766 | i5100_init_csrows(mci); |
| 767 | |
| 768 | /* this strange construction seems to be in every driver, dunno why */ |
| 769 | switch (edac_op_state) { |
| 770 | case EDAC_OPSTATE_POLL: |
| 771 | case EDAC_OPSTATE_NMI: |
| 772 | break; |
| 773 | default: |
| 774 | edac_op_state = EDAC_OPSTATE_POLL; |
| 775 | break; |
| 776 | } |
| 777 | |
| 778 | if (edac_mc_add_mc(mci)) { |
| 779 | ret = -ENODEV; |
| 780 | goto bail_mc; |
| 781 | } |
| 782 | |
| 783 | goto bail; |
| 784 | |
| 785 | bail_mc: |
| 786 | edac_mc_free(mci); |
| 787 | |
| 788 | bail_ch1: |
| 789 | pci_dev_put(ch1mm); |
| 790 | |
| 791 | bail_ch0: |
| 792 | pci_dev_put(ch0mm); |
| 793 | |
| 794 | bail: |
| 795 | return ret; |
| 796 | } |
| 797 | |
| 798 | static void __devexit i5100_remove_one(struct pci_dev *pdev) |
| 799 | { |
| 800 | struct mem_ctl_info *mci; |
| 801 | struct i5100_priv *priv; |
| 802 | |
| 803 | mci = edac_mc_del_mc(&pdev->dev); |
| 804 | |
| 805 | if (!mci) |
| 806 | return; |
| 807 | |
| 808 | priv = mci->pvt_info; |
| 809 | pci_dev_put(priv->ch0mm); |
| 810 | pci_dev_put(priv->ch1mm); |
| 811 | |
| 812 | edac_mc_free(mci); |
| 813 | } |
| 814 | |
| 815 | static const struct pci_device_id i5100_pci_tbl[] __devinitdata = { |
| 816 | /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */ |
| 817 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) }, |
| 818 | { 0, } |
| 819 | }; |
| 820 | MODULE_DEVICE_TABLE(pci, i5100_pci_tbl); |
| 821 | |
| 822 | static struct pci_driver i5100_driver = { |
| 823 | .name = KBUILD_BASENAME, |
| 824 | .probe = i5100_init_one, |
| 825 | .remove = __devexit_p(i5100_remove_one), |
| 826 | .id_table = i5100_pci_tbl, |
| 827 | }; |
| 828 | |
| 829 | static int __init i5100_init(void) |
| 830 | { |
| 831 | int pci_rc; |
| 832 | |
| 833 | pci_rc = pci_register_driver(&i5100_driver); |
| 834 | |
| 835 | return (pci_rc < 0) ? pci_rc : 0; |
| 836 | } |
| 837 | |
| 838 | static void __exit i5100_exit(void) |
| 839 | { |
| 840 | pci_unregister_driver(&i5100_driver); |
| 841 | } |
| 842 | |
| 843 | module_init(i5100_init); |
| 844 | module_exit(i5100_exit); |
| 845 | |
| 846 | MODULE_LICENSE("GPL"); |
| 847 | MODULE_AUTHOR |
| 848 | ("Arthur Jones <ajones@riverbed.com>"); |
| 849 | MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers"); |