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gerrit-public.fairphone.software / kernel / msm-4.19 / e5b2791d2a57e9da369bd75ae2a209bcce2ad4d3 / . / sound / soc / codecs / rt5677.c
blob: f0b751bf1d6c50e410181aede4432ef6048cbde9 [file] [log] [blame]
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1/*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/regmap.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/spi/spi.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
Axel Lin30f14b42014-06-10 08:57:36 +0800[diff] [blame]30#include "rl6231.h"
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]31#include "rt5677.h"
32
33#define RT5677_DEVICE_ID 0x6327
34
35#define RT5677_PR_RANGE_BASE (0xff + 1)
36#define RT5677_PR_SPACING 0x100
37
38#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
39
40static const struct regmap_range_cfg rt5677_ranges[] = {
41 {
42 .name = "PR",
43 .range_min = RT5677_PR_BASE,
44 .range_max = RT5677_PR_BASE + 0xfd,
45 .selector_reg = RT5677_PRIV_INDEX,
46 .selector_mask = 0xff,
47 .selector_shift = 0x0,
48 .window_start = RT5677_PRIV_DATA,
49 .window_len = 0x1,
50 },
51};
52
53static const struct reg_default init_list[] = {
54 {RT5677_PR_BASE + 0x3d, 0x364d},
55 {RT5677_PR_BASE + 0x17, 0x4fc0},
56 {RT5677_PR_BASE + 0x13, 0x0312},
57 {RT5677_PR_BASE + 0x1e, 0x0000},
58 {RT5677_PR_BASE + 0x12, 0x0eaa},
59 {RT5677_PR_BASE + 0x14, 0x018a},
60};
61#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
62
63static const struct reg_default rt5677_reg[] = {
64 {RT5677_RESET , 0x0000},
65 {RT5677_LOUT1 , 0xa800},
66 {RT5677_IN1 , 0x0000},
67 {RT5677_MICBIAS , 0x0000},
68 {RT5677_SLIMBUS_PARAM , 0x0000},
69 {RT5677_SLIMBUS_RX , 0x0000},
70 {RT5677_SLIMBUS_CTRL , 0x0000},
71 {RT5677_SIDETONE_CTRL , 0x000b},
72 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
73 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
74 {RT5677_DAC4_DIG_VOL , 0xafaf},
75 {RT5677_DAC3_DIG_VOL , 0xafaf},
76 {RT5677_DAC1_DIG_VOL , 0xafaf},
77 {RT5677_DAC2_DIG_VOL , 0xafaf},
78 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
79 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
80 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
81 {RT5677_STO1_2_ADC_BST , 0x0000},
82 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
83 {RT5677_ADC_BST_CTRL2 , 0x0000},
84 {RT5677_STO3_4_ADC_BST , 0x0000},
85 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
86 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
87 {RT5677_STO4_ADC_MIXER , 0xd4c0},
88 {RT5677_STO3_ADC_MIXER , 0xd4c0},
89 {RT5677_STO2_ADC_MIXER , 0xd4c0},
90 {RT5677_STO1_ADC_MIXER , 0xd4c0},
91 {RT5677_MONO_ADC_MIXER , 0xd4d1},
92 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
93 {RT5677_STO1_DAC_MIXER , 0xaaaa},
94 {RT5677_MONO_DAC_MIXER , 0xaaaa},
95 {RT5677_DD1_MIXER , 0xaaaa},
96 {RT5677_DD2_MIXER , 0xaaaa},
97 {RT5677_IF3_DATA , 0x0000},
98 {RT5677_IF4_DATA , 0x0000},
99 {RT5677_PDM_OUT_CTRL , 0x8888},
100 {RT5677_PDM_DATA_CTRL1 , 0x0000},
101 {RT5677_PDM_DATA_CTRL2 , 0x0000},
102 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
103 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
104 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
105 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
106 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
107 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
108 {RT5677_TDM1_CTRL1 , 0x0300},
109 {RT5677_TDM1_CTRL2 , 0x0000},
110 {RT5677_TDM1_CTRL3 , 0x4000},
111 {RT5677_TDM1_CTRL4 , 0x0123},
112 {RT5677_TDM1_CTRL5 , 0x4567},
113 {RT5677_TDM2_CTRL1 , 0x0300},
114 {RT5677_TDM2_CTRL2 , 0x0000},
115 {RT5677_TDM2_CTRL3 , 0x4000},
116 {RT5677_TDM2_CTRL4 , 0x0123},
117 {RT5677_TDM2_CTRL5 , 0x4567},
118 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
119 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
120 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
121 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
122 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
123 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
124 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
126 {RT5677_DMIC_CTRL1 , 0x1505},
127 {RT5677_DMIC_CTRL2 , 0x0055},
128 {RT5677_HAP_GENE_CTRL1 , 0x0111},
129 {RT5677_HAP_GENE_CTRL2 , 0x0064},
130 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
131 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
132 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
133 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
134 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
135 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
136 {RT5677_HAP_GENE_CTRL9 , 0xf000},
137 {RT5677_HAP_GENE_CTRL10 , 0x0000},
138 {RT5677_PWR_DIG1 , 0x0000},
139 {RT5677_PWR_DIG2 , 0x0000},
140 {RT5677_PWR_ANLG1 , 0x0055},
141 {RT5677_PWR_ANLG2 , 0x0000},
142 {RT5677_PWR_DSP1 , 0x0001},
143 {RT5677_PWR_DSP_ST , 0x0000},
144 {RT5677_PWR_DSP2 , 0x0000},
145 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
146 {RT5677_PRIV_INDEX , 0x0000},
147 {RT5677_PRIV_DATA , 0x0000},
148 {RT5677_I2S4_SDP , 0x8000},
149 {RT5677_I2S1_SDP , 0x8000},
150 {RT5677_I2S2_SDP , 0x8000},
151 {RT5677_I2S3_SDP , 0x8000},
152 {RT5677_CLK_TREE_CTRL1 , 0x1111},
153 {RT5677_CLK_TREE_CTRL2 , 0x1111},
154 {RT5677_CLK_TREE_CTRL3 , 0x0000},
155 {RT5677_PLL1_CTRL1 , 0x0000},
156 {RT5677_PLL1_CTRL2 , 0x0000},
157 {RT5677_PLL2_CTRL1 , 0x0c60},
158 {RT5677_PLL2_CTRL2 , 0x2000},
159 {RT5677_GLB_CLK1 , 0x0000},
160 {RT5677_GLB_CLK2 , 0x0000},
161 {RT5677_ASRC_1 , 0x0000},
162 {RT5677_ASRC_2 , 0x0000},
163 {RT5677_ASRC_3 , 0x0000},
164 {RT5677_ASRC_4 , 0x0000},
165 {RT5677_ASRC_5 , 0x0000},
166 {RT5677_ASRC_6 , 0x0000},
167 {RT5677_ASRC_7 , 0x0000},
168 {RT5677_ASRC_8 , 0x0000},
169 {RT5677_ASRC_9 , 0x0000},
170 {RT5677_ASRC_10 , 0x0000},
171 {RT5677_ASRC_11 , 0x0000},
172 {RT5677_ASRC_12 , 0x0008},
173 {RT5677_ASRC_13 , 0x0000},
174 {RT5677_ASRC_14 , 0x0000},
175 {RT5677_ASRC_15 , 0x0000},
176 {RT5677_ASRC_16 , 0x0000},
177 {RT5677_ASRC_17 , 0x0000},
178 {RT5677_ASRC_18 , 0x0000},
179 {RT5677_ASRC_19 , 0x0000},
180 {RT5677_ASRC_20 , 0x0000},
181 {RT5677_ASRC_21 , 0x000c},
182 {RT5677_ASRC_22 , 0x0000},
183 {RT5677_ASRC_23 , 0x0000},
184 {RT5677_VAD_CTRL1 , 0x2184},
185 {RT5677_VAD_CTRL2 , 0x010a},
186 {RT5677_VAD_CTRL3 , 0x0aea},
187 {RT5677_VAD_CTRL4 , 0x000c},
188 {RT5677_VAD_CTRL5 , 0x0000},
189 {RT5677_DSP_INB_CTRL1 , 0x0000},
190 {RT5677_DSP_INB_CTRL2 , 0x0000},
191 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
192 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
193 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
194 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
195 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
196 {RT5677_ADC_EQ_CTRL1 , 0x6000},
197 {RT5677_ADC_EQ_CTRL2 , 0x0000},
198 {RT5677_EQ_CTRL1 , 0xc000},
199 {RT5677_EQ_CTRL2 , 0x0000},
200 {RT5677_EQ_CTRL3 , 0x0000},
201 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
202 {RT5677_JD_CTRL1 , 0x0000},
203 {RT5677_JD_CTRL2 , 0x0000},
204 {RT5677_JD_CTRL3 , 0x0000},
205 {RT5677_IRQ_CTRL1 , 0x0000},
206 {RT5677_IRQ_CTRL2 , 0x0000},
207 {RT5677_GPIO_ST , 0x0000},
208 {RT5677_GPIO_CTRL1 , 0x0000},
209 {RT5677_GPIO_CTRL2 , 0x0000},
210 {RT5677_GPIO_CTRL3 , 0x0000},
211 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
212 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
213 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
214 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
215 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
216 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
217 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
218 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
219 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
220 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
221 {RT5677_MB_DRC_CTRL1 , 0x0f20},
222 {RT5677_DRC1_CTRL1 , 0x001f},
223 {RT5677_DRC1_CTRL2 , 0x020c},
224 {RT5677_DRC1_CTRL3 , 0x1f00},
225 {RT5677_DRC1_CTRL4 , 0x0000},
226 {RT5677_DRC1_CTRL5 , 0x0000},
227 {RT5677_DRC1_CTRL6 , 0x0029},
228 {RT5677_DRC2_CTRL1 , 0x001f},
229 {RT5677_DRC2_CTRL2 , 0x020c},
230 {RT5677_DRC2_CTRL3 , 0x1f00},
231 {RT5677_DRC2_CTRL4 , 0x0000},
232 {RT5677_DRC2_CTRL5 , 0x0000},
233 {RT5677_DRC2_CTRL6 , 0x0029},
234 {RT5677_DRC1_HL_CTRL1 , 0x8000},
235 {RT5677_DRC1_HL_CTRL2 , 0x0200},
236 {RT5677_DRC2_HL_CTRL1 , 0x8000},
237 {RT5677_DRC2_HL_CTRL2 , 0x0200},
238 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
239 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
240 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
241 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
242 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
243 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
244 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
245 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
246 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
247 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
248 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
249 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
250 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
251 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
252 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
253 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
254 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
255 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
256 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
257 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
258 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
259 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
260 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
261 {RT5677_DIG_MISC , 0x0000},
262 {RT5677_GEN_CTRL1 , 0x0000},
263 {RT5677_GEN_CTRL2 , 0x0000},
264 {RT5677_VENDOR_ID , 0x0000},
265 {RT5677_VENDOR_ID1 , 0x10ec},
266 {RT5677_VENDOR_ID2 , 0x6327},
267};
268
269static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
270{
271 int i;
272
273 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
274 if (reg >= rt5677_ranges[i].range_min &&
275 reg <= rt5677_ranges[i].range_max) {
276 return true;
277 }
278 }
279
280 switch (reg) {
281 case RT5677_RESET:
282 case RT5677_SLIMBUS_PARAM:
283 case RT5677_PDM_DATA_CTRL1:
284 case RT5677_PDM_DATA_CTRL2:
285 case RT5677_PDM1_DATA_CTRL4:
286 case RT5677_PDM2_DATA_CTRL4:
287 case RT5677_I2C_MASTER_CTRL1:
288 case RT5677_I2C_MASTER_CTRL7:
289 case RT5677_I2C_MASTER_CTRL8:
290 case RT5677_HAP_GENE_CTRL2:
291 case RT5677_PWR_DSP_ST:
292 case RT5677_PRIV_DATA:
293 case RT5677_PLL1_CTRL2:
294 case RT5677_PLL2_CTRL2:
295 case RT5677_ASRC_22:
296 case RT5677_ASRC_23:
297 case RT5677_VAD_CTRL5:
298 case RT5677_ADC_EQ_CTRL1:
299 case RT5677_EQ_CTRL1:
300 case RT5677_IRQ_CTRL1:
301 case RT5677_IRQ_CTRL2:
302 case RT5677_GPIO_ST:
303 case RT5677_DSP_INB1_SRC_CTRL4:
304 case RT5677_DSP_INB2_SRC_CTRL4:
305 case RT5677_DSP_INB3_SRC_CTRL4:
306 case RT5677_DSP_OUTB1_SRC_CTRL4:
307 case RT5677_DSP_OUTB2_SRC_CTRL4:
308 case RT5677_VENDOR_ID:
309 case RT5677_VENDOR_ID1:
310 case RT5677_VENDOR_ID2:
311 return true;
312 default:
313 return false;
314 }
315}
316
317static bool rt5677_readable_register(struct device *dev, unsigned int reg)
318{
319 int i;
320
321 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
322 if (reg >= rt5677_ranges[i].range_min &&
323 reg <= rt5677_ranges[i].range_max) {
324 return true;
325 }
326 }
327
328 switch (reg) {
329 case RT5677_RESET:
330 case RT5677_LOUT1:
331 case RT5677_IN1:
332 case RT5677_MICBIAS:
333 case RT5677_SLIMBUS_PARAM:
334 case RT5677_SLIMBUS_RX:
335 case RT5677_SLIMBUS_CTRL:
336 case RT5677_SIDETONE_CTRL:
337 case RT5677_ANA_DAC1_2_3_SRC:
338 case RT5677_IF_DSP_DAC3_4_MIXER:
339 case RT5677_DAC4_DIG_VOL:
340 case RT5677_DAC3_DIG_VOL:
341 case RT5677_DAC1_DIG_VOL:
342 case RT5677_DAC2_DIG_VOL:
343 case RT5677_IF_DSP_DAC2_MIXER:
344 case RT5677_STO1_ADC_DIG_VOL:
345 case RT5677_MONO_ADC_DIG_VOL:
346 case RT5677_STO1_2_ADC_BST:
347 case RT5677_STO2_ADC_DIG_VOL:
348 case RT5677_ADC_BST_CTRL2:
349 case RT5677_STO3_4_ADC_BST:
350 case RT5677_STO3_ADC_DIG_VOL:
351 case RT5677_STO4_ADC_DIG_VOL:
352 case RT5677_STO4_ADC_MIXER:
353 case RT5677_STO3_ADC_MIXER:
354 case RT5677_STO2_ADC_MIXER:
355 case RT5677_STO1_ADC_MIXER:
356 case RT5677_MONO_ADC_MIXER:
357 case RT5677_ADC_IF_DSP_DAC1_MIXER:
358 case RT5677_STO1_DAC_MIXER:
359 case RT5677_MONO_DAC_MIXER:
360 case RT5677_DD1_MIXER:
361 case RT5677_DD2_MIXER:
362 case RT5677_IF3_DATA:
363 case RT5677_IF4_DATA:
364 case RT5677_PDM_OUT_CTRL:
365 case RT5677_PDM_DATA_CTRL1:
366 case RT5677_PDM_DATA_CTRL2:
367 case RT5677_PDM1_DATA_CTRL2:
368 case RT5677_PDM1_DATA_CTRL3:
369 case RT5677_PDM1_DATA_CTRL4:
370 case RT5677_PDM2_DATA_CTRL2:
371 case RT5677_PDM2_DATA_CTRL3:
372 case RT5677_PDM2_DATA_CTRL4:
373 case RT5677_TDM1_CTRL1:
374 case RT5677_TDM1_CTRL2:
375 case RT5677_TDM1_CTRL3:
376 case RT5677_TDM1_CTRL4:
377 case RT5677_TDM1_CTRL5:
378 case RT5677_TDM2_CTRL1:
379 case RT5677_TDM2_CTRL2:
380 case RT5677_TDM2_CTRL3:
381 case RT5677_TDM2_CTRL4:
382 case RT5677_TDM2_CTRL5:
383 case RT5677_I2C_MASTER_CTRL1:
384 case RT5677_I2C_MASTER_CTRL2:
385 case RT5677_I2C_MASTER_CTRL3:
386 case RT5677_I2C_MASTER_CTRL4:
387 case RT5677_I2C_MASTER_CTRL5:
388 case RT5677_I2C_MASTER_CTRL6:
389 case RT5677_I2C_MASTER_CTRL7:
390 case RT5677_I2C_MASTER_CTRL8:
391 case RT5677_DMIC_CTRL1:
392 case RT5677_DMIC_CTRL2:
393 case RT5677_HAP_GENE_CTRL1:
394 case RT5677_HAP_GENE_CTRL2:
395 case RT5677_HAP_GENE_CTRL3:
396 case RT5677_HAP_GENE_CTRL4:
397 case RT5677_HAP_GENE_CTRL5:
398 case RT5677_HAP_GENE_CTRL6:
399 case RT5677_HAP_GENE_CTRL7:
400 case RT5677_HAP_GENE_CTRL8:
401 case RT5677_HAP_GENE_CTRL9:
402 case RT5677_HAP_GENE_CTRL10:
403 case RT5677_PWR_DIG1:
404 case RT5677_PWR_DIG2:
405 case RT5677_PWR_ANLG1:
406 case RT5677_PWR_ANLG2:
407 case RT5677_PWR_DSP1:
408 case RT5677_PWR_DSP_ST:
409 case RT5677_PWR_DSP2:
410 case RT5677_ADC_DAC_HPF_CTRL1:
411 case RT5677_PRIV_INDEX:
412 case RT5677_PRIV_DATA:
413 case RT5677_I2S4_SDP:
414 case RT5677_I2S1_SDP:
415 case RT5677_I2S2_SDP:
416 case RT5677_I2S3_SDP:
417 case RT5677_CLK_TREE_CTRL1:
418 case RT5677_CLK_TREE_CTRL2:
419 case RT5677_CLK_TREE_CTRL3:
420 case RT5677_PLL1_CTRL1:
421 case RT5677_PLL1_CTRL2:
422 case RT5677_PLL2_CTRL1:
423 case RT5677_PLL2_CTRL2:
424 case RT5677_GLB_CLK1:
425 case RT5677_GLB_CLK2:
426 case RT5677_ASRC_1:
427 case RT5677_ASRC_2:
428 case RT5677_ASRC_3:
429 case RT5677_ASRC_4:
430 case RT5677_ASRC_5:
431 case RT5677_ASRC_6:
432 case RT5677_ASRC_7:
433 case RT5677_ASRC_8:
434 case RT5677_ASRC_9:
435 case RT5677_ASRC_10:
436 case RT5677_ASRC_11:
437 case RT5677_ASRC_12:
438 case RT5677_ASRC_13:
439 case RT5677_ASRC_14:
440 case RT5677_ASRC_15:
441 case RT5677_ASRC_16:
442 case RT5677_ASRC_17:
443 case RT5677_ASRC_18:
444 case RT5677_ASRC_19:
445 case RT5677_ASRC_20:
446 case RT5677_ASRC_21:
447 case RT5677_ASRC_22:
448 case RT5677_ASRC_23:
449 case RT5677_VAD_CTRL1:
450 case RT5677_VAD_CTRL2:
451 case RT5677_VAD_CTRL3:
452 case RT5677_VAD_CTRL4:
453 case RT5677_VAD_CTRL5:
454 case RT5677_DSP_INB_CTRL1:
455 case RT5677_DSP_INB_CTRL2:
456 case RT5677_DSP_IN_OUTB_CTRL:
457 case RT5677_DSP_OUTB0_1_DIG_VOL:
458 case RT5677_DSP_OUTB2_3_DIG_VOL:
459 case RT5677_DSP_OUTB4_5_DIG_VOL:
460 case RT5677_DSP_OUTB6_7_DIG_VOL:
461 case RT5677_ADC_EQ_CTRL1:
462 case RT5677_ADC_EQ_CTRL2:
463 case RT5677_EQ_CTRL1:
464 case RT5677_EQ_CTRL2:
465 case RT5677_EQ_CTRL3:
466 case RT5677_SOFT_VOL_ZERO_CROSS1:
467 case RT5677_JD_CTRL1:
468 case RT5677_JD_CTRL2:
469 case RT5677_JD_CTRL3:
470 case RT5677_IRQ_CTRL1:
471 case RT5677_IRQ_CTRL2:
472 case RT5677_GPIO_ST:
473 case RT5677_GPIO_CTRL1:
474 case RT5677_GPIO_CTRL2:
475 case RT5677_GPIO_CTRL3:
476 case RT5677_STO1_ADC_HI_FILTER1:
477 case RT5677_STO1_ADC_HI_FILTER2:
478 case RT5677_MONO_ADC_HI_FILTER1:
479 case RT5677_MONO_ADC_HI_FILTER2:
480 case RT5677_STO2_ADC_HI_FILTER1:
481 case RT5677_STO2_ADC_HI_FILTER2:
482 case RT5677_STO3_ADC_HI_FILTER1:
483 case RT5677_STO3_ADC_HI_FILTER2:
484 case RT5677_STO4_ADC_HI_FILTER1:
485 case RT5677_STO4_ADC_HI_FILTER2:
486 case RT5677_MB_DRC_CTRL1:
487 case RT5677_DRC1_CTRL1:
488 case RT5677_DRC1_CTRL2:
489 case RT5677_DRC1_CTRL3:
490 case RT5677_DRC1_CTRL4:
491 case RT5677_DRC1_CTRL5:
492 case RT5677_DRC1_CTRL6:
493 case RT5677_DRC2_CTRL1:
494 case RT5677_DRC2_CTRL2:
495 case RT5677_DRC2_CTRL3:
496 case RT5677_DRC2_CTRL4:
497 case RT5677_DRC2_CTRL5:
498 case RT5677_DRC2_CTRL6:
499 case RT5677_DRC1_HL_CTRL1:
500 case RT5677_DRC1_HL_CTRL2:
501 case RT5677_DRC2_HL_CTRL1:
502 case RT5677_DRC2_HL_CTRL2:
503 case RT5677_DSP_INB1_SRC_CTRL1:
504 case RT5677_DSP_INB1_SRC_CTRL2:
505 case RT5677_DSP_INB1_SRC_CTRL3:
506 case RT5677_DSP_INB1_SRC_CTRL4:
507 case RT5677_DSP_INB2_SRC_CTRL1:
508 case RT5677_DSP_INB2_SRC_CTRL2:
509 case RT5677_DSP_INB2_SRC_CTRL3:
510 case RT5677_DSP_INB2_SRC_CTRL4:
511 case RT5677_DSP_INB3_SRC_CTRL1:
512 case RT5677_DSP_INB3_SRC_CTRL2:
513 case RT5677_DSP_INB3_SRC_CTRL3:
514 case RT5677_DSP_INB3_SRC_CTRL4:
515 case RT5677_DSP_OUTB1_SRC_CTRL1:
516 case RT5677_DSP_OUTB1_SRC_CTRL2:
517 case RT5677_DSP_OUTB1_SRC_CTRL3:
518 case RT5677_DSP_OUTB1_SRC_CTRL4:
519 case RT5677_DSP_OUTB2_SRC_CTRL1:
520 case RT5677_DSP_OUTB2_SRC_CTRL2:
521 case RT5677_DSP_OUTB2_SRC_CTRL3:
522 case RT5677_DSP_OUTB2_SRC_CTRL4:
523 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
524 case RT5677_DSP_OUTB_45_MIXER_CTRL:
525 case RT5677_DSP_OUTB_67_MIXER_CTRL:
526 case RT5677_DIG_MISC:
527 case RT5677_GEN_CTRL1:
528 case RT5677_GEN_CTRL2:
529 case RT5677_VENDOR_ID:
530 case RT5677_VENDOR_ID1:
531 case RT5677_VENDOR_ID2:
532 return true;
533 default:
534 return false;
535 }
536}
537
538static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
539static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
540static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
541static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
542static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
543
544/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
545static unsigned int bst_tlv[] = {
546 TLV_DB_RANGE_HEAD(7),
547 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
548 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
549 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
550 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
551 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
552 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
553 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
554};
555
556static const struct snd_kcontrol_new rt5677_snd_controls[] = {
557 /* OUTPUT Control */
558 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
559 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
560 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
561 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
562 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
563 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
564
565 /* DAC Digital Volume */
566 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
567 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
568 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
569 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
570 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
571 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
572 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
573 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
574
575 /* IN1/IN2 Control */
576 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
577 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
578
579 /* ADC Digital Volume Control */
580 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
581 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
582 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
583 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
584 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
585 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
586 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
587 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
588 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
589 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
590
591 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
592 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
593 adc_vol_tlv),
594 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
595 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
596 adc_vol_tlv),
597 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
598 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
599 adc_vol_tlv),
600 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
601 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
602 adc_vol_tlv),
603 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
604 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0,
605 adc_vol_tlv),
606
607 /* ADC Boost Volume Control */
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]608 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]609 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
610 adc_bst_tlv),
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]611 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]612 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
613 adc_bst_tlv),
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]614 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]615 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
616 adc_bst_tlv),
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]617 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]618 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
619 adc_bst_tlv),
Oder Chiou80220f22014-06-10 14:35:25 +0800[diff] [blame]620 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]621 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
622 adc_bst_tlv),
623};
624
625/**
626 * set_dmic_clk - Set parameter of dmic.
627 *
628 * @w: DAPM widget.
629 * @kcontrol: The kcontrol of this widget.
630 * @event: Event id.
631 *
632 * Choose dmic clock between 1MHz and 3MHz.
633 * It is better for clock to approximate 3MHz.
634 */
635static int set_dmic_clk(struct snd_soc_dapm_widget *w,
636 struct snd_kcontrol *kcontrol, int event)
637{
638 struct snd_soc_codec *codec = w->codec;
639 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
Axel Lin9a535812014-06-03 10:58:58 +0800[diff] [blame]640 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]641
642 if (idx < 0)
643 dev_err(codec->dev, "Failed to set DMIC clock\n");
644 else
645 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
646 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
647 return idx;
648}
649
650static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
651 struct snd_soc_dapm_widget *sink)
652{
653 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
654 unsigned int val;
655
656 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
657 val &= RT5677_SCLK_SRC_MASK;
658 if (val == RT5677_SCLK_SRC_PLL1)
659 return 1;
660 else
661 return 0;
662}
663
664/* Digital Mixer */
665static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
666 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
667 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
668 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
669 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
670};
671
672static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
673 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
674 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
675 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
676 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
677};
678
679static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
680 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
681 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
682 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
683 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
684};
685
686static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
687 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
688 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
689 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
690 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
691};
692
693static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
694 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
695 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
696 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
697 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
698};
699
700static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
701 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
702 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
703 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
704 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
705};
706
707static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
708 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
709 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
710 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
711 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
712};
713
714static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
715 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
716 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
717 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
718 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
719};
720
721static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
722 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
723 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
724 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
725 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
726};
727
728static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
729 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
730 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
731 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
732 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
733};
734
735static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
736 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
737 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
738 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
739 RT5677_M_DAC1_L_SFT, 1, 1),
740};
741
742static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
743 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
744 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
745 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
746 RT5677_M_DAC1_R_SFT, 1, 1),
747};
748
749static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
750 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
751 RT5677_M_ST_DAC1_L_SFT, 1, 1),
752 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
753 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
754 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
755 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
756 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
757 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
758};
759
760static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
761 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
762 RT5677_M_ST_DAC1_R_SFT, 1, 1),
763 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
764 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
765 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
766 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
767 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
768 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
769};
770
771static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
772 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
773 RT5677_M_ST_DAC2_L_SFT, 1, 1),
774 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
775 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
776 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
777 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
778 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
779 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
780};
781
782static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
783 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
784 RT5677_M_ST_DAC2_R_SFT, 1, 1),
785 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
786 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
787 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
788 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
789 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
790 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
791};
792
793static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
794 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
795 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
796 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
797 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
798 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
799 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
800 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
801 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
802};
803
804static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
805 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
806 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
807 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
808 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
809 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
810 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
811 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
812 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
813};
814
815static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
816 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
817 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
818 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
819 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
820 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
821 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
822 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
823 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
824};
825
826static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
827 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
828 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
829 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
830 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
831 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
832 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
833 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
834 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
835};
836
837static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
838 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
839 RT5677_DSP_IB_01_H_SFT, 1, 1),
840 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
841 RT5677_DSP_IB_23_H_SFT, 1, 1),
842 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
843 RT5677_DSP_IB_45_H_SFT, 1, 1),
844 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
845 RT5677_DSP_IB_6_H_SFT, 1, 1),
846 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
847 RT5677_DSP_IB_7_H_SFT, 1, 1),
848 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
849 RT5677_DSP_IB_8_H_SFT, 1, 1),
850 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
851 RT5677_DSP_IB_9_H_SFT, 1, 1),
852};
853
854static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
855 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
856 RT5677_DSP_IB_01_L_SFT, 1, 1),
857 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
858 RT5677_DSP_IB_23_L_SFT, 1, 1),
859 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
860 RT5677_DSP_IB_45_L_SFT, 1, 1),
861 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
862 RT5677_DSP_IB_6_L_SFT, 1, 1),
863 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
864 RT5677_DSP_IB_7_L_SFT, 1, 1),
865 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
866 RT5677_DSP_IB_8_L_SFT, 1, 1),
867 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
868 RT5677_DSP_IB_9_L_SFT, 1, 1),
869};
870
871static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
872 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
873 RT5677_DSP_IB_01_H_SFT, 1, 1),
874 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
875 RT5677_DSP_IB_23_H_SFT, 1, 1),
876 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
877 RT5677_DSP_IB_45_H_SFT, 1, 1),
878 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
879 RT5677_DSP_IB_6_H_SFT, 1, 1),
880 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
881 RT5677_DSP_IB_7_H_SFT, 1, 1),
882 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
883 RT5677_DSP_IB_8_H_SFT, 1, 1),
884 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
885 RT5677_DSP_IB_9_H_SFT, 1, 1),
886};
887
888static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
889 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
890 RT5677_DSP_IB_01_L_SFT, 1, 1),
891 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
892 RT5677_DSP_IB_23_L_SFT, 1, 1),
893 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
894 RT5677_DSP_IB_45_L_SFT, 1, 1),
895 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
896 RT5677_DSP_IB_6_L_SFT, 1, 1),
897 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
898 RT5677_DSP_IB_7_L_SFT, 1, 1),
899 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
900 RT5677_DSP_IB_8_L_SFT, 1, 1),
901 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
902 RT5677_DSP_IB_9_L_SFT, 1, 1),
903};
904
905static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
906 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
907 RT5677_DSP_IB_01_H_SFT, 1, 1),
908 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
909 RT5677_DSP_IB_23_H_SFT, 1, 1),
910 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
911 RT5677_DSP_IB_45_H_SFT, 1, 1),
912 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
913 RT5677_DSP_IB_6_H_SFT, 1, 1),
914 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
915 RT5677_DSP_IB_7_H_SFT, 1, 1),
916 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
917 RT5677_DSP_IB_8_H_SFT, 1, 1),
918 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
919 RT5677_DSP_IB_9_H_SFT, 1, 1),
920};
921
922static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
923 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
924 RT5677_DSP_IB_01_L_SFT, 1, 1),
925 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
926 RT5677_DSP_IB_23_L_SFT, 1, 1),
927 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
928 RT5677_DSP_IB_45_L_SFT, 1, 1),
929 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
930 RT5677_DSP_IB_6_L_SFT, 1, 1),
931 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
932 RT5677_DSP_IB_7_L_SFT, 1, 1),
933 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
934 RT5677_DSP_IB_8_L_SFT, 1, 1),
935 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
936 RT5677_DSP_IB_9_L_SFT, 1, 1),
937};
938
939
940/* Mux */
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]941/* DAC1 L/R Source */ /* MX-29 [10:8] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]942static const char * const rt5677_dac1_src[] = {
943 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
944 "OB 01"
945};
946
947static SOC_ENUM_SINGLE_DECL(
948 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
949 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
950
951static const struct snd_kcontrol_new rt5677_dac1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]952 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]953
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]954/* ADDA1 L/R Source */ /* MX-29 [1:0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]955static const char * const rt5677_adda1_src[] = {
956 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
957};
958
959static SOC_ENUM_SINGLE_DECL(
960 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
961 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
962
963static const struct snd_kcontrol_new rt5677_adda1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]964 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]965
966
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]967/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]968static const char * const rt5677_dac2l_src[] = {
969 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
970 "OB 2",
971};
972
973static SOC_ENUM_SINGLE_DECL(
974 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
975 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
976
977static const struct snd_kcontrol_new rt5677_dac2_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]978 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]979
980static const char * const rt5677_dac2r_src[] = {
981 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
982 "OB 3", "Haptic Generator", "VAD ADC"
983};
984
985static SOC_ENUM_SINGLE_DECL(
986 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
987 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
988
989static const struct snd_kcontrol_new rt5677_dac2_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]990 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]991
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]992/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]993static const char * const rt5677_dac3l_src[] = {
994 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
995 "SLB DAC 4", "OB 4"
996};
997
998static SOC_ENUM_SINGLE_DECL(
999 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1000 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1001
1002static const struct snd_kcontrol_new rt5677_dac3_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1003 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1004
1005static const char * const rt5677_dac3r_src[] = {
1006 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1007 "SLB DAC 5", "OB 5"
1008};
1009
1010static SOC_ENUM_SINGLE_DECL(
1011 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1012 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1013
1014static const struct snd_kcontrol_new rt5677_dac3_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1015 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1016
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1017/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1018static const char * const rt5677_dac4l_src[] = {
1019 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1020 "SLB DAC 6", "OB 6"
1021};
1022
1023static SOC_ENUM_SINGLE_DECL(
1024 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1025 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1026
1027static const struct snd_kcontrol_new rt5677_dac4_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1028 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1029
1030static const char * const rt5677_dac4r_src[] = {
1031 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1032 "SLB DAC 7", "OB 7"
1033};
1034
1035static SOC_ENUM_SINGLE_DECL(
1036 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1037 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1038
1039static const struct snd_kcontrol_new rt5677_dac4_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1040 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1041
1042/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1043static const char * const rt5677_iob_bypass_src[] = {
1044 "Bypass", "Pass SRC"
1045};
1046
1047static SOC_ENUM_SINGLE_DECL(
1048 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1049 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1050
1051static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1052 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1053
1054static SOC_ENUM_SINGLE_DECL(
1055 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1056 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1057
1058static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1059 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1060
1061static SOC_ENUM_SINGLE_DECL(
1062 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1063 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1064
1065static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1066 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1067
1068static SOC_ENUM_SINGLE_DECL(
1069 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1070 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1071
1072static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1073 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1074
1075static SOC_ENUM_SINGLE_DECL(
1076 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1077 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1078
1079static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1080 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1081
1082/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1083static const char * const rt5677_stereo_adc2_src[] = {
1084 "DD MIX1", "DMIC", "Stereo DAC MIX"
1085};
1086
1087static SOC_ENUM_SINGLE_DECL(
1088 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1089 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1090
1091static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1092 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1093
1094static SOC_ENUM_SINGLE_DECL(
1095 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1096 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1097
1098static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1099 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1100
1101static SOC_ENUM_SINGLE_DECL(
1102 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1103 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1104
1105static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1106 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1107
1108/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1109static const char * const rt5677_dmic_src[] = {
1110 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1111};
1112
1113static SOC_ENUM_SINGLE_DECL(
1114 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1115 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1116
1117static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1118 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1119
1120static SOC_ENUM_SINGLE_DECL(
1121 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1122 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1123
1124static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1125 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1126
1127static SOC_ENUM_SINGLE_DECL(
1128 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1129 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1130
1131static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1132 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1133
1134static SOC_ENUM_SINGLE_DECL(
1135 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1136 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1137
1138static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1139 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1140
1141static SOC_ENUM_SINGLE_DECL(
1142 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1143 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1144
1145static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1146 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1147
1148static SOC_ENUM_SINGLE_DECL(
1149 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1150 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1151
1152static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1153 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1154
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1155/* Stereo2 ADC Source */ /* MX-26 [0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1156static const char * const rt5677_stereo2_adc_lr_src[] = {
1157 "L", "LR"
1158};
1159
1160static SOC_ENUM_SINGLE_DECL(
1161 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1162 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1163
1164static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1165 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1166
1167/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1168static const char * const rt5677_stereo_adc1_src[] = {
1169 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1170};
1171
1172static SOC_ENUM_SINGLE_DECL(
1173 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1174 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1175
1176static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1177 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1178
1179static SOC_ENUM_SINGLE_DECL(
1180 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1181 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1182
1183static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1184 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1185
1186static SOC_ENUM_SINGLE_DECL(
1187 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1188 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1189
1190static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1191 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1192
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1193/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1194static const char * const rt5677_mono_adc2_l_src[] = {
1195 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1196};
1197
1198static SOC_ENUM_SINGLE_DECL(
1199 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1200 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1201
1202static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1203 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1204
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1205/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1206static const char * const rt5677_mono_adc1_l_src[] = {
1207 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1208};
1209
1210static SOC_ENUM_SINGLE_DECL(
1211 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1212 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1213
1214static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1215 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1216
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1217/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1218static const char * const rt5677_mono_adc2_r_src[] = {
1219 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1220};
1221
1222static SOC_ENUM_SINGLE_DECL(
1223 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1224 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1225
1226static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1227 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1228
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1229/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1230static const char * const rt5677_mono_adc1_r_src[] = {
1231 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1232};
1233
1234static SOC_ENUM_SINGLE_DECL(
1235 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1236 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1237
1238static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1239 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1240
1241/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1242static const char * const rt5677_stereo4_adc2_src[] = {
1243 "DD MIX1", "DMIC", "DD MIX2"
1244};
1245
1246static SOC_ENUM_SINGLE_DECL(
1247 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1248 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1249
1250static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1251 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1252
1253
1254/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1255static const char * const rt5677_stereo4_adc1_src[] = {
1256 "DD MIX1", "ADC1/2", "DD MIX2"
1257};
1258
1259static SOC_ENUM_SINGLE_DECL(
1260 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1261 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1262
1263static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1264 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1265
1266/* InBound0/1 Source */ /* MX-A3 [14:12] */
1267static const char * const rt5677_inbound01_src[] = {
1268 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1269 "VAD ADC/DAC1 FS"
1270};
1271
1272static SOC_ENUM_SINGLE_DECL(
1273 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1274 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1275
1276static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1277 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1278
1279/* InBound2/3 Source */ /* MX-A3 [10:8] */
1280static const char * const rt5677_inbound23_src[] = {
1281 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1282 "DAC1 FS", "IF4 DAC"
1283};
1284
1285static SOC_ENUM_SINGLE_DECL(
1286 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1287 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1288
1289static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1290 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1291
1292/* InBound4/5 Source */ /* MX-A3 [6:4] */
1293static const char * const rt5677_inbound45_src[] = {
1294 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1295 "IF3 DAC"
1296};
1297
1298static SOC_ENUM_SINGLE_DECL(
1299 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1300 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1301
1302static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1303 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1304
1305/* InBound6 Source */ /* MX-A3 [2:0] */
1306static const char * const rt5677_inbound6_src[] = {
1307 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1308 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1309};
1310
1311static SOC_ENUM_SINGLE_DECL(
1312 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1313 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1314
1315static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1316 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1317
1318/* InBound7 Source */ /* MX-A4 [14:12] */
1319static const char * const rt5677_inbound7_src[] = {
1320 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1321 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1322};
1323
1324static SOC_ENUM_SINGLE_DECL(
1325 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1326 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1327
1328static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1329 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1330
1331/* InBound8 Source */ /* MX-A4 [10:8] */
1332static const char * const rt5677_inbound8_src[] = {
1333 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1334 "MONO ADC MIX L", "DACL1 FS"
1335};
1336
1337static SOC_ENUM_SINGLE_DECL(
1338 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1339 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1340
1341static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1342 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1343
1344/* InBound9 Source */ /* MX-A4 [6:4] */
1345static const char * const rt5677_inbound9_src[] = {
1346 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1347 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1348};
1349
1350static SOC_ENUM_SINGLE_DECL(
1351 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1352 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1353
1354static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1355 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1356
1357/* VAD Source */ /* MX-9F [6:4] */
1358static const char * const rt5677_vad_src[] = {
1359 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1360 "STO3 ADC MIX L"
1361};
1362
1363static SOC_ENUM_SINGLE_DECL(
1364 rt5677_vad_enum, RT5677_VAD_CTRL4,
1365 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1366
1367static const struct snd_kcontrol_new rt5677_vad_src_mux =
1368 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1369
1370/* Sidetone Source */ /* MX-13 [11:9] */
1371static const char * const rt5677_sidetone_src[] = {
1372 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1373};
1374
1375static SOC_ENUM_SINGLE_DECL(
1376 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1377 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1378
1379static const struct snd_kcontrol_new rt5677_sidetone_mux =
1380 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1381
1382/* DAC1/2 Source */ /* MX-15 [1:0] */
1383static const char * const rt5677_dac12_src[] = {
1384 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1385};
1386
1387static SOC_ENUM_SINGLE_DECL(
1388 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1389 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1390
1391static const struct snd_kcontrol_new rt5677_dac12_mux =
1392 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1393
1394/* DAC3 Source */ /* MX-15 [5:4] */
1395static const char * const rt5677_dac3_src[] = {
1396 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1397};
1398
1399static SOC_ENUM_SINGLE_DECL(
1400 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1401 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1402
1403static const struct snd_kcontrol_new rt5677_dac3_mux =
1404 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1405
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1406/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1407static const char * const rt5677_pdm_src[] = {
1408 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1409};
1410
1411static SOC_ENUM_SINGLE_DECL(
1412 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1413 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1414
1415static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1416 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1417
1418static SOC_ENUM_SINGLE_DECL(
1419 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1420 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1421
1422static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1423 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1424
1425static SOC_ENUM_SINGLE_DECL(
1426 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1427 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1428
1429static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1430 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1431
1432static SOC_ENUM_SINGLE_DECL(
1433 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1434 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1435
1436static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1437 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1438
1439/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0]*/
1440static const char * const rt5677_if12_adc1_src[] = {
1441 "STO1 ADC MIX", "OB01", "VAD ADC"
1442};
1443
1444static SOC_ENUM_SINGLE_DECL(
1445 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1446 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1447
1448static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1449 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1450
1451static SOC_ENUM_SINGLE_DECL(
1452 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1453 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1454
1455static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1456 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1457
1458static SOC_ENUM_SINGLE_DECL(
1459 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1460 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1461
1462static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1463 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1464
1465/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1466static const char * const rt5677_if12_adc2_src[] = {
1467 "STO2 ADC MIX", "OB23"
1468};
1469
1470static SOC_ENUM_SINGLE_DECL(
1471 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1472 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1473
1474static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1475 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1476
1477static SOC_ENUM_SINGLE_DECL(
1478 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1479 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1480
1481static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1482 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1483
1484static SOC_ENUM_SINGLE_DECL(
1485 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1486 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1487
1488static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1489 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1490
1491/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1492static const char * const rt5677_if12_adc3_src[] = {
1493 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1494};
1495
1496static SOC_ENUM_SINGLE_DECL(
1497 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1498 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1499
1500static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1501 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1502
1503static SOC_ENUM_SINGLE_DECL(
1504 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1505 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1506
1507static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1508 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1509
1510static SOC_ENUM_SINGLE_DECL(
1511 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1512 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1513
1514static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1515 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1516
1517/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1518static const char * const rt5677_if12_adc4_src[] = {
1519 "STO4 ADC MIX", "OB67", "OB01"
1520};
1521
1522static SOC_ENUM_SINGLE_DECL(
1523 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1524 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1525
1526static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1527 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1528
1529static SOC_ENUM_SINGLE_DECL(
1530 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1531 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1532
1533static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1534 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1535
1536static SOC_ENUM_SINGLE_DECL(
1537 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1538 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1539
1540static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1541 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1542
1543/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4]*/
1544static const char * const rt5677_if34_adc_src[] = {
1545 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1546 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1547};
1548
1549static SOC_ENUM_SINGLE_DECL(
1550 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1551 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1552
1553static const struct snd_kcontrol_new rt5677_if3_adc_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1554 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1555
1556static SOC_ENUM_SINGLE_DECL(
1557 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1558 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1559
1560static const struct snd_kcontrol_new rt5677_if4_adc_mux =
Oder Chiou1b7fd762014-06-10 14:35:24 +0800[diff] [blame]1561 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1562
1563static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
1564 struct snd_kcontrol *kcontrol, int event)
1565{
1566 struct snd_soc_codec *codec = w->codec;
1567 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1568
1569 switch (event) {
1570 case SND_SOC_DAPM_POST_PMU:
1571 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1572 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
1573 break;
1574
1575 case SND_SOC_DAPM_PRE_PMD:
1576 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1577 RT5677_PWR_BST1_P, 0);
1578 break;
1579
1580 default:
1581 return 0;
1582 }
1583
1584 return 0;
1585}
1586
1587static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
1588 struct snd_kcontrol *kcontrol, int event)
1589{
1590 struct snd_soc_codec *codec = w->codec;
1591 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1592
1593 switch (event) {
1594 case SND_SOC_DAPM_POST_PMU:
1595 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1596 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
1597 break;
1598
1599 case SND_SOC_DAPM_PRE_PMD:
1600 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1601 RT5677_PWR_BST2_P, 0);
1602 break;
1603
1604 default:
1605 return 0;
1606 }
1607
1608 return 0;
1609}
1610
1611static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
1612 struct snd_kcontrol *kcontrol, int event)
1613{
1614 struct snd_soc_codec *codec = w->codec;
1615 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1616
1617 switch (event) {
1618 case SND_SOC_DAPM_POST_PMU:
1619 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
1620 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
1621 break;
1622 default:
1623 return 0;
1624 }
1625
1626 return 0;
1627}
1628
1629static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
1630 struct snd_kcontrol *kcontrol, int event)
1631{
1632 struct snd_soc_codec *codec = w->codec;
1633 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1634
1635 switch (event) {
1636 case SND_SOC_DAPM_POST_PMU:
1637 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
1638 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
1639 break;
1640 default:
1641 return 0;
1642 }
1643
1644 return 0;
1645}
1646
1647static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
1648 struct snd_kcontrol *kcontrol, int event)
1649{
1650 struct snd_soc_codec *codec = w->codec;
1651 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1652
1653 switch (event) {
1654 case SND_SOC_DAPM_POST_PMU:
1655 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1656 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
1657 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
1658 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
1659 break;
Oder Chiouf58c3b92014-06-10 14:35:26 +0800[diff] [blame]1660
1661 case SND_SOC_DAPM_PRE_PMD:
1662 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1663 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
1664 RT5677_PWR_CLK_MB, 0);
1665 break;
1666
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1667 default:
1668 return 0;
1669 }
1670
1671 return 0;
1672}
1673
1674static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
1675 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
1676 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
1677 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
1678 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
1679
1680 /* Input Side */
1681 /* micbias */
Oder Chiou3d0c03d2014-06-10 14:35:23 +0800[diff] [blame]1682 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
Oder Chiouf58c3b92014-06-10 14:35:26 +0800[diff] [blame]1683 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
1684 SND_SOC_DAPM_POST_PMU),
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1685
1686 /* Input Lines */
1687 SND_SOC_DAPM_INPUT("DMIC L1"),
1688 SND_SOC_DAPM_INPUT("DMIC R1"),
1689 SND_SOC_DAPM_INPUT("DMIC L2"),
1690 SND_SOC_DAPM_INPUT("DMIC R2"),
1691 SND_SOC_DAPM_INPUT("DMIC L3"),
1692 SND_SOC_DAPM_INPUT("DMIC R3"),
1693 SND_SOC_DAPM_INPUT("DMIC L4"),
1694 SND_SOC_DAPM_INPUT("DMIC R4"),
1695
1696 SND_SOC_DAPM_INPUT("IN1P"),
1697 SND_SOC_DAPM_INPUT("IN1N"),
1698 SND_SOC_DAPM_INPUT("IN2P"),
1699 SND_SOC_DAPM_INPUT("IN2N"),
1700
1701 SND_SOC_DAPM_INPUT("Haptic Generator"),
1702
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]1703 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1704 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1705 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1706 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1707
1708 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
1709 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
1710 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
1711 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
1712 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
1713 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
1714 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
1715 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]1716
1717 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1718 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1719
1720 /* Boost */
1721 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
1722 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
1723 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1724 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
1725 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
1726 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1727
1728 /* ADCs */
1729 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
1730 0, 0),
1731 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
1732 0, 0),
1733 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
1734
1735 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
1736 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
1737 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
1738 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
1739 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
1740 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
1741 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
1742 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
1743
1744 /* ADC Mux */
1745 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1746 &rt5677_sto1_dmic_mux),
1747 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1748 &rt5677_sto1_adc1_mux),
1749 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1750 &rt5677_sto1_adc2_mux),
1751 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
1752 &rt5677_sto2_dmic_mux),
1753 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1754 &rt5677_sto2_adc1_mux),
1755 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1756 &rt5677_sto2_adc2_mux),
1757 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
1758 &rt5677_sto2_adc_lr_mux),
1759 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
1760 &rt5677_sto3_dmic_mux),
1761 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1762 &rt5677_sto3_adc1_mux),
1763 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1764 &rt5677_sto3_adc2_mux),
1765 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
1766 &rt5677_sto4_dmic_mux),
1767 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1768 &rt5677_sto4_adc1_mux),
1769 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1770 &rt5677_sto4_adc2_mux),
1771 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1772 &rt5677_mono_dmic_l_mux),
1773 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1774 &rt5677_mono_dmic_r_mux),
1775 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
1776 &rt5677_mono_adc2_l_mux),
1777 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
1778 &rt5677_mono_adc1_l_mux),
1779 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
1780 &rt5677_mono_adc1_r_mux),
1781 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
1782 &rt5677_mono_adc2_r_mux),
1783
1784 /* ADC Mixer */
1785 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
1786 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
1787 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
1788 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
1789 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
1790 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
1791 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
1792 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
1793 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1794 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
1795 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1796 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
1797 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1798 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
1799 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1800 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
1801 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
1802 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
1803 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
1804 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
1805 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
1806 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
1807 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
1808 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
1809 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
1810 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1811 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1812 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
1813 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
1814 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1815 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1816 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
1817
1818 /* ADC PGA */
1819 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1820 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1821 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1822 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1823 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1824 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1825 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1826 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1827 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1828 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1829 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1830 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1831 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1832 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1833 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1834 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1835 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1836 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1837
1838 /* DSP */
1839 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
1840 &rt5677_ib9_src_mux),
1841 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
1842 &rt5677_ib8_src_mux),
1843 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
1844 &rt5677_ib7_src_mux),
1845 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
1846 &rt5677_ib6_src_mux),
1847 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
1848 &rt5677_ib45_src_mux),
1849 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
1850 &rt5677_ib23_src_mux),
1851 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
1852 &rt5677_ib01_src_mux),
1853 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
1854 &rt5677_ib45_bypass_src_mux),
1855 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
1856 &rt5677_ib23_bypass_src_mux),
1857 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
1858 &rt5677_ib01_bypass_src_mux),
1859 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
1860 &rt5677_ob23_bypass_src_mux),
1861 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
1862 &rt5677_ob01_bypass_src_mux),
1863
1864 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
1865 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
1866
1867 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
1868 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
1869 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
1870 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
1871 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
1872 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
1873
1874 /* Digital Interface */
1875 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
1876 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
1877 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1878 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1879 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1880 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1881 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1882 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1883 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1884 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1885 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1886 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1887 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1888 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1889 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1890 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1891 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1892 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1893
1894 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
1895 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
1896 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1897 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1898 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1899 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1900 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1901 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1902 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1903 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1904 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1905 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1906 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1907 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1908 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1909 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1910 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1911 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1912
1913 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
1914 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
1915 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1916 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1917 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1918 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1919 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1920 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1921
1922 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
1923 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
1924 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1925 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1926 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1927 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1928 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1929 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1930
1931 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
1932 RT5677_PWR_SLB_BIT, 0, NULL, 0),
1933 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1934 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1935 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1936 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1937 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1938 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1939 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1940 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1941 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1942 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1943 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1944 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1945 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1946 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1947 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1948 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1949
1950 /* Digital Interface Select */
1951 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1952 &rt5677_if1_adc1_mux),
1953 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1954 &rt5677_if1_adc2_mux),
1955 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
1956 &rt5677_if1_adc3_mux),
1957 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1958 &rt5677_if1_adc4_mux),
1959 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1960 &rt5677_if2_adc1_mux),
1961 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1962 &rt5677_if2_adc2_mux),
1963 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
1964 &rt5677_if2_adc3_mux),
1965 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1966 &rt5677_if2_adc4_mux),
1967 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
1968 &rt5677_if3_adc_mux),
1969 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
1970 &rt5677_if4_adc_mux),
1971 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
1972 &rt5677_slb_adc1_mux),
1973 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
1974 &rt5677_slb_adc2_mux),
1975 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
1976 &rt5677_slb_adc3_mux),
1977 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
1978 &rt5677_slb_adc4_mux),
1979
1980 /* Audio Interface */
1981 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1982 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1983 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1984 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1985 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1986 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1987 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
1988 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
1989 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
1990 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
1991
1992 /* Sidetone Mux */
1993 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
1994 &rt5677_sidetone_mux),
1995 /* VAD Mux*/
1996 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
1997 &rt5677_vad_src_mux),
1998
1999 /* Tensilica DSP */
2000 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2001 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2002 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2003 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2004 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2005 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2006 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2007 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2008 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2009 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2010 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2011 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2012 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2013
2014 /* Output Side */
2015 /* DAC mixer before sound effect */
2016 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2017 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2018 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2019 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2020 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2021
2022 /* DAC Mux */
2023 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2024 &rt5677_dac1_mux),
2025 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2026 &rt5677_adda1_mux),
2027 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2028 &rt5677_dac12_mux),
2029 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2030 &rt5677_dac3_mux),
2031
2032 /* DAC2 channel Mux */
2033 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2034 &rt5677_dac2_l_mux),
2035 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2036 &rt5677_dac2_r_mux),
2037
2038 /* DAC3 channel Mux */
2039 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2040 &rt5677_dac3_l_mux),
2041 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2042 &rt5677_dac3_r_mux),
2043
2044 /* DAC4 channel Mux */
2045 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2046 &rt5677_dac4_l_mux),
2047 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2048 &rt5677_dac4_r_mux),
2049
2050 /* DAC Mixer */
2051 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2052 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2053 SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2,
2054 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2055 SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2,
2056 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2057
2058 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2059 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2060 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2061 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2062 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2063 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2064 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2065 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2066 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2067 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2068 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2069 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2070 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2071 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2072 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2073 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2074 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2075 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2076 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2077 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2078
2079 /* DACs */
2080 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2081 RT5677_PWR_DAC1_BIT, 0),
2082 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2083 RT5677_PWR_DAC2_BIT, 0),
2084 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2085 RT5677_PWR_DAC3_BIT, 0),
2086
2087 /* PDM */
2088 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2089 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2090 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2091 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2092
2093 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2094 1, &rt5677_pdm1_l_mux),
2095 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2096 1, &rt5677_pdm1_r_mux),
2097 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2098 1, &rt5677_pdm2_l_mux),
2099 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2100 1, &rt5677_pdm2_r_mux),
2101
2102 SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2103 0, NULL, 0),
2104 SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2105 0, NULL, 0),
2106 SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2107 0, NULL, 0),
2108
2109 /* Output Lines */
2110 SND_SOC_DAPM_OUTPUT("LOUT1"),
2111 SND_SOC_DAPM_OUTPUT("LOUT2"),
2112 SND_SOC_DAPM_OUTPUT("LOUT3"),
2113 SND_SOC_DAPM_OUTPUT("PDM1L"),
2114 SND_SOC_DAPM_OUTPUT("PDM1R"),
2115 SND_SOC_DAPM_OUTPUT("PDM2L"),
2116 SND_SOC_DAPM_OUTPUT("PDM2R"),
2117};
2118
2119static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2120 { "DMIC1", NULL, "DMIC L1" },
2121 { "DMIC1", NULL, "DMIC R1" },
2122 { "DMIC2", NULL, "DMIC L2" },
2123 { "DMIC2", NULL, "DMIC R2" },
2124 { "DMIC3", NULL, "DMIC L3" },
2125 { "DMIC3", NULL, "DMIC R3" },
2126 { "DMIC4", NULL, "DMIC L4" },
2127 { "DMIC4", NULL, "DMIC R4" },
2128
2129 { "DMIC L1", NULL, "DMIC CLK" },
2130 { "DMIC R1", NULL, "DMIC CLK" },
2131 { "DMIC L2", NULL, "DMIC CLK" },
2132 { "DMIC R2", NULL, "DMIC CLK" },
2133 { "DMIC L3", NULL, "DMIC CLK" },
2134 { "DMIC R3", NULL, "DMIC CLK" },
2135 { "DMIC L4", NULL, "DMIC CLK" },
2136 { "DMIC R4", NULL, "DMIC CLK" },
2137
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]2138 { "DMIC L1", NULL, "DMIC1 power" },
2139 { "DMIC R1", NULL, "DMIC1 power" },
2140 { "DMIC L3", NULL, "DMIC3 power" },
2141 { "DMIC R3", NULL, "DMIC3 power" },
2142 { "DMIC L4", NULL, "DMIC4 power" },
2143 { "DMIC R4", NULL, "DMIC4 power" },
2144
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2145 { "BST1", NULL, "IN1P" },
2146 { "BST1", NULL, "IN1N" },
2147 { "BST2", NULL, "IN2P" },
2148 { "BST2", NULL, "IN2N" },
2149
2150 { "IN1P", NULL, "micbias1" },
2151 { "IN1N", NULL, "micbias1" },
2152 { "IN2P", NULL, "micbias1" },
2153 { "IN2N", NULL, "micbias1" },
2154
2155 { "ADC 1", NULL, "BST1" },
2156 { "ADC 1", NULL, "ADC 1 power" },
2157 { "ADC 1", NULL, "ADC1 clock" },
2158 { "ADC 2", NULL, "BST2" },
2159 { "ADC 2", NULL, "ADC 2 power" },
2160 { "ADC 2", NULL, "ADC2 clock" },
2161
2162 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2163 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2164 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2165 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2166
2167 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2168 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2169 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2170 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2171
2172 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2173 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2174 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2175 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2176
2177 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2178 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2179 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2180 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2181
2182 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2183 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2184 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2185 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2186
2187 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2188 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2189 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2190 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2191
2192 { "ADC 1_2", NULL, "ADC 1" },
2193 { "ADC 1_2", NULL, "ADC 2" },
2194
2195 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2196 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2197 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2198
2199 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2200 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2201 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2202
2203 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2204 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2205 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2206
2207 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2208 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2209 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2210
2211 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2212 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2213 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2214
2215 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2216 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2217 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2218
2219 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2220 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2221 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
2222
2223 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2224 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2225 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
2226
2227 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
2228 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
2229 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2230
2231 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
2232 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
2233 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2234
2235 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
2236 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
2237 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2238
2239 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
2240 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
2241 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2242
2243 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2244 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2245 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2246 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2247
2248 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2249 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2250 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2251
2252 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2253 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2254 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2255
2256 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
2257 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
2258
2259 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2260 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2261 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2262 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2263
2264 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
2265 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
2266
2267 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
2268 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
2269
2270 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
2271 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
2272 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2273
2274 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
2275 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
2276 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2277
2278 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
2279 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
2280
2281 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2282 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2283 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2284 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2285
2286 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
2287 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
2288 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2289
2290 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
2291 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
2292 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2293
2294 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
2295 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
2296
2297 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2298 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2299 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2300 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2301
2302 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
2303 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
2304 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2305
2306 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
2307 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
2308 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2309
2310 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
2311 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
2312
2313 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
2314 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
2315 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2316 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2317
2318 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
2319 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
2320 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2321 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2322
2323 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
2324 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
2325
2326 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2327 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2328 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2329 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2330 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2331
2332 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2333 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2334 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2335
2336 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2337 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2338
2339 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2340 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2341 { "IF1 ADC3 Mux", "OB45", "OB45" },
2342
2343 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2344 { "IF1 ADC4 Mux", "OB67", "OB67" },
2345 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2346
2347 { "AIF1TX", NULL, "I2S1" },
2348 { "AIF1TX", NULL, "IF1 ADC1 Mux" },
2349 { "AIF1TX", NULL, "IF1 ADC2 Mux" },
2350 { "AIF1TX", NULL, "IF1 ADC3 Mux" },
2351 { "AIF1TX", NULL, "IF1 ADC4 Mux" },
2352
2353 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2354 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2355 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2356
2357 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2358 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2359
2360 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2361 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2362 { "IF2 ADC3 Mux", "OB45", "OB45" },
2363
2364 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2365 { "IF2 ADC4 Mux", "OB67", "OB67" },
2366 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2367
2368 { "AIF2TX", NULL, "I2S2" },
2369 { "AIF2TX", NULL, "IF2 ADC1 Mux" },
2370 { "AIF2TX", NULL, "IF2 ADC2 Mux" },
2371 { "AIF2TX", NULL, "IF2 ADC3 Mux" },
2372 { "AIF2TX", NULL, "IF2 ADC4 Mux" },
2373
2374 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2375 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2376 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2377 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2378 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2379 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
2380 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
2381 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2382
2383 { "AIF3TX", NULL, "I2S3" },
2384 { "AIF3TX", NULL, "IF3 ADC Mux" },
2385
2386 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2387 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2388 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2389 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2390 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2391 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
2392 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
2393 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2394
2395 { "AIF4TX", NULL, "I2S4" },
2396 { "AIF4TX", NULL, "IF4 ADC Mux" },
2397
2398 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2399 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2400 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2401
2402 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2403 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2404
2405 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2406 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2407 { "SLB ADC3 Mux", "OB45", "OB45" },
2408
2409 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2410 { "SLB ADC4 Mux", "OB67", "OB67" },
2411 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2412
2413 { "SLBTX", NULL, "SLB" },
2414 { "SLBTX", NULL, "SLB ADC1 Mux" },
2415 { "SLBTX", NULL, "SLB ADC2 Mux" },
2416 { "SLBTX", NULL, "SLB ADC3 Mux" },
2417 { "SLBTX", NULL, "SLB ADC4 Mux" },
2418
2419 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
2420 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
2421 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
2422 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2423 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
2424
2425 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
2426 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
2427
2428 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
2429 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
2430 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
2431 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2432 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
2433 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
2434
2435 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
2436 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
2437
2438 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
2439 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
2440 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
2441 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2442 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
2443
2444 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
2445 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
2446
2447 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
2448 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
2449 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
2450 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2451 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
2452 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2453 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2454 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2455
2456 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
2457 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
2458 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
2459 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2460 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
2461 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2462 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2463 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2464
2465 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2466 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2467 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2468 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2469 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2470 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
2471
2472 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2473 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2474 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2475 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2476 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2477 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
2478 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
2479
2480 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2481 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2482 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2483 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
2484 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
2485 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
2486 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
2487
2488 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2489 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2490 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2491 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
2492 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
2493 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
2494 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
2495
2496 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2497 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2498 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2499 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
2500 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
2501 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
2502 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
2503
2504 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2505 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2506 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2507 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
2508 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
2509 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
2510 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
2511
2512 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2513 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2514 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2515 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
2516 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
2517 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
2518 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
2519
2520 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2521 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2522 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2523 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
2524 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
2525 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
2526 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
2527
2528 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
2529 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
2530 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
2531 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
2532
2533 { "OutBound2", NULL, "OB23 Bypass Mux" },
2534 { "OutBound3", NULL, "OB23 Bypass Mux" },
2535 { "OutBound4", NULL, "OB4 MIX" },
2536 { "OutBound5", NULL, "OB5 MIX" },
2537 { "OutBound6", NULL, "OB6 MIX" },
2538 { "OutBound7", NULL, "OB7 MIX" },
2539
2540 { "OB45", NULL, "OutBound4" },
2541 { "OB45", NULL, "OutBound5" },
2542 { "OB67", NULL, "OutBound6" },
2543 { "OB67", NULL, "OutBound7" },
2544
2545 { "IF1 DAC0", NULL, "AIF1RX" },
2546 { "IF1 DAC1", NULL, "AIF1RX" },
2547 { "IF1 DAC2", NULL, "AIF1RX" },
2548 { "IF1 DAC3", NULL, "AIF1RX" },
2549 { "IF1 DAC4", NULL, "AIF1RX" },
2550 { "IF1 DAC5", NULL, "AIF1RX" },
2551 { "IF1 DAC6", NULL, "AIF1RX" },
2552 { "IF1 DAC7", NULL, "AIF1RX" },
2553 { "IF1 DAC0", NULL, "I2S1" },
2554 { "IF1 DAC1", NULL, "I2S1" },
2555 { "IF1 DAC2", NULL, "I2S1" },
2556 { "IF1 DAC3", NULL, "I2S1" },
2557 { "IF1 DAC4", NULL, "I2S1" },
2558 { "IF1 DAC5", NULL, "I2S1" },
2559 { "IF1 DAC6", NULL, "I2S1" },
2560 { "IF1 DAC7", NULL, "I2S1" },
2561
2562 { "IF1 DAC01", NULL, "IF1 DAC0" },
2563 { "IF1 DAC01", NULL, "IF1 DAC1" },
2564 { "IF1 DAC23", NULL, "IF1 DAC2" },
2565 { "IF1 DAC23", NULL, "IF1 DAC3" },
2566 { "IF1 DAC45", NULL, "IF1 DAC4" },
2567 { "IF1 DAC45", NULL, "IF1 DAC5" },
2568 { "IF1 DAC67", NULL, "IF1 DAC6" },
2569 { "IF1 DAC67", NULL, "IF1 DAC7" },
2570
2571 { "IF2 DAC0", NULL, "AIF2RX" },
2572 { "IF2 DAC1", NULL, "AIF2RX" },
2573 { "IF2 DAC2", NULL, "AIF2RX" },
2574 { "IF2 DAC3", NULL, "AIF2RX" },
2575 { "IF2 DAC4", NULL, "AIF2RX" },
2576 { "IF2 DAC5", NULL, "AIF2RX" },
2577 { "IF2 DAC6", NULL, "AIF2RX" },
2578 { "IF2 DAC7", NULL, "AIF2RX" },
2579 { "IF2 DAC0", NULL, "I2S2" },
2580 { "IF2 DAC1", NULL, "I2S2" },
2581 { "IF2 DAC2", NULL, "I2S2" },
2582 { "IF2 DAC3", NULL, "I2S2" },
2583 { "IF2 DAC4", NULL, "I2S2" },
2584 { "IF2 DAC5", NULL, "I2S2" },
2585 { "IF2 DAC6", NULL, "I2S2" },
2586 { "IF2 DAC7", NULL, "I2S2" },
2587
2588 { "IF2 DAC01", NULL, "IF2 DAC0" },
2589 { "IF2 DAC01", NULL, "IF2 DAC1" },
2590 { "IF2 DAC23", NULL, "IF2 DAC2" },
2591 { "IF2 DAC23", NULL, "IF2 DAC3" },
2592 { "IF2 DAC45", NULL, "IF2 DAC4" },
2593 { "IF2 DAC45", NULL, "IF2 DAC5" },
2594 { "IF2 DAC67", NULL, "IF2 DAC6" },
2595 { "IF2 DAC67", NULL, "IF2 DAC7" },
2596
2597 { "IF3 DAC", NULL, "AIF3RX" },
2598 { "IF3 DAC", NULL, "I2S3" },
2599
2600 { "IF4 DAC", NULL, "AIF4RX" },
2601 { "IF4 DAC", NULL, "I2S4" },
2602
2603 { "IF3 DAC L", NULL, "IF3 DAC" },
2604 { "IF3 DAC R", NULL, "IF3 DAC" },
2605
2606 { "IF4 DAC L", NULL, "IF4 DAC" },
2607 { "IF4 DAC R", NULL, "IF4 DAC" },
2608
2609 { "SLB DAC0", NULL, "SLBRX" },
2610 { "SLB DAC1", NULL, "SLBRX" },
2611 { "SLB DAC2", NULL, "SLBRX" },
2612 { "SLB DAC3", NULL, "SLBRX" },
2613 { "SLB DAC4", NULL, "SLBRX" },
2614 { "SLB DAC5", NULL, "SLBRX" },
2615 { "SLB DAC6", NULL, "SLBRX" },
2616 { "SLB DAC7", NULL, "SLBRX" },
2617 { "SLB DAC0", NULL, "SLB" },
2618 { "SLB DAC1", NULL, "SLB" },
2619 { "SLB DAC2", NULL, "SLB" },
2620 { "SLB DAC3", NULL, "SLB" },
2621 { "SLB DAC4", NULL, "SLB" },
2622 { "SLB DAC5", NULL, "SLB" },
2623 { "SLB DAC6", NULL, "SLB" },
2624 { "SLB DAC7", NULL, "SLB" },
2625
2626 { "SLB DAC01", NULL, "SLB DAC0" },
2627 { "SLB DAC01", NULL, "SLB DAC1" },
2628 { "SLB DAC23", NULL, "SLB DAC2" },
2629 { "SLB DAC23", NULL, "SLB DAC3" },
2630 { "SLB DAC45", NULL, "SLB DAC4" },
2631 { "SLB DAC45", NULL, "SLB DAC5" },
2632 { "SLB DAC67", NULL, "SLB DAC6" },
2633 { "SLB DAC67", NULL, "SLB DAC7" },
2634
2635 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2636 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2637 { "ADDA1 Mux", "OB 67", "OB67" },
2638
2639 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
2640 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
2641 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
2642 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
2643 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
2644 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
2645
2646 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
2647 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
2648 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2649 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
2650 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
2651 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2652
2653 { "DAC1 FS", NULL, "DAC1 MIXL" },
2654 { "DAC1 FS", NULL, "DAC1 MIXR" },
2655
2656 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
2657 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
2658 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
2659 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
2660 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
2661 { "DAC2 L Mux", "OB 2", "OutBound2" },
2662
2663 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
2664 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
2665 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
2666 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
2667 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
2668 { "DAC2 R Mux", "OB 3", "OutBound3" },
2669 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
2670 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
2671
2672 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
2673 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
2674 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
2675 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
2676 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
2677 { "DAC3 L Mux", "OB 4", "OutBound4" },
2678
2679 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
2680 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
2681 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
2682 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
2683 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
2684 { "DAC3 R Mux", "OB 5", "OutBound5" },
2685
2686 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
2687 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
2688 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
2689 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
2690 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
2691 { "DAC4 L Mux", "OB 6", "OutBound6" },
2692
2693 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
2694 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
2695 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
2696 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
2697 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
2698 { "DAC4 R Mux", "OB 7", "OutBound7" },
2699
2700 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
2701 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
2702 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
2703 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
2704 { "Sidetone Mux", "ADC1", "ADC 1" },
2705 { "Sidetone Mux", "ADC2", "ADC 2" },
2706
2707 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
2708 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2709 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2710 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
2711 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2712 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
2713 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2714 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2715 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
2716 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2717
2718 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
2719 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2720 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2721 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
2722 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2723 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
2724 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2725 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2726 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
2727 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2728
2729 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2730 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
2731 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
2732 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
2733 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2734 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
2735 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
2736 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
2737
2738 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2739 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
2740 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
2741 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
2742 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2743 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
2744 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
2745 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
2746
2747 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
2748 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
2749 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
2750 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
2751 { "DD1 MIX", NULL, "DD1 MIXL" },
2752 { "DD1 MIX", NULL, "DD1 MIXR" },
2753 { "DD2 MIX", NULL, "DD2 MIXL" },
2754 { "DD2 MIX", NULL, "DD2 MIXR" },
2755
2756 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
2757 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
2758 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
2759 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
2760
2761 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2762 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2763 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
2764 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
2765
2766 { "DAC 1", NULL, "DAC12 SRC Mux" },
2767 { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll },
2768 { "DAC 2", NULL, "DAC12 SRC Mux" },
2769 { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll },
2770 { "DAC 3", NULL, "DAC3 SRC Mux" },
2771 { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll },
2772
2773 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
2774 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
2775 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
2776 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
2777 { "PDM1 L Mux", NULL, "PDM1 Power" },
2778 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
2779 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
2780 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
2781 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
2782 { "PDM1 R Mux", NULL, "PDM1 Power" },
2783 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
2784 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
2785 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
2786 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
2787 { "PDM2 L Mux", NULL, "PDM2 Power" },
2788 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
2789 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
2790 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
2791 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
2792 { "PDM2 R Mux", NULL, "PDM2 Power" },
2793
2794 { "LOUT1 amp", NULL, "DAC 1" },
2795 { "LOUT2 amp", NULL, "DAC 2" },
2796 { "LOUT3 amp", NULL, "DAC 3" },
2797
2798 { "LOUT1", NULL, "LOUT1 amp" },
2799 { "LOUT2", NULL, "LOUT2 amp" },
2800 { "LOUT3", NULL, "LOUT3 amp" },
2801
2802 { "PDM1L", NULL, "PDM1 L Mux" },
2803 { "PDM1R", NULL, "PDM1 R Mux" },
2804 { "PDM2L", NULL, "PDM2 L Mux" },
2805 { "PDM2R", NULL, "PDM2 R Mux" },
2806};
2807
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]2808static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
2809 { "DMIC L2", NULL, "DMIC1 power" },
2810 { "DMIC R2", NULL, "DMIC1 power" },
2811};
2812
2813static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
2814 { "DMIC L2", NULL, "DMIC2 power" },
2815 { "DMIC R2", NULL, "DMIC2 power" },
2816};
2817
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2818static int rt5677_hw_params(struct snd_pcm_substream *substream,
2819 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2820{
2821 struct snd_soc_codec *codec = dai->codec;
2822 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2823 unsigned int val_len = 0, val_clk, mask_clk;
2824 int pre_div, bclk_ms, frame_size;
2825
2826 rt5677->lrck[dai->id] = params_rate(params);
Axel Lin30f14b42014-06-10 08:57:36 +0800[diff] [blame]2827 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]2828 if (pre_div < 0) {
2829 dev_err(codec->dev, "Unsupported clock setting\n");
2830 return -EINVAL;
2831 }
2832 frame_size = snd_soc_params_to_frame_size(params);
2833 if (frame_size < 0) {
2834 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2835 return -EINVAL;
2836 }
2837 bclk_ms = frame_size > 32;
2838 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
2839
2840 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2841 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
2842 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2843 bclk_ms, pre_div, dai->id);
2844
2845 switch (params_width(params)) {
2846 case 16:
2847 break;
2848 case 20:
2849 val_len |= RT5677_I2S_DL_20;
2850 break;
2851 case 24:
2852 val_len |= RT5677_I2S_DL_24;
2853 break;
2854 case 8:
2855 val_len |= RT5677_I2S_DL_8;
2856 break;
2857 default:
2858 return -EINVAL;
2859 }
2860
2861 switch (dai->id) {
2862 case RT5677_AIF1:
2863 mask_clk = RT5677_I2S_PD1_MASK;
2864 val_clk = pre_div << RT5677_I2S_PD1_SFT;
2865 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
2866 RT5677_I2S_DL_MASK, val_len);
2867 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2868 mask_clk, val_clk);
2869 break;
2870 case RT5677_AIF2:
2871 mask_clk = RT5677_I2S_PD2_MASK;
2872 val_clk = pre_div << RT5677_I2S_PD2_SFT;
2873 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
2874 RT5677_I2S_DL_MASK, val_len);
2875 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2876 mask_clk, val_clk);
2877 break;
2878 case RT5677_AIF3:
2879 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
2880 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
2881 pre_div << RT5677_I2S_PD3_SFT;
2882 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
2883 RT5677_I2S_DL_MASK, val_len);
2884 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2885 mask_clk, val_clk);
2886 break;
2887 case RT5677_AIF4:
2888 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
2889 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
2890 pre_div << RT5677_I2S_PD4_SFT;
2891 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
2892 RT5677_I2S_DL_MASK, val_len);
2893 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2894 mask_clk, val_clk);
2895 break;
2896 default:
2897 break;
2898 }
2899
2900 return 0;
2901}
2902
2903static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2904{
2905 struct snd_soc_codec *codec = dai->codec;
2906 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2907 unsigned int reg_val = 0;
2908
2909 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2910 case SND_SOC_DAIFMT_CBM_CFM:
2911 rt5677->master[dai->id] = 1;
2912 break;
2913 case SND_SOC_DAIFMT_CBS_CFS:
2914 reg_val |= RT5677_I2S_MS_S;
2915 rt5677->master[dai->id] = 0;
2916 break;
2917 default:
2918 return -EINVAL;
2919 }
2920
2921 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2922 case SND_SOC_DAIFMT_NB_NF:
2923 break;
2924 case SND_SOC_DAIFMT_IB_NF:
2925 reg_val |= RT5677_I2S_BP_INV;
2926 break;
2927 default:
2928 return -EINVAL;
2929 }
2930
2931 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2932 case SND_SOC_DAIFMT_I2S:
2933 break;
2934 case SND_SOC_DAIFMT_LEFT_J:
2935 reg_val |= RT5677_I2S_DF_LEFT;
2936 break;
2937 case SND_SOC_DAIFMT_DSP_A:
2938 reg_val |= RT5677_I2S_DF_PCM_A;
2939 break;
2940 case SND_SOC_DAIFMT_DSP_B:
2941 reg_val |= RT5677_I2S_DF_PCM_B;
2942 break;
2943 default:
2944 return -EINVAL;
2945 }
2946
2947 switch (dai->id) {
2948 case RT5677_AIF1:
2949 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
2950 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2951 RT5677_I2S_DF_MASK, reg_val);
2952 break;
2953 case RT5677_AIF2:
2954 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
2955 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2956 RT5677_I2S_DF_MASK, reg_val);
2957 break;
2958 case RT5677_AIF3:
2959 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
2960 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2961 RT5677_I2S_DF_MASK, reg_val);
2962 break;
2963 case RT5677_AIF4:
2964 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
2965 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2966 RT5677_I2S_DF_MASK, reg_val);
2967 break;
2968 default:
2969 break;
2970 }
2971
2972
2973 return 0;
2974}
2975
2976static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
2977 int clk_id, unsigned int freq, int dir)
2978{
2979 struct snd_soc_codec *codec = dai->codec;
2980 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2981 unsigned int reg_val = 0;
2982
2983 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
2984 return 0;
2985
2986 switch (clk_id) {
2987 case RT5677_SCLK_S_MCLK:
2988 reg_val |= RT5677_SCLK_SRC_MCLK;
2989 break;
2990 case RT5677_SCLK_S_PLL1:
2991 reg_val |= RT5677_SCLK_SRC_PLL1;
2992 break;
2993 case RT5677_SCLK_S_RCCLK:
2994 reg_val |= RT5677_SCLK_SRC_RCCLK;
2995 break;
2996 default:
2997 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2998 return -EINVAL;
2999 }
3000 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3001 RT5677_SCLK_SRC_MASK, reg_val);
3002 rt5677->sysclk = freq;
3003 rt5677->sysclk_src = clk_id;
3004
3005 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3006
3007 return 0;
3008}
3009
3010/**
3011 * rt5677_pll_calc - Calcualte PLL M/N/K code.
3012 * @freq_in: external clock provided to codec.
3013 * @freq_out: target clock which codec works on.
3014 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
3015 *
3016 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
3017 *
3018 * Returns 0 for success or negative error code.
3019 */
3020static int rt5677_pll_calc(const unsigned int freq_in,
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3021 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3022{
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3023 if (RT5677_PLL_INP_MIN > freq_in)
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3024 return -EINVAL;
3025
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3026 return rl6231_pll_calc(freq_in, freq_out, pll_code);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3027}
3028
3029static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3030 unsigned int freq_in, unsigned int freq_out)
3031{
3032 struct snd_soc_codec *codec = dai->codec;
3033 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3034 struct rl6231_pll_code pll_code;
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3035 int ret;
3036
3037 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
3038 freq_out == rt5677->pll_out)
3039 return 0;
3040
3041 if (!freq_in || !freq_out) {
3042 dev_dbg(codec->dev, "PLL disabled\n");
3043
3044 rt5677->pll_in = 0;
3045 rt5677->pll_out = 0;
3046 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3047 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
3048 return 0;
3049 }
3050
3051 switch (source) {
3052 case RT5677_PLL1_S_MCLK:
3053 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3054 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
3055 break;
3056 case RT5677_PLL1_S_BCLK1:
3057 case RT5677_PLL1_S_BCLK2:
3058 case RT5677_PLL1_S_BCLK3:
3059 case RT5677_PLL1_S_BCLK4:
3060 switch (dai->id) {
3061 case RT5677_AIF1:
3062 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3063 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
3064 break;
3065 case RT5677_AIF2:
3066 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3067 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
3068 break;
3069 case RT5677_AIF3:
3070 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3071 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
3072 break;
3073 case RT5677_AIF4:
3074 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3075 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
3076 break;
3077 default:
3078 break;
3079 }
3080 break;
3081 default:
3082 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3083 return -EINVAL;
3084 }
3085
3086 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
3087 if (ret < 0) {
3088 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3089 return ret;
3090 }
3091
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3092 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
3093 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
3094 pll_code.n_code, pll_code.k_code);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3095
3096 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
Axel Lin099d3342014-06-17 12:41:31 +0800[diff] [blame]3097 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3098 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
3099 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
3100 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
3101
3102 rt5677->pll_in = freq_in;
3103 rt5677->pll_out = freq_out;
3104 rt5677->pll_src = source;
3105
3106 return 0;
3107}
3108
3109static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3110 enum snd_soc_bias_level level)
3111{
3112 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3113
3114 switch (level) {
3115 case SND_SOC_BIAS_ON:
3116 break;
3117
3118 case SND_SOC_BIAS_PREPARE:
3119 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
3120 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3121 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
3122 0x0055);
3123 regmap_update_bits(rt5677->regmap,
3124 RT5677_PR_BASE + RT5677_BIAS_CUR4,
3125 0x0f00, 0x0f00);
3126 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3127 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3128 RT5677_PWR_BG | RT5677_PWR_VREF2,
3129 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3130 RT5677_PWR_BG | RT5677_PWR_VREF2);
3131 mdelay(20);
3132 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3133 RT5677_PWR_FV1 | RT5677_PWR_FV2,
3134 RT5677_PWR_FV1 | RT5677_PWR_FV2);
3135 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
3136 RT5677_PWR_CORE, RT5677_PWR_CORE);
3137 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
3138 0x1, 0x1);
3139 }
3140 break;
3141
3142 case SND_SOC_BIAS_STANDBY:
3143 break;
3144
3145 case SND_SOC_BIAS_OFF:
3146 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
3147 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
3148 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
Oder Chiouf18803a2014-07-07 15:37:00 +0800[diff] [blame]3149 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3150 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
3151 regmap_update_bits(rt5677->regmap,
3152 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
3153 break;
3154
3155 default:
3156 break;
3157 }
3158 codec->dapm.bias_level = level;
3159
3160 return 0;
3161}
3162
3163static int rt5677_probe(struct snd_soc_codec *codec)
3164{
3165 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3166
3167 rt5677->codec = codec;
3168
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]3169 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
3170 snd_soc_dapm_add_routes(&codec->dapm,
3171 rt5677_dmic2_clk_2,
3172 ARRAY_SIZE(rt5677_dmic2_clk_2));
3173 } else { /*use dmic1 clock by default*/
3174 snd_soc_dapm_add_routes(&codec->dapm,
3175 rt5677_dmic2_clk_1,
3176 ARRAY_SIZE(rt5677_dmic2_clk_1));
3177 }
3178
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3179 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
3180
3181 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
3182 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
3183
3184 return 0;
3185}
3186
3187static int rt5677_remove(struct snd_soc_codec *codec)
3188{
3189 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3190
3191 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3192
3193 return 0;
3194}
3195
3196#ifdef CONFIG_PM
3197static int rt5677_suspend(struct snd_soc_codec *codec)
3198{
3199 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3200
3201 regcache_cache_only(rt5677->regmap, true);
3202 regcache_mark_dirty(rt5677->regmap);
3203
3204 return 0;
3205}
3206
3207static int rt5677_resume(struct snd_soc_codec *codec)
3208{
3209 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3210
3211 regcache_cache_only(rt5677->regmap, false);
3212 regcache_sync(rt5677->regmap);
3213
3214 return 0;
3215}
3216#else
3217#define rt5677_suspend NULL
3218#define rt5677_resume NULL
3219#endif
3220
3221#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3222#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3223 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3224
3225static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
3226 .hw_params = rt5677_hw_params,
3227 .set_fmt = rt5677_set_dai_fmt,
3228 .set_sysclk = rt5677_set_dai_sysclk,
3229 .set_pll = rt5677_set_dai_pll,
3230};
3231
3232static struct snd_soc_dai_driver rt5677_dai[] = {
3233 {
3234 .name = "rt5677-aif1",
3235 .id = RT5677_AIF1,
3236 .playback = {
3237 .stream_name = "AIF1 Playback",
3238 .channels_min = 1,
3239 .channels_max = 2,
3240 .rates = RT5677_STEREO_RATES,
3241 .formats = RT5677_FORMATS,
3242 },
3243 .capture = {
3244 .stream_name = "AIF1 Capture",
3245 .channels_min = 1,
3246 .channels_max = 2,
3247 .rates = RT5677_STEREO_RATES,
3248 .formats = RT5677_FORMATS,
3249 },
3250 .ops = &rt5677_aif_dai_ops,
3251 },
3252 {
3253 .name = "rt5677-aif2",
3254 .id = RT5677_AIF2,
3255 .playback = {
3256 .stream_name = "AIF2 Playback",
3257 .channels_min = 1,
3258 .channels_max = 2,
3259 .rates = RT5677_STEREO_RATES,
3260 .formats = RT5677_FORMATS,
3261 },
3262 .capture = {
3263 .stream_name = "AIF2 Capture",
3264 .channels_min = 1,
3265 .channels_max = 2,
3266 .rates = RT5677_STEREO_RATES,
3267 .formats = RT5677_FORMATS,
3268 },
3269 .ops = &rt5677_aif_dai_ops,
3270 },
3271 {
3272 .name = "rt5677-aif3",
3273 .id = RT5677_AIF3,
3274 .playback = {
3275 .stream_name = "AIF3 Playback",
3276 .channels_min = 1,
3277 .channels_max = 2,
3278 .rates = RT5677_STEREO_RATES,
3279 .formats = RT5677_FORMATS,
3280 },
3281 .capture = {
3282 .stream_name = "AIF3 Capture",
3283 .channels_min = 1,
3284 .channels_max = 2,
3285 .rates = RT5677_STEREO_RATES,
3286 .formats = RT5677_FORMATS,
3287 },
3288 .ops = &rt5677_aif_dai_ops,
3289 },
3290 {
3291 .name = "rt5677-aif4",
3292 .id = RT5677_AIF4,
3293 .playback = {
3294 .stream_name = "AIF4 Playback",
3295 .channels_min = 1,
3296 .channels_max = 2,
3297 .rates = RT5677_STEREO_RATES,
3298 .formats = RT5677_FORMATS,
3299 },
3300 .capture = {
3301 .stream_name = "AIF4 Capture",
3302 .channels_min = 1,
3303 .channels_max = 2,
3304 .rates = RT5677_STEREO_RATES,
3305 .formats = RT5677_FORMATS,
3306 },
3307 .ops = &rt5677_aif_dai_ops,
3308 },
3309 {
3310 .name = "rt5677-slimbus",
3311 .id = RT5677_AIF5,
3312 .playback = {
3313 .stream_name = "SLIMBus Playback",
3314 .channels_min = 1,
3315 .channels_max = 2,
3316 .rates = RT5677_STEREO_RATES,
3317 .formats = RT5677_FORMATS,
3318 },
3319 .capture = {
3320 .stream_name = "SLIMBus Capture",
3321 .channels_min = 1,
3322 .channels_max = 2,
3323 .rates = RT5677_STEREO_RATES,
3324 .formats = RT5677_FORMATS,
3325 },
3326 .ops = &rt5677_aif_dai_ops,
3327 },
3328};
3329
3330static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
3331 .probe = rt5677_probe,
3332 .remove = rt5677_remove,
3333 .suspend = rt5677_suspend,
3334 .resume = rt5677_resume,
3335 .set_bias_level = rt5677_set_bias_level,
3336 .idle_bias_off = true,
3337 .controls = rt5677_snd_controls,
3338 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
3339 .dapm_widgets = rt5677_dapm_widgets,
3340 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
3341 .dapm_routes = rt5677_dapm_routes,
3342 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
3343};
3344
3345static const struct regmap_config rt5677_regmap = {
3346 .reg_bits = 8,
3347 .val_bits = 16,
3348
3349 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
3350 RT5677_PR_SPACING),
3351
3352 .volatile_reg = rt5677_volatile_register,
3353 .readable_reg = rt5677_readable_register,
3354
3355 .cache_type = REGCACHE_RBTREE,
3356 .reg_defaults = rt5677_reg,
3357 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
3358 .ranges = rt5677_ranges,
3359 .num_ranges = ARRAY_SIZE(rt5677_ranges),
3360};
3361
3362static const struct i2c_device_id rt5677_i2c_id[] = {
3363 { "rt5677", 0 },
3364 { }
3365};
3366MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
3367
3368static int rt5677_i2c_probe(struct i2c_client *i2c,
3369 const struct i2c_device_id *id)
3370{
3371 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
3372 struct rt5677_priv *rt5677;
3373 int ret;
3374 unsigned int val;
3375
3376 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
3377 GFP_KERNEL);
3378 if (rt5677 == NULL)
3379 return -ENOMEM;
3380
3381 i2c_set_clientdata(i2c, rt5677);
3382
3383 if (pdata)
3384 rt5677->pdata = *pdata;
3385
3386 rt5677->regmap = devm_regmap_init_i2c(i2c, &rt5677_regmap);
3387 if (IS_ERR(rt5677->regmap)) {
3388 ret = PTR_ERR(rt5677->regmap);
3389 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3390 ret);
3391 return ret;
3392 }
3393
3394 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
3395 if (val != RT5677_DEVICE_ID) {
3396 dev_err(&i2c->dev,
3397 "Device with ID register %x is not rt5677\n", val);
3398 return -ENODEV;
3399 }
3400
3401 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3402
3403 ret = regmap_register_patch(rt5677->regmap, init_list,
3404 ARRAY_SIZE(init_list));
3405 if (ret != 0)
3406 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3407
3408 if (rt5677->pdata.in1_diff)
3409 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3410 RT5677_IN_DF1, RT5677_IN_DF1);
3411
3412 if (rt5677->pdata.in2_diff)
3413 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3414 RT5677_IN_DF2, RT5677_IN_DF2);
3415
Bard Liao2d15d972014-08-27 19:50:34 +0800[diff] [blame]3416 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
3417 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
3418 RT5677_GPIO5_FUNC_MASK,
3419 RT5677_GPIO5_FUNC_DMIC);
3420 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3421 RT5677_GPIO5_DIR_MASK,
3422 RT5677_GPIO5_DIR_OUT);
3423 }
3424
Axel Lind0bdcb92014-06-10 11:37:24 +0800[diff] [blame]3425 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
3426 rt5677_dai, ARRAY_SIZE(rt5677_dai));
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3427}
3428
3429static int rt5677_i2c_remove(struct i2c_client *i2c)
3430{
3431 snd_soc_unregister_codec(&i2c->dev);
3432
3433 return 0;
3434}
3435
3436static struct i2c_driver rt5677_i2c_driver = {
3437 .driver = {
3438 .name = "rt5677",
3439 .owner = THIS_MODULE,
3440 },
3441 .probe = rt5677_i2c_probe,
3442 .remove = rt5677_i2c_remove,
3443 .id_table = rt5677_i2c_id,
3444};
Axel Linc8cfbec2014-06-03 10:56:41 +0800[diff] [blame]3445module_i2c_driver(rt5677_i2c_driver);
Oder Chiou0e826e82014-05-26 20:32:33 +0800[diff] [blame]3446
3447MODULE_DESCRIPTION("ASoC RT5677 driver");
3448MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
3449MODULE_LICENSE("GPL v2");