Blame - sound/soc/codecs/rt5677.c - kernel/msm-4.19

blob: 67f14556462ff35bd6601062fc55a40ec2a96310 [file] [log] [blame]

Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1	/*
				2	* rt5677.c -- RT5677 ALSA SoC audio codec driver
				3	*
				4	* Copyright 2013 Realtek Semiconductor Corp.
				5	* Author: Oder Chiou <oder_chiou@realtek.com>
				6	*
				7	* This program is free software; you can redistribute it and/or modify
				8	* it under the terms of the GNU General Public License version 2 as
				9	* published by the Free Software Foundation.
				10	*/
				11
				12	#include <linux/fs.h>
				13	#include <linux/module.h>
				14	#include <linux/moduleparam.h>
				15	#include <linux/init.h>
				16	#include <linux/delay.h>
				17	#include <linux/pm.h>
				18	#include <linux/regmap.h>
				19	#include <linux/i2c.h>
				20	#include <linux/platform_device.h>
				21	#include <linux/spi/spi.h>
				22	#include <sound/core.h>
				23	#include <sound/pcm.h>
				24	#include <sound/pcm_params.h>
				25	#include <sound/soc.h>
				26	#include <sound/soc-dapm.h>
				27	#include <sound/initval.h>
				28	#include <sound/tlv.h>
				29
Axel Lin	30f14b4	2014-06-10 08:57:36 +0800	[diff] [blame]	30	#include "rl6231.h"
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	31	#include "rt5677.h"
				32
				33	#define RT5677_DEVICE_ID 0x6327
				34
				35	#define RT5677_PR_RANGE_BASE (0xff + 1)
				36	#define RT5677_PR_SPACING 0x100
				37
				38	#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
				39
				40	static const struct regmap_range_cfg rt5677_ranges[] = {
				41	{
				42	.name = "PR",
				43	.range_min = RT5677_PR_BASE,
				44	.range_max = RT5677_PR_BASE + 0xfd,
				45	.selector_reg = RT5677_PRIV_INDEX,
				46	.selector_mask = 0xff,
				47	.selector_shift = 0x0,
				48	.window_start = RT5677_PRIV_DATA,
				49	.window_len = 0x1,
				50	},
				51	};
				52
				53	static const struct reg_default init_list[] = {
				54	{RT5677_PR_BASE + 0x3d, 0x364d},
				55	{RT5677_PR_BASE + 0x17, 0x4fc0},
				56	{RT5677_PR_BASE + 0x13, 0x0312},
				57	{RT5677_PR_BASE + 0x1e, 0x0000},
				58	{RT5677_PR_BASE + 0x12, 0x0eaa},
				59	{RT5677_PR_BASE + 0x14, 0x018a},
				60	};
				61	#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
				62
				63	static const struct reg_default rt5677_reg[] = {
				64	{RT5677_RESET , 0x0000},
				65	{RT5677_LOUT1 , 0xa800},
				66	{RT5677_IN1 , 0x0000},
				67	{RT5677_MICBIAS , 0x0000},
				68	{RT5677_SLIMBUS_PARAM , 0x0000},
				69	{RT5677_SLIMBUS_RX , 0x0000},
				70	{RT5677_SLIMBUS_CTRL , 0x0000},
				71	{RT5677_SIDETONE_CTRL , 0x000b},
				72	{RT5677_ANA_DAC1_2_3_SRC , 0x0000},
				73	{RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
				74	{RT5677_DAC4_DIG_VOL , 0xafaf},
				75	{RT5677_DAC3_DIG_VOL , 0xafaf},
				76	{RT5677_DAC1_DIG_VOL , 0xafaf},
				77	{RT5677_DAC2_DIG_VOL , 0xafaf},
				78	{RT5677_IF_DSP_DAC2_MIXER , 0x0011},
				79	{RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
				80	{RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
				81	{RT5677_STO1_2_ADC_BST , 0x0000},
				82	{RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
				83	{RT5677_ADC_BST_CTRL2 , 0x0000},
				84	{RT5677_STO3_4_ADC_BST , 0x0000},
				85	{RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
				86	{RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
				87	{RT5677_STO4_ADC_MIXER , 0xd4c0},
				88	{RT5677_STO3_ADC_MIXER , 0xd4c0},
				89	{RT5677_STO2_ADC_MIXER , 0xd4c0},
				90	{RT5677_STO1_ADC_MIXER , 0xd4c0},
				91	{RT5677_MONO_ADC_MIXER , 0xd4d1},
				92	{RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
				93	{RT5677_STO1_DAC_MIXER , 0xaaaa},
				94	{RT5677_MONO_DAC_MIXER , 0xaaaa},
				95	{RT5677_DD1_MIXER , 0xaaaa},
				96	{RT5677_DD2_MIXER , 0xaaaa},
				97	{RT5677_IF3_DATA , 0x0000},
				98	{RT5677_IF4_DATA , 0x0000},
				99	{RT5677_PDM_OUT_CTRL , 0x8888},
				100	{RT5677_PDM_DATA_CTRL1 , 0x0000},
				101	{RT5677_PDM_DATA_CTRL2 , 0x0000},
				102	{RT5677_PDM1_DATA_CTRL2 , 0x0000},
				103	{RT5677_PDM1_DATA_CTRL3 , 0x0000},
				104	{RT5677_PDM1_DATA_CTRL4 , 0x0000},
				105	{RT5677_PDM2_DATA_CTRL2 , 0x0000},
				106	{RT5677_PDM2_DATA_CTRL3 , 0x0000},
				107	{RT5677_PDM2_DATA_CTRL4 , 0x0000},
				108	{RT5677_TDM1_CTRL1 , 0x0300},
				109	{RT5677_TDM1_CTRL2 , 0x0000},
				110	{RT5677_TDM1_CTRL3 , 0x4000},
				111	{RT5677_TDM1_CTRL4 , 0x0123},
				112	{RT5677_TDM1_CTRL5 , 0x4567},
				113	{RT5677_TDM2_CTRL1 , 0x0300},
				114	{RT5677_TDM2_CTRL2 , 0x0000},
				115	{RT5677_TDM2_CTRL3 , 0x4000},
				116	{RT5677_TDM2_CTRL4 , 0x0123},
				117	{RT5677_TDM2_CTRL5 , 0x4567},
				118	{RT5677_I2C_MASTER_CTRL1 , 0x0001},
				119	{RT5677_I2C_MASTER_CTRL2 , 0x0000},
				120	{RT5677_I2C_MASTER_CTRL3 , 0x0000},
				121	{RT5677_I2C_MASTER_CTRL4 , 0x0000},
				122	{RT5677_I2C_MASTER_CTRL5 , 0x0000},
				123	{RT5677_I2C_MASTER_CTRL6 , 0x0000},
				124	{RT5677_I2C_MASTER_CTRL7 , 0x0000},
				125	{RT5677_I2C_MASTER_CTRL8 , 0x0000},
				126	{RT5677_DMIC_CTRL1 , 0x1505},
				127	{RT5677_DMIC_CTRL2 , 0x0055},
				128	{RT5677_HAP_GENE_CTRL1 , 0x0111},
				129	{RT5677_HAP_GENE_CTRL2 , 0x0064},
				130	{RT5677_HAP_GENE_CTRL3 , 0xef0e},
				131	{RT5677_HAP_GENE_CTRL4 , 0xf0f0},
				132	{RT5677_HAP_GENE_CTRL5 , 0xef0e},
				133	{RT5677_HAP_GENE_CTRL6 , 0xf0f0},
				134	{RT5677_HAP_GENE_CTRL7 , 0xef0e},
				135	{RT5677_HAP_GENE_CTRL8 , 0xf0f0},
				136	{RT5677_HAP_GENE_CTRL9 , 0xf000},
				137	{RT5677_HAP_GENE_CTRL10 , 0x0000},
				138	{RT5677_PWR_DIG1 , 0x0000},
				139	{RT5677_PWR_DIG2 , 0x0000},
				140	{RT5677_PWR_ANLG1 , 0x0055},
				141	{RT5677_PWR_ANLG2 , 0x0000},
				142	{RT5677_PWR_DSP1 , 0x0001},
				143	{RT5677_PWR_DSP_ST , 0x0000},
				144	{RT5677_PWR_DSP2 , 0x0000},
				145	{RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
				146	{RT5677_PRIV_INDEX , 0x0000},
				147	{RT5677_PRIV_DATA , 0x0000},
				148	{RT5677_I2S4_SDP , 0x8000},
				149	{RT5677_I2S1_SDP , 0x8000},
				150	{RT5677_I2S2_SDP , 0x8000},
				151	{RT5677_I2S3_SDP , 0x8000},
				152	{RT5677_CLK_TREE_CTRL1 , 0x1111},
				153	{RT5677_CLK_TREE_CTRL2 , 0x1111},
				154	{RT5677_CLK_TREE_CTRL3 , 0x0000},
				155	{RT5677_PLL1_CTRL1 , 0x0000},
				156	{RT5677_PLL1_CTRL2 , 0x0000},
				157	{RT5677_PLL2_CTRL1 , 0x0c60},
				158	{RT5677_PLL2_CTRL2 , 0x2000},
				159	{RT5677_GLB_CLK1 , 0x0000},
				160	{RT5677_GLB_CLK2 , 0x0000},
				161	{RT5677_ASRC_1 , 0x0000},
				162	{RT5677_ASRC_2 , 0x0000},
				163	{RT5677_ASRC_3 , 0x0000},
				164	{RT5677_ASRC_4 , 0x0000},
				165	{RT5677_ASRC_5 , 0x0000},
				166	{RT5677_ASRC_6 , 0x0000},
				167	{RT5677_ASRC_7 , 0x0000},
				168	{RT5677_ASRC_8 , 0x0000},
				169	{RT5677_ASRC_9 , 0x0000},
				170	{RT5677_ASRC_10 , 0x0000},
				171	{RT5677_ASRC_11 , 0x0000},
				172	{RT5677_ASRC_12 , 0x0008},
				173	{RT5677_ASRC_13 , 0x0000},
				174	{RT5677_ASRC_14 , 0x0000},
				175	{RT5677_ASRC_15 , 0x0000},
				176	{RT5677_ASRC_16 , 0x0000},
				177	{RT5677_ASRC_17 , 0x0000},
				178	{RT5677_ASRC_18 , 0x0000},
				179	{RT5677_ASRC_19 , 0x0000},
				180	{RT5677_ASRC_20 , 0x0000},
				181	{RT5677_ASRC_21 , 0x000c},
				182	{RT5677_ASRC_22 , 0x0000},
				183	{RT5677_ASRC_23 , 0x0000},
				184	{RT5677_VAD_CTRL1 , 0x2184},
				185	{RT5677_VAD_CTRL2 , 0x010a},
				186	{RT5677_VAD_CTRL3 , 0x0aea},
				187	{RT5677_VAD_CTRL4 , 0x000c},
				188	{RT5677_VAD_CTRL5 , 0x0000},
				189	{RT5677_DSP_INB_CTRL1 , 0x0000},
				190	{RT5677_DSP_INB_CTRL2 , 0x0000},
				191	{RT5677_DSP_IN_OUTB_CTRL , 0x0000},
				192	{RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
				193	{RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
				194	{RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
				195	{RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
				196	{RT5677_ADC_EQ_CTRL1 , 0x6000},
				197	{RT5677_ADC_EQ_CTRL2 , 0x0000},
				198	{RT5677_EQ_CTRL1 , 0xc000},
				199	{RT5677_EQ_CTRL2 , 0x0000},
				200	{RT5677_EQ_CTRL3 , 0x0000},
				201	{RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
				202	{RT5677_JD_CTRL1 , 0x0000},
				203	{RT5677_JD_CTRL2 , 0x0000},
				204	{RT5677_JD_CTRL3 , 0x0000},
				205	{RT5677_IRQ_CTRL1 , 0x0000},
				206	{RT5677_IRQ_CTRL2 , 0x0000},
				207	{RT5677_GPIO_ST , 0x0000},
				208	{RT5677_GPIO_CTRL1 , 0x0000},
				209	{RT5677_GPIO_CTRL2 , 0x0000},
				210	{RT5677_GPIO_CTRL3 , 0x0000},
				211	{RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
				212	{RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
				213	{RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
				214	{RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
				215	{RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
				216	{RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
				217	{RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
				218	{RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
				219	{RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
				220	{RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
				221	{RT5677_MB_DRC_CTRL1 , 0x0f20},
				222	{RT5677_DRC1_CTRL1 , 0x001f},
				223	{RT5677_DRC1_CTRL2 , 0x020c},
				224	{RT5677_DRC1_CTRL3 , 0x1f00},
				225	{RT5677_DRC1_CTRL4 , 0x0000},
				226	{RT5677_DRC1_CTRL5 , 0x0000},
				227	{RT5677_DRC1_CTRL6 , 0x0029},
				228	{RT5677_DRC2_CTRL1 , 0x001f},
				229	{RT5677_DRC2_CTRL2 , 0x020c},
				230	{RT5677_DRC2_CTRL3 , 0x1f00},
				231	{RT5677_DRC2_CTRL4 , 0x0000},
				232	{RT5677_DRC2_CTRL5 , 0x0000},
				233	{RT5677_DRC2_CTRL6 , 0x0029},
				234	{RT5677_DRC1_HL_CTRL1 , 0x8000},
				235	{RT5677_DRC1_HL_CTRL2 , 0x0200},
				236	{RT5677_DRC2_HL_CTRL1 , 0x8000},
				237	{RT5677_DRC2_HL_CTRL2 , 0x0200},
				238	{RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
				239	{RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
				240	{RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
				241	{RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
				242	{RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
				243	{RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
				244	{RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
				245	{RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
				246	{RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
				247	{RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
				248	{RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
				249	{RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
				250	{RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
				251	{RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
				252	{RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
				253	{RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
				254	{RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
				255	{RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
				256	{RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
				257	{RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
				258	{RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
				259	{RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
				260	{RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
				261	{RT5677_DIG_MISC , 0x0000},
				262	{RT5677_GEN_CTRL1 , 0x0000},
				263	{RT5677_GEN_CTRL2 , 0x0000},
				264	{RT5677_VENDOR_ID , 0x0000},
				265	{RT5677_VENDOR_ID1 , 0x10ec},
				266	{RT5677_VENDOR_ID2 , 0x6327},
				267	};
				268
				269	static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
				270	{
				271	int i;
				272
				273	for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
				274	if (reg >= rt5677_ranges[i].range_min &&
				275	reg <= rt5677_ranges[i].range_max) {
				276	return true;
				277	}
				278	}
				279
				280	switch (reg) {
				281	case RT5677_RESET:
				282	case RT5677_SLIMBUS_PARAM:
				283	case RT5677_PDM_DATA_CTRL1:
				284	case RT5677_PDM_DATA_CTRL2:
				285	case RT5677_PDM1_DATA_CTRL4:
				286	case RT5677_PDM2_DATA_CTRL4:
				287	case RT5677_I2C_MASTER_CTRL1:
				288	case RT5677_I2C_MASTER_CTRL7:
				289	case RT5677_I2C_MASTER_CTRL8:
				290	case RT5677_HAP_GENE_CTRL2:
				291	case RT5677_PWR_DSP_ST:
				292	case RT5677_PRIV_DATA:
				293	case RT5677_PLL1_CTRL2:
				294	case RT5677_PLL2_CTRL2:
				295	case RT5677_ASRC_22:
				296	case RT5677_ASRC_23:
				297	case RT5677_VAD_CTRL5:
				298	case RT5677_ADC_EQ_CTRL1:
				299	case RT5677_EQ_CTRL1:
				300	case RT5677_IRQ_CTRL1:
				301	case RT5677_IRQ_CTRL2:
				302	case RT5677_GPIO_ST:
				303	case RT5677_DSP_INB1_SRC_CTRL4:
				304	case RT5677_DSP_INB2_SRC_CTRL4:
				305	case RT5677_DSP_INB3_SRC_CTRL4:
				306	case RT5677_DSP_OUTB1_SRC_CTRL4:
				307	case RT5677_DSP_OUTB2_SRC_CTRL4:
				308	case RT5677_VENDOR_ID:
				309	case RT5677_VENDOR_ID1:
				310	case RT5677_VENDOR_ID2:
				311	return true;
				312	default:
				313	return false;
				314	}
				315	}
				316
				317	static bool rt5677_readable_register(struct device *dev, unsigned int reg)
				318	{
				319	int i;
				320
				321	for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
				322	if (reg >= rt5677_ranges[i].range_min &&
				323	reg <= rt5677_ranges[i].range_max) {
				324	return true;
				325	}
				326	}
				327
				328	switch (reg) {
				329	case RT5677_RESET:
				330	case RT5677_LOUT1:
				331	case RT5677_IN1:
				332	case RT5677_MICBIAS:
				333	case RT5677_SLIMBUS_PARAM:
				334	case RT5677_SLIMBUS_RX:
				335	case RT5677_SLIMBUS_CTRL:
				336	case RT5677_SIDETONE_CTRL:
				337	case RT5677_ANA_DAC1_2_3_SRC:
				338	case RT5677_IF_DSP_DAC3_4_MIXER:
				339	case RT5677_DAC4_DIG_VOL:
				340	case RT5677_DAC3_DIG_VOL:
				341	case RT5677_DAC1_DIG_VOL:
				342	case RT5677_DAC2_DIG_VOL:
				343	case RT5677_IF_DSP_DAC2_MIXER:
				344	case RT5677_STO1_ADC_DIG_VOL:
				345	case RT5677_MONO_ADC_DIG_VOL:
				346	case RT5677_STO1_2_ADC_BST:
				347	case RT5677_STO2_ADC_DIG_VOL:
				348	case RT5677_ADC_BST_CTRL2:
				349	case RT5677_STO3_4_ADC_BST:
				350	case RT5677_STO3_ADC_DIG_VOL:
				351	case RT5677_STO4_ADC_DIG_VOL:
				352	case RT5677_STO4_ADC_MIXER:
				353	case RT5677_STO3_ADC_MIXER:
				354	case RT5677_STO2_ADC_MIXER:
				355	case RT5677_STO1_ADC_MIXER:
				356	case RT5677_MONO_ADC_MIXER:
				357	case RT5677_ADC_IF_DSP_DAC1_MIXER:
				358	case RT5677_STO1_DAC_MIXER:
				359	case RT5677_MONO_DAC_MIXER:
				360	case RT5677_DD1_MIXER:
				361	case RT5677_DD2_MIXER:
				362	case RT5677_IF3_DATA:
				363	case RT5677_IF4_DATA:
				364	case RT5677_PDM_OUT_CTRL:
				365	case RT5677_PDM_DATA_CTRL1:
				366	case RT5677_PDM_DATA_CTRL2:
				367	case RT5677_PDM1_DATA_CTRL2:
				368	case RT5677_PDM1_DATA_CTRL3:
				369	case RT5677_PDM1_DATA_CTRL4:
				370	case RT5677_PDM2_DATA_CTRL2:
				371	case RT5677_PDM2_DATA_CTRL3:
				372	case RT5677_PDM2_DATA_CTRL4:
				373	case RT5677_TDM1_CTRL1:
				374	case RT5677_TDM1_CTRL2:
				375	case RT5677_TDM1_CTRL3:
				376	case RT5677_TDM1_CTRL4:
				377	case RT5677_TDM1_CTRL5:
				378	case RT5677_TDM2_CTRL1:
				379	case RT5677_TDM2_CTRL2:
				380	case RT5677_TDM2_CTRL3:
				381	case RT5677_TDM2_CTRL4:
				382	case RT5677_TDM2_CTRL5:
				383	case RT5677_I2C_MASTER_CTRL1:
				384	case RT5677_I2C_MASTER_CTRL2:
				385	case RT5677_I2C_MASTER_CTRL3:
				386	case RT5677_I2C_MASTER_CTRL4:
				387	case RT5677_I2C_MASTER_CTRL5:
				388	case RT5677_I2C_MASTER_CTRL6:
				389	case RT5677_I2C_MASTER_CTRL7:
				390	case RT5677_I2C_MASTER_CTRL8:
				391	case RT5677_DMIC_CTRL1:
				392	case RT5677_DMIC_CTRL2:
				393	case RT5677_HAP_GENE_CTRL1:
				394	case RT5677_HAP_GENE_CTRL2:
				395	case RT5677_HAP_GENE_CTRL3:
				396	case RT5677_HAP_GENE_CTRL4:
				397	case RT5677_HAP_GENE_CTRL5:
				398	case RT5677_HAP_GENE_CTRL6:
				399	case RT5677_HAP_GENE_CTRL7:
				400	case RT5677_HAP_GENE_CTRL8:
				401	case RT5677_HAP_GENE_CTRL9:
				402	case RT5677_HAP_GENE_CTRL10:
				403	case RT5677_PWR_DIG1:
				404	case RT5677_PWR_DIG2:
				405	case RT5677_PWR_ANLG1:
				406	case RT5677_PWR_ANLG2:
				407	case RT5677_PWR_DSP1:
				408	case RT5677_PWR_DSP_ST:
				409	case RT5677_PWR_DSP2:
				410	case RT5677_ADC_DAC_HPF_CTRL1:
				411	case RT5677_PRIV_INDEX:
				412	case RT5677_PRIV_DATA:
				413	case RT5677_I2S4_SDP:
				414	case RT5677_I2S1_SDP:
				415	case RT5677_I2S2_SDP:
				416	case RT5677_I2S3_SDP:
				417	case RT5677_CLK_TREE_CTRL1:
				418	case RT5677_CLK_TREE_CTRL2:
				419	case RT5677_CLK_TREE_CTRL3:
				420	case RT5677_PLL1_CTRL1:
				421	case RT5677_PLL1_CTRL2:
				422	case RT5677_PLL2_CTRL1:
				423	case RT5677_PLL2_CTRL2:
				424	case RT5677_GLB_CLK1:
				425	case RT5677_GLB_CLK2:
				426	case RT5677_ASRC_1:
				427	case RT5677_ASRC_2:
				428	case RT5677_ASRC_3:
				429	case RT5677_ASRC_4:
				430	case RT5677_ASRC_5:
				431	case RT5677_ASRC_6:
				432	case RT5677_ASRC_7:
				433	case RT5677_ASRC_8:
				434	case RT5677_ASRC_9:
				435	case RT5677_ASRC_10:
				436	case RT5677_ASRC_11:
				437	case RT5677_ASRC_12:
				438	case RT5677_ASRC_13:
				439	case RT5677_ASRC_14:
				440	case RT5677_ASRC_15:
				441	case RT5677_ASRC_16:
				442	case RT5677_ASRC_17:
				443	case RT5677_ASRC_18:
				444	case RT5677_ASRC_19:
				445	case RT5677_ASRC_20:
				446	case RT5677_ASRC_21:
				447	case RT5677_ASRC_22:
				448	case RT5677_ASRC_23:
				449	case RT5677_VAD_CTRL1:
				450	case RT5677_VAD_CTRL2:
				451	case RT5677_VAD_CTRL3:
				452	case RT5677_VAD_CTRL4:
				453	case RT5677_VAD_CTRL5:
				454	case RT5677_DSP_INB_CTRL1:
				455	case RT5677_DSP_INB_CTRL2:
				456	case RT5677_DSP_IN_OUTB_CTRL:
				457	case RT5677_DSP_OUTB0_1_DIG_VOL:
				458	case RT5677_DSP_OUTB2_3_DIG_VOL:
				459	case RT5677_DSP_OUTB4_5_DIG_VOL:
				460	case RT5677_DSP_OUTB6_7_DIG_VOL:
				461	case RT5677_ADC_EQ_CTRL1:
				462	case RT5677_ADC_EQ_CTRL2:
				463	case RT5677_EQ_CTRL1:
				464	case RT5677_EQ_CTRL2:
				465	case RT5677_EQ_CTRL3:
				466	case RT5677_SOFT_VOL_ZERO_CROSS1:
				467	case RT5677_JD_CTRL1:
				468	case RT5677_JD_CTRL2:
				469	case RT5677_JD_CTRL3:
				470	case RT5677_IRQ_CTRL1:
				471	case RT5677_IRQ_CTRL2:
				472	case RT5677_GPIO_ST:
				473	case RT5677_GPIO_CTRL1:
				474	case RT5677_GPIO_CTRL2:
				475	case RT5677_GPIO_CTRL3:
				476	case RT5677_STO1_ADC_HI_FILTER1:
				477	case RT5677_STO1_ADC_HI_FILTER2:
				478	case RT5677_MONO_ADC_HI_FILTER1:
				479	case RT5677_MONO_ADC_HI_FILTER2:
				480	case RT5677_STO2_ADC_HI_FILTER1:
				481	case RT5677_STO2_ADC_HI_FILTER2:
				482	case RT5677_STO3_ADC_HI_FILTER1:
				483	case RT5677_STO3_ADC_HI_FILTER2:
				484	case RT5677_STO4_ADC_HI_FILTER1:
				485	case RT5677_STO4_ADC_HI_FILTER2:
				486	case RT5677_MB_DRC_CTRL1:
				487	case RT5677_DRC1_CTRL1:
				488	case RT5677_DRC1_CTRL2:
				489	case RT5677_DRC1_CTRL3:
				490	case RT5677_DRC1_CTRL4:
				491	case RT5677_DRC1_CTRL5:
				492	case RT5677_DRC1_CTRL6:
				493	case RT5677_DRC2_CTRL1:
				494	case RT5677_DRC2_CTRL2:
				495	case RT5677_DRC2_CTRL3:
				496	case RT5677_DRC2_CTRL4:
				497	case RT5677_DRC2_CTRL5:
				498	case RT5677_DRC2_CTRL6:
				499	case RT5677_DRC1_HL_CTRL1:
				500	case RT5677_DRC1_HL_CTRL2:
				501	case RT5677_DRC2_HL_CTRL1:
				502	case RT5677_DRC2_HL_CTRL2:
				503	case RT5677_DSP_INB1_SRC_CTRL1:
				504	case RT5677_DSP_INB1_SRC_CTRL2:
				505	case RT5677_DSP_INB1_SRC_CTRL3:
				506	case RT5677_DSP_INB1_SRC_CTRL4:
				507	case RT5677_DSP_INB2_SRC_CTRL1:
				508	case RT5677_DSP_INB2_SRC_CTRL2:
				509	case RT5677_DSP_INB2_SRC_CTRL3:
				510	case RT5677_DSP_INB2_SRC_CTRL4:
				511	case RT5677_DSP_INB3_SRC_CTRL1:
				512	case RT5677_DSP_INB3_SRC_CTRL2:
				513	case RT5677_DSP_INB3_SRC_CTRL3:
				514	case RT5677_DSP_INB3_SRC_CTRL4:
				515	case RT5677_DSP_OUTB1_SRC_CTRL1:
				516	case RT5677_DSP_OUTB1_SRC_CTRL2:
				517	case RT5677_DSP_OUTB1_SRC_CTRL3:
				518	case RT5677_DSP_OUTB1_SRC_CTRL4:
				519	case RT5677_DSP_OUTB2_SRC_CTRL1:
				520	case RT5677_DSP_OUTB2_SRC_CTRL2:
				521	case RT5677_DSP_OUTB2_SRC_CTRL3:
				522	case RT5677_DSP_OUTB2_SRC_CTRL4:
				523	case RT5677_DSP_OUTB_0123_MIXER_CTRL:
				524	case RT5677_DSP_OUTB_45_MIXER_CTRL:
				525	case RT5677_DSP_OUTB_67_MIXER_CTRL:
				526	case RT5677_DIG_MISC:
				527	case RT5677_GEN_CTRL1:
				528	case RT5677_GEN_CTRL2:
				529	case RT5677_VENDOR_ID:
				530	case RT5677_VENDOR_ID1:
				531	case RT5677_VENDOR_ID2:
				532	return true;
				533	default:
				534	return false;
				535	}
				536	}
				537
				538	static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
				539	static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
				540	static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
				541	static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
				542	static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
				543
				544	/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
				545	static unsigned int bst_tlv[] = {
				546	TLV_DB_RANGE_HEAD(7),
				547	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
				548	1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
				549	2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
				550	3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
				551	6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
				552	7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
				553	8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
				554	};
				555
				556	static const struct snd_kcontrol_new rt5677_snd_controls[] = {
				557	/* OUTPUT Control */
				558	SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
				559	RT5677_LOUT1_L_MUTE_SFT, 1, 1),
				560	SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
				561	RT5677_LOUT2_L_MUTE_SFT, 1, 1),
				562	SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
				563	RT5677_LOUT3_L_MUTE_SFT, 1, 1),
				564
				565	/* DAC Digital Volume */
				566	SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
				567	RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
				568	SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
				569	RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
				570	SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
				571	RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
				572	SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
				573	RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
				574
				575	/* IN1/IN2 Control */
				576	SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
				577	SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
				578
				579	/* ADC Digital Volume Control */
				580	SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
				581	RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
				582	SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
				583	RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
				584	SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
				585	RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
				586	SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
				587	RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
				588	SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
				589	RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
				590
				591	SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
				592	RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
				593	adc_vol_tlv),
				594	SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
				595	RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
				596	adc_vol_tlv),
				597	SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
				598	RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
				599	adc_vol_tlv),
				600	SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
				601	RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
				602	adc_vol_tlv),
				603	SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
				604	RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0,
				605	adc_vol_tlv),
				606
				607	/* ADC Boost Volume Control */
Oder Chiou	80220f2	2014-06-10 14:35:25 +0800	[diff] [blame]	608	SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	609	RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
				610	adc_bst_tlv),
Oder Chiou	80220f2	2014-06-10 14:35:25 +0800	[diff] [blame]	611	SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	612	RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
				613	adc_bst_tlv),
Oder Chiou	80220f2	2014-06-10 14:35:25 +0800	[diff] [blame]	614	SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	615	RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
				616	adc_bst_tlv),
Oder Chiou	80220f2	2014-06-10 14:35:25 +0800	[diff] [blame]	617	SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	618	RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
				619	adc_bst_tlv),
Oder Chiou	80220f2	2014-06-10 14:35:25 +0800	[diff] [blame]	620	SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	621	RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
				622	adc_bst_tlv),
				623	};
				624
				625	/**
				626	* set_dmic_clk - Set parameter of dmic.
				627	*
				628	* @w: DAPM widget.
				629	* @kcontrol: The kcontrol of this widget.
				630	* @event: Event id.
				631	*
				632	* Choose dmic clock between 1MHz and 3MHz.
				633	* It is better for clock to approximate 3MHz.
				634	*/
				635	static int set_dmic_clk(struct snd_soc_dapm_widget *w,
				636	struct snd_kcontrol *kcontrol, int event)
				637	{
				638	struct snd_soc_codec *codec = w->codec;
				639	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
Axel Lin	9a53581	2014-06-03 10:58:58 +0800	[diff] [blame]	640	int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	641
				642	if (idx < 0)
				643	dev_err(codec->dev, "Failed to set DMIC clock\n");
				644	else
				645	regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
				646	RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
				647	return idx;
				648	}
				649
				650	static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
				651	struct snd_soc_dapm_widget *sink)
				652	{
				653	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
				654	unsigned int val;
				655
				656	regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
				657	val &= RT5677_SCLK_SRC_MASK;
				658	if (val == RT5677_SCLK_SRC_PLL1)
				659	return 1;
				660	else
				661	return 0;
				662	}
				663
				664	/* Digital Mixer */
				665	static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
				666	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
				667	RT5677_M_STO1_ADC_L1_SFT, 1, 1),
				668	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
				669	RT5677_M_STO1_ADC_L2_SFT, 1, 1),
				670	};
				671
				672	static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
				673	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
				674	RT5677_M_STO1_ADC_R1_SFT, 1, 1),
				675	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
				676	RT5677_M_STO1_ADC_R2_SFT, 1, 1),
				677	};
				678
				679	static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
				680	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
				681	RT5677_M_STO2_ADC_L1_SFT, 1, 1),
				682	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
				683	RT5677_M_STO2_ADC_L2_SFT, 1, 1),
				684	};
				685
				686	static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
				687	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
				688	RT5677_M_STO2_ADC_R1_SFT, 1, 1),
				689	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
				690	RT5677_M_STO2_ADC_R2_SFT, 1, 1),
				691	};
				692
				693	static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
				694	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
				695	RT5677_M_STO3_ADC_L1_SFT, 1, 1),
				696	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
				697	RT5677_M_STO3_ADC_L2_SFT, 1, 1),
				698	};
				699
				700	static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
				701	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
				702	RT5677_M_STO3_ADC_R1_SFT, 1, 1),
				703	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
				704	RT5677_M_STO3_ADC_R2_SFT, 1, 1),
				705	};
				706
				707	static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
				708	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
				709	RT5677_M_STO4_ADC_L1_SFT, 1, 1),
				710	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
				711	RT5677_M_STO4_ADC_L2_SFT, 1, 1),
				712	};
				713
				714	static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
				715	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
				716	RT5677_M_STO4_ADC_R1_SFT, 1, 1),
				717	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
				718	RT5677_M_STO4_ADC_R2_SFT, 1, 1),
				719	};
				720
				721	static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
				722	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
				723	RT5677_M_MONO_ADC_L1_SFT, 1, 1),
				724	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
				725	RT5677_M_MONO_ADC_L2_SFT, 1, 1),
				726	};
				727
				728	static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
				729	SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
				730	RT5677_M_MONO_ADC_R1_SFT, 1, 1),
				731	SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
				732	RT5677_M_MONO_ADC_R2_SFT, 1, 1),
				733	};
				734
				735	static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
				736	SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
				737	RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
				738	SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
				739	RT5677_M_DAC1_L_SFT, 1, 1),
				740	};
				741
				742	static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
				743	SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
				744	RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
				745	SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
				746	RT5677_M_DAC1_R_SFT, 1, 1),
				747	};
				748
				749	static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
				750	SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
				751	RT5677_M_ST_DAC1_L_SFT, 1, 1),
				752	SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
				753	RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
				754	SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
				755	RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
				756	SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
				757	RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
				758	};
				759
				760	static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
				761	SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
				762	RT5677_M_ST_DAC1_R_SFT, 1, 1),
				763	SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
				764	RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
				765	SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
				766	RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
				767	SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
				768	RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
				769	};
				770
				771	static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
				772	SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
				773	RT5677_M_ST_DAC2_L_SFT, 1, 1),
				774	SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
				775	RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
				776	SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
				777	RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
				778	SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
				779	RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
				780	};
				781
				782	static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
				783	SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
				784	RT5677_M_ST_DAC2_R_SFT, 1, 1),
				785	SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
				786	RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
				787	SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
				788	RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
				789	SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
				790	RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
				791	};
				792
				793	static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
				794	SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
				795	RT5677_M_STO_L_DD1_L_SFT, 1, 1),
				796	SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
				797	RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
				798	SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
				799	RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
				800	SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
				801	RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
				802	};
				803
				804	static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
				805	SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
				806	RT5677_M_STO_R_DD1_R_SFT, 1, 1),
				807	SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
				808	RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
				809	SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
				810	RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
				811	SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
				812	RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
				813	};
				814
				815	static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
				816	SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
				817	RT5677_M_STO_L_DD2_L_SFT, 1, 1),
				818	SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
				819	RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
				820	SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
				821	RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
				822	SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
				823	RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
				824	};
				825
				826	static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
				827	SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
				828	RT5677_M_STO_R_DD2_R_SFT, 1, 1),
				829	SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
				830	RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
				831	SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
				832	RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
				833	SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
				834	RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
				835	};
				836
				837	static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
				838	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
				839	RT5677_DSP_IB_01_H_SFT, 1, 1),
				840	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
				841	RT5677_DSP_IB_23_H_SFT, 1, 1),
				842	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
				843	RT5677_DSP_IB_45_H_SFT, 1, 1),
				844	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
				845	RT5677_DSP_IB_6_H_SFT, 1, 1),
				846	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
				847	RT5677_DSP_IB_7_H_SFT, 1, 1),
				848	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
				849	RT5677_DSP_IB_8_H_SFT, 1, 1),
				850	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
				851	RT5677_DSP_IB_9_H_SFT, 1, 1),
				852	};
				853
				854	static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
				855	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
				856	RT5677_DSP_IB_01_L_SFT, 1, 1),
				857	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
				858	RT5677_DSP_IB_23_L_SFT, 1, 1),
				859	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
				860	RT5677_DSP_IB_45_L_SFT, 1, 1),
				861	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
				862	RT5677_DSP_IB_6_L_SFT, 1, 1),
				863	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
				864	RT5677_DSP_IB_7_L_SFT, 1, 1),
				865	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
				866	RT5677_DSP_IB_8_L_SFT, 1, 1),
				867	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
				868	RT5677_DSP_IB_9_L_SFT, 1, 1),
				869	};
				870
				871	static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
				872	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
				873	RT5677_DSP_IB_01_H_SFT, 1, 1),
				874	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
				875	RT5677_DSP_IB_23_H_SFT, 1, 1),
				876	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
				877	RT5677_DSP_IB_45_H_SFT, 1, 1),
				878	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
				879	RT5677_DSP_IB_6_H_SFT, 1, 1),
				880	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
				881	RT5677_DSP_IB_7_H_SFT, 1, 1),
				882	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
				883	RT5677_DSP_IB_8_H_SFT, 1, 1),
				884	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
				885	RT5677_DSP_IB_9_H_SFT, 1, 1),
				886	};
				887
				888	static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
				889	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
				890	RT5677_DSP_IB_01_L_SFT, 1, 1),
				891	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
				892	RT5677_DSP_IB_23_L_SFT, 1, 1),
				893	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
				894	RT5677_DSP_IB_45_L_SFT, 1, 1),
				895	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
				896	RT5677_DSP_IB_6_L_SFT, 1, 1),
				897	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
				898	RT5677_DSP_IB_7_L_SFT, 1, 1),
				899	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
				900	RT5677_DSP_IB_8_L_SFT, 1, 1),
				901	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
				902	RT5677_DSP_IB_9_L_SFT, 1, 1),
				903	};
				904
				905	static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
				906	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
				907	RT5677_DSP_IB_01_H_SFT, 1, 1),
				908	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
				909	RT5677_DSP_IB_23_H_SFT, 1, 1),
				910	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
				911	RT5677_DSP_IB_45_H_SFT, 1, 1),
				912	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
				913	RT5677_DSP_IB_6_H_SFT, 1, 1),
				914	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
				915	RT5677_DSP_IB_7_H_SFT, 1, 1),
				916	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
				917	RT5677_DSP_IB_8_H_SFT, 1, 1),
				918	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
				919	RT5677_DSP_IB_9_H_SFT, 1, 1),
				920	};
				921
				922	static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
				923	SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
				924	RT5677_DSP_IB_01_L_SFT, 1, 1),
				925	SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
				926	RT5677_DSP_IB_23_L_SFT, 1, 1),
				927	SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
				928	RT5677_DSP_IB_45_L_SFT, 1, 1),
				929	SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
				930	RT5677_DSP_IB_6_L_SFT, 1, 1),
				931	SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
				932	RT5677_DSP_IB_7_L_SFT, 1, 1),
				933	SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
				934	RT5677_DSP_IB_8_L_SFT, 1, 1),
				935	SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
				936	RT5677_DSP_IB_9_L_SFT, 1, 1),
				937	};
				938
				939
				940	/* Mux */
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	941	/* DAC1 L/R Source / / MX-29 [10:8] */
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	942	static const char * const rt5677_dac1_src[] = {
				943	"IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
				944	"OB 01"
				945	};
				946
				947	static SOC_ENUM_SINGLE_DECL(
				948	rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
				949	RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
				950
				951	static const struct snd_kcontrol_new rt5677_dac1_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	952	SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	953
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	954	/* ADDA1 L/R Source / / MX-29 [1:0] */
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	955	static const char * const rt5677_adda1_src[] = {
				956	"STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
				957	};
				958
				959	static SOC_ENUM_SINGLE_DECL(
				960	rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
				961	RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
				962
				963	static const struct snd_kcontrol_new rt5677_adda1_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	964	SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	965
				966
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	967	/DAC2 L/R Source/ /* MX-1B [6:4] [2:0] */
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	968	static const char * const rt5677_dac2l_src[] = {
				969	"IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
				970	"OB 2",
				971	};
				972
				973	static SOC_ENUM_SINGLE_DECL(
				974	rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
				975	RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
				976
				977	static const struct snd_kcontrol_new rt5677_dac2_l_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	978	SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	979
				980	static const char * const rt5677_dac2r_src[] = {
				981	"IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
				982	"OB 3", "Haptic Generator", "VAD ADC"
				983	};
				984
				985	static SOC_ENUM_SINGLE_DECL(
				986	rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
				987	RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
				988
				989	static const struct snd_kcontrol_new rt5677_dac2_r_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	990	SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	991
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	992	/DAC3 L/R Source/ /* MX-16 [6:4] [2:0] */
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	993	static const char * const rt5677_dac3l_src[] = {
				994	"IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
				995	"SLB DAC 4", "OB 4"
				996	};
				997
				998	static SOC_ENUM_SINGLE_DECL(
				999	rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
				1000	RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
				1001
				1002	static const struct snd_kcontrol_new rt5677_dac3_l_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1003	SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1004
				1005	static const char * const rt5677_dac3r_src[] = {
				1006	"IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
				1007	"SLB DAC 5", "OB 5"
				1008	};
				1009
				1010	static SOC_ENUM_SINGLE_DECL(
				1011	rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
				1012	RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
				1013
				1014	static const struct snd_kcontrol_new rt5677_dac3_r_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1015	SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1016
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1017	/DAC4 L/R Source/ /* MX-16 [14:12] [10:8] */
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1018	static const char * const rt5677_dac4l_src[] = {
				1019	"IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
				1020	"SLB DAC 6", "OB 6"
				1021	};
				1022
				1023	static SOC_ENUM_SINGLE_DECL(
				1024	rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
				1025	RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
				1026
				1027	static const struct snd_kcontrol_new rt5677_dac4_l_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1028	SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1029
				1030	static const char * const rt5677_dac4r_src[] = {
				1031	"IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
				1032	"SLB DAC 7", "OB 7"
				1033	};
				1034
				1035	static SOC_ENUM_SINGLE_DECL(
				1036	rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
				1037	RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
				1038
				1039	static const struct snd_kcontrol_new rt5677_dac4_r_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1040	SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1041
				1042	/* In/OutBound Source Pass SRC / / MX-A5 [3] [4] [0] [1] [2] */
				1043	static const char * const rt5677_iob_bypass_src[] = {
				1044	"Bypass", "Pass SRC"
				1045	};
				1046
				1047	static SOC_ENUM_SINGLE_DECL(
				1048	rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
				1049	RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
				1050
				1051	static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1052	SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1053
				1054	static SOC_ENUM_SINGLE_DECL(
				1055	rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
				1056	RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
				1057
				1058	static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1059	SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1060
				1061	static SOC_ENUM_SINGLE_DECL(
				1062	rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
				1063	RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
				1064
				1065	static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1066	SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1067
				1068	static SOC_ENUM_SINGLE_DECL(
				1069	rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
				1070	RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
				1071
				1072	static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1073	SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1074
				1075	static SOC_ENUM_SINGLE_DECL(
				1076	rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
				1077	RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
				1078
				1079	static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1080	SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1081
				1082	/* Stereo ADC Source 2 / / MX-27 MX26 MX25 [11:10] */
				1083	static const char * const rt5677_stereo_adc2_src[] = {
				1084	"DD MIX1", "DMIC", "Stereo DAC MIX"
				1085	};
				1086
				1087	static SOC_ENUM_SINGLE_DECL(
				1088	rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
				1089	RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
				1090
				1091	static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1092	SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1093
				1094	static SOC_ENUM_SINGLE_DECL(
				1095	rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
				1096	RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
				1097
				1098	static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1099	SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1100
				1101	static SOC_ENUM_SINGLE_DECL(
				1102	rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
				1103	RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
				1104
				1105	static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1106	SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1107
				1108	/* DMIC Source / / MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
				1109	static const char * const rt5677_dmic_src[] = {
				1110	"DMIC1", "DMIC2", "DMIC3", "DMIC4"
				1111	};
				1112
				1113	static SOC_ENUM_SINGLE_DECL(
				1114	rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
				1115	RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
				1116
				1117	static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1118	SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1119
				1120	static SOC_ENUM_SINGLE_DECL(
				1121	rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
				1122	RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
				1123
				1124	static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1125	SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1126
				1127	static SOC_ENUM_SINGLE_DECL(
				1128	rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
				1129	RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
				1130
				1131	static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1132	SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1133
				1134	static SOC_ENUM_SINGLE_DECL(
				1135	rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
				1136	RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
				1137
				1138	static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1139	SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1140
				1141	static SOC_ENUM_SINGLE_DECL(
				1142	rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
				1143	RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
				1144
				1145	static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1146	SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1147
				1148	static SOC_ENUM_SINGLE_DECL(
				1149	rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
				1150	RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
				1151
				1152	static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1153	SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1154
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1155	/* Stereo2 ADC Source / / MX-26 [0] */
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1156	static const char * const rt5677_stereo2_adc_lr_src[] = {
				1157	"L", "LR"
				1158	};
				1159
				1160	static SOC_ENUM_SINGLE_DECL(
				1161	rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
				1162	RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
				1163
				1164	static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1165	SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1166
				1167	/* Stereo1 ADC Source 1 / / MX-27 MX26 MX25 [13:12] */
				1168	static const char * const rt5677_stereo_adc1_src[] = {
				1169	"DD MIX1", "ADC1/2", "Stereo DAC MIX"
				1170	};
				1171
				1172	static SOC_ENUM_SINGLE_DECL(
				1173	rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
				1174	RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
				1175
				1176	static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1177	SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1178
				1179	static SOC_ENUM_SINGLE_DECL(
				1180	rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
				1181	RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
				1182
				1183	static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1184	SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1185
				1186	static SOC_ENUM_SINGLE_DECL(
				1187	rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
				1188	RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
				1189
				1190	static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1191	SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1192
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1193	/* Mono ADC Left Source 2 / / MX-28 [11:10] */
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1194	static const char * const rt5677_mono_adc2_l_src[] = {
				1195	"DD MIX1L", "DMIC", "MONO DAC MIXL"
				1196	};
				1197
				1198	static SOC_ENUM_SINGLE_DECL(
				1199	rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
				1200	RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
				1201
				1202	static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1203	SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1204
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1205	/* Mono ADC Left Source 1 / / MX-28 [13:12] */
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1206	static const char * const rt5677_mono_adc1_l_src[] = {
				1207	"DD MIX1L", "ADC1", "MONO DAC MIXL"
				1208	};
				1209
				1210	static SOC_ENUM_SINGLE_DECL(
				1211	rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
				1212	RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
				1213
				1214	static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1215	SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1216
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1217	/* Mono ADC Right Source 2 / / MX-28 [3:2] */
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1218	static const char * const rt5677_mono_adc2_r_src[] = {
				1219	"DD MIX1R", "DMIC", "MONO DAC MIXR"
				1220	};
				1221
				1222	static SOC_ENUM_SINGLE_DECL(
				1223	rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
				1224	RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
				1225
				1226	static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1227	SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1228
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1229	/* Mono ADC Right Source 1 / / MX-28 [5:4] */
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1230	static const char * const rt5677_mono_adc1_r_src[] = {
				1231	"DD MIX1R", "ADC2", "MONO DAC MIXR"
				1232	};
				1233
				1234	static SOC_ENUM_SINGLE_DECL(
				1235	rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
				1236	RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
				1237
				1238	static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1239	SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1240
				1241	/* Stereo4 ADC Source 2 / / MX-24 [11:10] */
				1242	static const char * const rt5677_stereo4_adc2_src[] = {
				1243	"DD MIX1", "DMIC", "DD MIX2"
				1244	};
				1245
				1246	static SOC_ENUM_SINGLE_DECL(
				1247	rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
				1248	RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
				1249
				1250	static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1251	SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1252
				1253
				1254	/* Stereo4 ADC Source 1 / / MX-24 [13:12] */
				1255	static const char * const rt5677_stereo4_adc1_src[] = {
				1256	"DD MIX1", "ADC1/2", "DD MIX2"
				1257	};
				1258
				1259	static SOC_ENUM_SINGLE_DECL(
				1260	rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
				1261	RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
				1262
				1263	static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1264	SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1265
				1266	/* InBound0/1 Source / / MX-A3 [14:12] */
				1267	static const char * const rt5677_inbound01_src[] = {
				1268	"IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
				1269	"VAD ADC/DAC1 FS"
				1270	};
				1271
				1272	static SOC_ENUM_SINGLE_DECL(
				1273	rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
				1274	RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
				1275
				1276	static const struct snd_kcontrol_new rt5677_ib01_src_mux =
				1277	SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
				1278
				1279	/* InBound2/3 Source / / MX-A3 [10:8] */
				1280	static const char * const rt5677_inbound23_src[] = {
				1281	"IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
				1282	"DAC1 FS", "IF4 DAC"
				1283	};
				1284
				1285	static SOC_ENUM_SINGLE_DECL(
				1286	rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
				1287	RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
				1288
				1289	static const struct snd_kcontrol_new rt5677_ib23_src_mux =
				1290	SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
				1291
				1292	/* InBound4/5 Source / / MX-A3 [6:4] */
				1293	static const char * const rt5677_inbound45_src[] = {
				1294	"IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
				1295	"IF3 DAC"
				1296	};
				1297
				1298	static SOC_ENUM_SINGLE_DECL(
				1299	rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
				1300	RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
				1301
				1302	static const struct snd_kcontrol_new rt5677_ib45_src_mux =
				1303	SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
				1304
				1305	/* InBound6 Source / / MX-A3 [2:0] */
				1306	static const char * const rt5677_inbound6_src[] = {
				1307	"IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
				1308	"IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
				1309	};
				1310
				1311	static SOC_ENUM_SINGLE_DECL(
				1312	rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
				1313	RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
				1314
				1315	static const struct snd_kcontrol_new rt5677_ib6_src_mux =
				1316	SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
				1317
				1318	/* InBound7 Source / / MX-A4 [14:12] */
				1319	static const char * const rt5677_inbound7_src[] = {
				1320	"IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
				1321	"IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
				1322	};
				1323
				1324	static SOC_ENUM_SINGLE_DECL(
				1325	rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
				1326	RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
				1327
				1328	static const struct snd_kcontrol_new rt5677_ib7_src_mux =
				1329	SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
				1330
				1331	/* InBound8 Source / / MX-A4 [10:8] */
				1332	static const char * const rt5677_inbound8_src[] = {
				1333	"STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
				1334	"MONO ADC MIX L", "DACL1 FS"
				1335	};
				1336
				1337	static SOC_ENUM_SINGLE_DECL(
				1338	rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
				1339	RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
				1340
				1341	static const struct snd_kcontrol_new rt5677_ib8_src_mux =
				1342	SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
				1343
				1344	/* InBound9 Source / / MX-A4 [6:4] */
				1345	static const char * const rt5677_inbound9_src[] = {
				1346	"STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
				1347	"MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
				1348	};
				1349
				1350	static SOC_ENUM_SINGLE_DECL(
				1351	rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
				1352	RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
				1353
				1354	static const struct snd_kcontrol_new rt5677_ib9_src_mux =
				1355	SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
				1356
				1357	/* VAD Source / / MX-9F [6:4] */
				1358	static const char * const rt5677_vad_src[] = {
				1359	"STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
				1360	"STO3 ADC MIX L"
				1361	};
				1362
				1363	static SOC_ENUM_SINGLE_DECL(
				1364	rt5677_vad_enum, RT5677_VAD_CTRL4,
				1365	RT5677_VAD_SRC_SFT, rt5677_vad_src);
				1366
				1367	static const struct snd_kcontrol_new rt5677_vad_src_mux =
				1368	SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
				1369
				1370	/* Sidetone Source / / MX-13 [11:9] */
				1371	static const char * const rt5677_sidetone_src[] = {
				1372	"DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
				1373	};
				1374
				1375	static SOC_ENUM_SINGLE_DECL(
				1376	rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
				1377	RT5677_ST_SEL_SFT, rt5677_sidetone_src);
				1378
				1379	static const struct snd_kcontrol_new rt5677_sidetone_mux =
				1380	SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
				1381
				1382	/* DAC1/2 Source / / MX-15 [1:0] */
				1383	static const char * const rt5677_dac12_src[] = {
				1384	"STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
				1385	};
				1386
				1387	static SOC_ENUM_SINGLE_DECL(
				1388	rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
				1389	RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
				1390
				1391	static const struct snd_kcontrol_new rt5677_dac12_mux =
				1392	SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
				1393
				1394	/* DAC3 Source / / MX-15 [5:4] */
				1395	static const char * const rt5677_dac3_src[] = {
				1396	"MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
				1397	};
				1398
				1399	static SOC_ENUM_SINGLE_DECL(
				1400	rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
				1401	RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
				1402
				1403	static const struct snd_kcontrol_new rt5677_dac3_mux =
				1404	SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
				1405
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1406	/* PDM channel Source / / MX-31 [13:12][9:8][5:4][1:0] */
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1407	static const char * const rt5677_pdm_src[] = {
				1408	"STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
				1409	};
				1410
				1411	static SOC_ENUM_SINGLE_DECL(
				1412	rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
				1413	RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
				1414
				1415	static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1416	SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1417
				1418	static SOC_ENUM_SINGLE_DECL(
				1419	rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
				1420	RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
				1421
				1422	static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1423	SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1424
				1425	static SOC_ENUM_SINGLE_DECL(
				1426	rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
				1427	RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
				1428
				1429	static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1430	SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1431
				1432	static SOC_ENUM_SINGLE_DECL(
				1433	rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
				1434	RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
				1435
				1436	static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1437	SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1438
				1439	/* TDM IF1/2 SLB ADC1 Data Selection / / MX-3C MX-41 [5:4] MX-08 [1:0]*/
				1440	static const char * const rt5677_if12_adc1_src[] = {
				1441	"STO1 ADC MIX", "OB01", "VAD ADC"
				1442	};
				1443
				1444	static SOC_ENUM_SINGLE_DECL(
				1445	rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
				1446	RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
				1447
				1448	static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1449	SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1450
				1451	static SOC_ENUM_SINGLE_DECL(
				1452	rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
				1453	RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
				1454
				1455	static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1456	SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1457
				1458	static SOC_ENUM_SINGLE_DECL(
				1459	rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
				1460	RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
				1461
				1462	static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1463	SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1464
				1465	/* TDM IF1/2 SLB ADC2 Data Selection / / MX-3C MX-41 [7:6] MX-08 [3:2] */
				1466	static const char * const rt5677_if12_adc2_src[] = {
				1467	"STO2 ADC MIX", "OB23"
				1468	};
				1469
				1470	static SOC_ENUM_SINGLE_DECL(
				1471	rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
				1472	RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
				1473
				1474	static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1475	SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1476
				1477	static SOC_ENUM_SINGLE_DECL(
				1478	rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
				1479	RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
				1480
				1481	static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1482	SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1483
				1484	static SOC_ENUM_SINGLE_DECL(
				1485	rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
				1486	RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
				1487
				1488	static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1489	SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1490
				1491	/* TDM IF1/2 SLB ADC3 Data Selection / / MX-3C MX-41 [9:8] MX-08 [5:4] */
				1492	static const char * const rt5677_if12_adc3_src[] = {
				1493	"STO3 ADC MIX", "MONO ADC MIX", "OB45"
				1494	};
				1495
				1496	static SOC_ENUM_SINGLE_DECL(
				1497	rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
				1498	RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
				1499
				1500	static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1501	SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1502
				1503	static SOC_ENUM_SINGLE_DECL(
				1504	rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
				1505	RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
				1506
				1507	static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1508	SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1509
				1510	static SOC_ENUM_SINGLE_DECL(
				1511	rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
				1512	RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
				1513
				1514	static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1515	SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1516
				1517	/* TDM IF1/2 SLB ADC4 Data Selection / / MX-3C MX-41 [11:10] MX-08 [7:6] */
				1518	static const char * const rt5677_if12_adc4_src[] = {
				1519	"STO4 ADC MIX", "OB67", "OB01"
				1520	};
				1521
				1522	static SOC_ENUM_SINGLE_DECL(
				1523	rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
				1524	RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
				1525
				1526	static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1527	SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1528
				1529	static SOC_ENUM_SINGLE_DECL(
				1530	rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
				1531	RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
				1532
				1533	static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1534	SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1535
				1536	static SOC_ENUM_SINGLE_DECL(
				1537	rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
				1538	RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
				1539
				1540	static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1541	SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1542
				1543	/* Interface3/4 ADC Data Input / / MX-2F [3:0] MX-30 [7:4]*/
				1544	static const char * const rt5677_if34_adc_src[] = {
				1545	"STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
				1546	"MONO ADC MIX", "OB01", "OB23", "VAD ADC"
				1547	};
				1548
				1549	static SOC_ENUM_SINGLE_DECL(
				1550	rt5677_if3_adc_enum, RT5677_IF3_DATA,
				1551	RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
				1552
				1553	static const struct snd_kcontrol_new rt5677_if3_adc_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1554	SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1555
				1556	static SOC_ENUM_SINGLE_DECL(
				1557	rt5677_if4_adc_enum, RT5677_IF4_DATA,
				1558	RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
				1559
				1560	static const struct snd_kcontrol_new rt5677_if4_adc_mux =
Oder Chiou	1b7fd76	2014-06-10 14:35:24 +0800	[diff] [blame]	1561	SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1562
				1563	static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
				1564	struct snd_kcontrol *kcontrol, int event)
				1565	{
				1566	struct snd_soc_codec *codec = w->codec;
				1567	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
				1568
				1569	switch (event) {
				1570	case SND_SOC_DAPM_POST_PMU:
				1571	regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
				1572	RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
				1573	break;
				1574
				1575	case SND_SOC_DAPM_PRE_PMD:
				1576	regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
				1577	RT5677_PWR_BST1_P, 0);
				1578	break;
				1579
				1580	default:
				1581	return 0;
				1582	}
				1583
				1584	return 0;
				1585	}
				1586
				1587	static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
				1588	struct snd_kcontrol *kcontrol, int event)
				1589	{
				1590	struct snd_soc_codec *codec = w->codec;
				1591	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
				1592
				1593	switch (event) {
				1594	case SND_SOC_DAPM_POST_PMU:
				1595	regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
				1596	RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
				1597	break;
				1598
				1599	case SND_SOC_DAPM_PRE_PMD:
				1600	regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
				1601	RT5677_PWR_BST2_P, 0);
				1602	break;
				1603
				1604	default:
				1605	return 0;
				1606	}
				1607
				1608	return 0;
				1609	}
				1610
				1611	static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
				1612	struct snd_kcontrol *kcontrol, int event)
				1613	{
				1614	struct snd_soc_codec *codec = w->codec;
				1615	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
				1616
				1617	switch (event) {
				1618	case SND_SOC_DAPM_POST_PMU:
				1619	regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
				1620	regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
				1621	break;
				1622	default:
				1623	return 0;
				1624	}
				1625
				1626	return 0;
				1627	}
				1628
				1629	static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
				1630	struct snd_kcontrol *kcontrol, int event)
				1631	{
				1632	struct snd_soc_codec *codec = w->codec;
				1633	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
				1634
				1635	switch (event) {
				1636	case SND_SOC_DAPM_POST_PMU:
				1637	regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
				1638	regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
				1639	break;
				1640	default:
				1641	return 0;
				1642	}
				1643
				1644	return 0;
				1645	}
				1646
				1647	static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
				1648	struct snd_kcontrol *kcontrol, int event)
				1649	{
				1650	struct snd_soc_codec *codec = w->codec;
				1651	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
				1652
				1653	switch (event) {
				1654	case SND_SOC_DAPM_POST_PMU:
				1655	regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
				1656	RT5677_PWR_CLK_MB1 \| RT5677_PWR_PP_MB1 \|
				1657	RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 \|
				1658	RT5677_PWR_PP_MB1 \| RT5677_PWR_CLK_MB);
				1659	break;
Oder Chiou	f58c3b9	2014-06-10 14:35:26 +0800	[diff] [blame]	1660
				1661	case SND_SOC_DAPM_PRE_PMD:
				1662	regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
				1663	RT5677_PWR_CLK_MB1 \| RT5677_PWR_PP_MB1 \|
				1664	RT5677_PWR_CLK_MB, 0);
				1665	break;
				1666
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1667	default:
				1668	return 0;
				1669	}
				1670
				1671	return 0;
				1672	}
				1673
				1674	static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
				1675	SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
				1676	0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
				1677	SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
				1678	0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
				1679
				1680	/* Input Side */
				1681	/* micbias */
Oder Chiou	3d0c03d	2014-06-10 14:35:23 +0800	[diff] [blame]	1682	SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
Oder Chiou	f58c3b9	2014-06-10 14:35:26 +0800	[diff] [blame]	1683	0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD \|
				1684	SND_SOC_DAPM_POST_PMU),
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	1685
				1686	/* Input Lines */
				1687	SND_SOC_DAPM_INPUT("DMIC L1"),
				1688	SND_SOC_DAPM_INPUT("DMIC R1"),
				1689	SND_SOC_DAPM_INPUT("DMIC L2"),
				1690	SND_SOC_DAPM_INPUT("DMIC R2"),
				1691	SND_SOC_DAPM_INPUT("DMIC L3"),
				1692	SND_SOC_DAPM_INPUT("DMIC R3"),
				1693	SND_SOC_DAPM_INPUT("DMIC L4"),
				1694	SND_SOC_DAPM_INPUT("DMIC R4"),
				1695
				1696	SND_SOC_DAPM_INPUT("IN1P"),
				1697	SND_SOC_DAPM_INPUT("IN1N"),
				1698	SND_SOC_DAPM_INPUT("IN2P"),
				1699	SND_SOC_DAPM_INPUT("IN2N"),
				1700
				1701	SND_SOC_DAPM_INPUT("Haptic Generator"),
				1702
				1703	SND_SOC_DAPM_PGA("DMIC1", RT5677_DMIC_CTRL1, RT5677_DMIC_1_EN_SFT, 0,
				1704	NULL, 0),
				1705	SND_SOC_DAPM_PGA("DMIC2", RT5677_DMIC_CTRL1, RT5677_DMIC_2_EN_SFT, 0,
				1706	NULL, 0),
				1707	SND_SOC_DAPM_PGA("DMIC3", RT5677_DMIC_CTRL1, RT5677_DMIC_3_EN_SFT, 0,
				1708	NULL, 0),
				1709	SND_SOC_DAPM_PGA("DMIC4", RT5677_DMIC_CTRL2, RT5677_DMIC_4_EN_SFT, 0,
				1710	NULL, 0),
				1711
				1712	SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
				1713	set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
				1714
				1715	/* Boost */
				1716	SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
				1717	RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
				1718	SND_SOC_DAPM_PRE_PMD \| SND_SOC_DAPM_POST_PMU),
				1719	SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
				1720	RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
				1721	SND_SOC_DAPM_PRE_PMD \| SND_SOC_DAPM_POST_PMU),
				1722
				1723	/* ADCs */
				1724	SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
				1725	0, 0),
				1726	SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
				1727	0, 0),
				1728	SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
				1729
				1730	SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
				1731	RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
				1732	SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
				1733	RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
				1734	SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
				1735	RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
				1736	SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
				1737	RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
				1738
				1739	/* ADC Mux */
				1740	SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
				1741	&rt5677_sto1_dmic_mux),
				1742	SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
				1743	&rt5677_sto1_adc1_mux),
				1744	SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
				1745	&rt5677_sto1_adc2_mux),
				1746	SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
				1747	&rt5677_sto2_dmic_mux),
				1748	SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
				1749	&rt5677_sto2_adc1_mux),
				1750	SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
				1751	&rt5677_sto2_adc2_mux),
				1752	SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
				1753	&rt5677_sto2_adc_lr_mux),
				1754	SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
				1755	&rt5677_sto3_dmic_mux),
				1756	SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
				1757	&rt5677_sto3_adc1_mux),
				1758	SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
				1759	&rt5677_sto3_adc2_mux),
				1760	SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
				1761	&rt5677_sto4_dmic_mux),
				1762	SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
				1763	&rt5677_sto4_adc1_mux),
				1764	SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
				1765	&rt5677_sto4_adc2_mux),
				1766	SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
				1767	&rt5677_mono_dmic_l_mux),
				1768	SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
				1769	&rt5677_mono_dmic_r_mux),
				1770	SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
				1771	&rt5677_mono_adc2_l_mux),
				1772	SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
				1773	&rt5677_mono_adc1_l_mux),
				1774	SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
				1775	&rt5677_mono_adc1_r_mux),
				1776	SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
				1777	&rt5677_mono_adc2_r_mux),
				1778
				1779	/* ADC Mixer */
				1780	SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
				1781	RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
				1782	SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
				1783	RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
				1784	SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
				1785	RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
				1786	SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
				1787	RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
				1788	SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
				1789	rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
				1790	SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
				1791	rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
				1792	SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
				1793	rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
				1794	SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
				1795	rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
				1796	SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
				1797	rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
				1798	SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
				1799	rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
				1800	SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
				1801	rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
				1802	SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
				1803	rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
				1804	SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
				1805	RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
				1806	SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
				1807	rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
				1808	SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
				1809	RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
				1810	SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
				1811	rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
				1812
				1813	/* ADC PGA */
				1814	SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
				1815	SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
				1816	SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
				1817	SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
				1818	SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
				1819	SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
				1820	SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
				1821	SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
				1822	SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
				1823	SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
				1824	SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
				1825	SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
				1826	SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
				1827	SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
				1828	SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
				1829	SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
				1830	SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
				1831	SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
				1832
				1833	/* DSP */
				1834	SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
				1835	&rt5677_ib9_src_mux),
				1836	SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
				1837	&rt5677_ib8_src_mux),
				1838	SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
				1839	&rt5677_ib7_src_mux),
				1840	SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
				1841	&rt5677_ib6_src_mux),
				1842	SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
				1843	&rt5677_ib45_src_mux),
				1844	SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
				1845	&rt5677_ib23_src_mux),
				1846	SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
				1847	&rt5677_ib01_src_mux),
				1848	SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
				1849	&rt5677_ib45_bypass_src_mux),
				1850	SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
				1851	&rt5677_ib23_bypass_src_mux),
				1852	SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
				1853	&rt5677_ib01_bypass_src_mux),
				1854	SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
				1855	&rt5677_ob23_bypass_src_mux),
				1856	SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
				1857	&rt5677_ob01_bypass_src_mux),
				1858
				1859	SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
				1860	SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
				1861
				1862	SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
				1863	SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
				1864	SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
				1865	SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
				1866	SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
				1867	SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
				1868
				1869	/* Digital Interface */
				1870	SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
				1871	RT5677_PWR_I2S1_BIT, 0, NULL, 0),
				1872	SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
				1873	SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
				1874	SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
				1875	SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
				1876	SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
				1877	SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
				1878	SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
				1879	SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
				1880	SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
				1881	SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
				1882	SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
				1883	SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
				1884	SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
				1885	SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
				1886	SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
				1887	SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
				1888
				1889	SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
				1890	RT5677_PWR_I2S2_BIT, 0, NULL, 0),
				1891	SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
				1892	SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
				1893	SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
				1894	SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
				1895	SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
				1896	SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
				1897	SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
				1898	SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
				1899	SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
				1900	SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
				1901	SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
				1902	SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
				1903	SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
				1904	SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
				1905	SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
				1906	SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
				1907
				1908	SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
				1909	RT5677_PWR_I2S3_BIT, 0, NULL, 0),
				1910	SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
				1911	SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
				1912	SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
				1913	SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
				1914	SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
				1915	SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
				1916
				1917	SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
				1918	RT5677_PWR_I2S4_BIT, 0, NULL, 0),
				1919	SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
				1920	SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
				1921	SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
				1922	SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
				1923	SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
				1924	SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
				1925
				1926	SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
				1927	RT5677_PWR_SLB_BIT, 0, NULL, 0),
				1928	SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
				1929	SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
				1930	SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
				1931	SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
				1932	SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
				1933	SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
				1934	SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
				1935	SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
				1936	SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
				1937	SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
				1938	SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
				1939	SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
				1940	SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
				1941	SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
				1942	SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
				1943	SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
				1944
				1945	/* Digital Interface Select */
				1946	SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
				1947	&rt5677_if1_adc1_mux),
				1948	SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
				1949	&rt5677_if1_adc2_mux),
				1950	SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
				1951	&rt5677_if1_adc3_mux),
				1952	SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
				1953	&rt5677_if1_adc4_mux),
				1954	SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
				1955	&rt5677_if2_adc1_mux),
				1956	SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
				1957	&rt5677_if2_adc2_mux),
				1958	SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
				1959	&rt5677_if2_adc3_mux),
				1960	SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
				1961	&rt5677_if2_adc4_mux),
				1962	SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
				1963	&rt5677_if3_adc_mux),
				1964	SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
				1965	&rt5677_if4_adc_mux),
				1966	SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
				1967	&rt5677_slb_adc1_mux),
				1968	SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
				1969	&rt5677_slb_adc2_mux),
				1970	SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
				1971	&rt5677_slb_adc3_mux),
				1972	SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
				1973	&rt5677_slb_adc4_mux),
				1974
				1975	/* Audio Interface */
				1976	SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
				1977	SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
				1978	SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
				1979	SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
				1980	SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
				1981	SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
				1982	SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
				1983	SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
				1984	SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
				1985	SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
				1986
				1987	/* Sidetone Mux */
				1988	SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
				1989	&rt5677_sidetone_mux),
				1990	/* VAD Mux*/
				1991	SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
				1992	&rt5677_vad_src_mux),
				1993
				1994	/* Tensilica DSP */
				1995	SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
				1996	SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
				1997	rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
				1998	SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
				1999	rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
				2000	SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
				2001	rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
				2002	SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
				2003	rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
				2004	SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
				2005	rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
				2006	SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
				2007	rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
				2008
				2009	/* Output Side */
				2010	/* DAC mixer before sound effect */
				2011	SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
				2012	rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
				2013	SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
				2014	rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
				2015	SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
				2016
				2017	/* DAC Mux */
				2018	SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
				2019	&rt5677_dac1_mux),
				2020	SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
				2021	&rt5677_adda1_mux),
				2022	SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
				2023	&rt5677_dac12_mux),
				2024	SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
				2025	&rt5677_dac3_mux),
				2026
				2027	/* DAC2 channel Mux */
				2028	SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
				2029	&rt5677_dac2_l_mux),
				2030	SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
				2031	&rt5677_dac2_r_mux),
				2032
				2033	/* DAC3 channel Mux */
				2034	SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
				2035	&rt5677_dac3_l_mux),
				2036	SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
				2037	&rt5677_dac3_r_mux),
				2038
				2039	/* DAC4 channel Mux */
				2040	SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
				2041	&rt5677_dac4_l_mux),
				2042	SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
				2043	&rt5677_dac4_r_mux),
				2044
				2045	/* DAC Mixer */
				2046	SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
				2047	RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
				2048	SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2,
				2049	RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
				2050	SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2,
				2051	RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
				2052
				2053	SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
				2054	rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
				2055	SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
				2056	rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
				2057	SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
				2058	rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
				2059	SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
				2060	rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
				2061	SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
				2062	rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
				2063	SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
				2064	rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
				2065	SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
				2066	rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
				2067	SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
				2068	rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
				2069	SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
				2070	SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
				2071	SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
				2072	SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
				2073
				2074	/* DACs */
				2075	SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
				2076	RT5677_PWR_DAC1_BIT, 0),
				2077	SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
				2078	RT5677_PWR_DAC2_BIT, 0),
				2079	SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
				2080	RT5677_PWR_DAC3_BIT, 0),
				2081
				2082	/* PDM */
				2083	SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
				2084	RT5677_PWR_PDM1_BIT, 0, NULL, 0),
				2085	SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
				2086	RT5677_PWR_PDM2_BIT, 0, NULL, 0),
				2087
				2088	SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
				2089	1, &rt5677_pdm1_l_mux),
				2090	SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
				2091	1, &rt5677_pdm1_r_mux),
				2092	SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
				2093	1, &rt5677_pdm2_l_mux),
				2094	SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
				2095	1, &rt5677_pdm2_r_mux),
				2096
				2097	SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
				2098	0, NULL, 0),
				2099	SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
				2100	0, NULL, 0),
				2101	SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
				2102	0, NULL, 0),
				2103
				2104	/* Output Lines */
				2105	SND_SOC_DAPM_OUTPUT("LOUT1"),
				2106	SND_SOC_DAPM_OUTPUT("LOUT2"),
				2107	SND_SOC_DAPM_OUTPUT("LOUT3"),
				2108	SND_SOC_DAPM_OUTPUT("PDM1L"),
				2109	SND_SOC_DAPM_OUTPUT("PDM1R"),
				2110	SND_SOC_DAPM_OUTPUT("PDM2L"),
				2111	SND_SOC_DAPM_OUTPUT("PDM2R"),
				2112	};
				2113
				2114	static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
				2115	{ "DMIC1", NULL, "DMIC L1" },
				2116	{ "DMIC1", NULL, "DMIC R1" },
				2117	{ "DMIC2", NULL, "DMIC L2" },
				2118	{ "DMIC2", NULL, "DMIC R2" },
				2119	{ "DMIC3", NULL, "DMIC L3" },
				2120	{ "DMIC3", NULL, "DMIC R3" },
				2121	{ "DMIC4", NULL, "DMIC L4" },
				2122	{ "DMIC4", NULL, "DMIC R4" },
				2123
				2124	{ "DMIC L1", NULL, "DMIC CLK" },
				2125	{ "DMIC R1", NULL, "DMIC CLK" },
				2126	{ "DMIC L2", NULL, "DMIC CLK" },
				2127	{ "DMIC R2", NULL, "DMIC CLK" },
				2128	{ "DMIC L3", NULL, "DMIC CLK" },
				2129	{ "DMIC R3", NULL, "DMIC CLK" },
				2130	{ "DMIC L4", NULL, "DMIC CLK" },
				2131	{ "DMIC R4", NULL, "DMIC CLK" },
				2132
				2133	{ "BST1", NULL, "IN1P" },
				2134	{ "BST1", NULL, "IN1N" },
				2135	{ "BST2", NULL, "IN2P" },
				2136	{ "BST2", NULL, "IN2N" },
				2137
				2138	{ "IN1P", NULL, "micbias1" },
				2139	{ "IN1N", NULL, "micbias1" },
				2140	{ "IN2P", NULL, "micbias1" },
				2141	{ "IN2N", NULL, "micbias1" },
				2142
				2143	{ "ADC 1", NULL, "BST1" },
				2144	{ "ADC 1", NULL, "ADC 1 power" },
				2145	{ "ADC 1", NULL, "ADC1 clock" },
				2146	{ "ADC 2", NULL, "BST2" },
				2147	{ "ADC 2", NULL, "ADC 2 power" },
				2148	{ "ADC 2", NULL, "ADC2 clock" },
				2149
				2150	{ "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
				2151	{ "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
				2152	{ "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
				2153	{ "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
				2154
				2155	{ "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
				2156	{ "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
				2157	{ "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
				2158	{ "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
				2159
				2160	{ "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
				2161	{ "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
				2162	{ "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
				2163	{ "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
				2164
				2165	{ "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
				2166	{ "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
				2167	{ "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
				2168	{ "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
				2169
				2170	{ "Mono DMIC L Mux", "DMIC1", "DMIC1" },
				2171	{ "Mono DMIC L Mux", "DMIC2", "DMIC2" },
				2172	{ "Mono DMIC L Mux", "DMIC3", "DMIC3" },
				2173	{ "Mono DMIC L Mux", "DMIC4", "DMIC4" },
				2174
				2175	{ "Mono DMIC R Mux", "DMIC1", "DMIC1" },
				2176	{ "Mono DMIC R Mux", "DMIC2", "DMIC2" },
				2177	{ "Mono DMIC R Mux", "DMIC3", "DMIC3" },
				2178	{ "Mono DMIC R Mux", "DMIC4", "DMIC4" },
				2179
				2180	{ "ADC 1_2", NULL, "ADC 1" },
				2181	{ "ADC 1_2", NULL, "ADC 2" },
				2182
				2183	{ "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
				2184	{ "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
				2185	{ "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
				2186
				2187	{ "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
				2188	{ "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
				2189	{ "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
				2190
				2191	{ "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
				2192	{ "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
				2193	{ "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
				2194
				2195	{ "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
				2196	{ "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
				2197	{ "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
				2198
				2199	{ "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
				2200	{ "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
				2201	{ "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
				2202
				2203	{ "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
				2204	{ "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
				2205	{ "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
				2206
				2207	{ "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
				2208	{ "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
				2209	{ "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
				2210
				2211	{ "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
				2212	{ "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
				2213	{ "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
				2214
				2215	{ "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
				2216	{ "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
				2217	{ "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
				2218
				2219	{ "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
				2220	{ "Mono ADC1 L Mux", "ADC1", "ADC 1" },
				2221	{ "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
				2222
				2223	{ "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
				2224	{ "Mono ADC1 R Mux", "ADC2", "ADC 2" },
				2225	{ "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
				2226
				2227	{ "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
				2228	{ "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
				2229	{ "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
				2230
				2231	{ "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
				2232	{ "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
				2233	{ "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
				2234	{ "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
				2235
				2236	{ "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
				2237	{ "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
				2238	{ "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
				2239
				2240	{ "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
				2241	{ "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
				2242	{ "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
				2243
				2244	{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
				2245	{ "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
				2246
				2247	{ "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
				2248	{ "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
				2249	{ "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
				2250	{ "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
				2251
				2252	{ "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
				2253	{ "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
				2254
				2255	{ "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
				2256	{ "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
				2257
				2258	{ "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
				2259	{ "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
				2260	{ "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
				2261
				2262	{ "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
				2263	{ "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
				2264	{ "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
				2265
				2266	{ "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
				2267	{ "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
				2268
				2269	{ "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
				2270	{ "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
				2271	{ "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
				2272	{ "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
				2273
				2274	{ "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
				2275	{ "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
				2276	{ "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
				2277
				2278	{ "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
				2279	{ "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
				2280	{ "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
				2281
				2282	{ "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
				2283	{ "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
				2284
				2285	{ "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
				2286	{ "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
				2287	{ "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
				2288	{ "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
				2289
				2290	{ "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
				2291	{ "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
				2292	{ "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
				2293
				2294	{ "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
				2295	{ "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
				2296	{ "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
				2297
				2298	{ "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
				2299	{ "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
				2300
				2301	{ "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
				2302	{ "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
				2303	{ "Mono ADC MIXL", NULL, "adc mono left filter" },
				2304	{ "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
				2305
				2306	{ "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
				2307	{ "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
				2308	{ "Mono ADC MIXR", NULL, "adc mono right filter" },
				2309	{ "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
				2310
				2311	{ "Mono ADC MIX", NULL, "Mono ADC MIXL" },
				2312	{ "Mono ADC MIX", NULL, "Mono ADC MIXR" },
				2313
				2314	{ "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
				2315	{ "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
				2316	{ "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
				2317	{ "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
				2318	{ "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
				2319
				2320	{ "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
				2321	{ "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
				2322	{ "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
				2323
				2324	{ "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
				2325	{ "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
				2326
				2327	{ "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
				2328	{ "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
				2329	{ "IF1 ADC3 Mux", "OB45", "OB45" },
				2330
				2331	{ "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
				2332	{ "IF1 ADC4 Mux", "OB67", "OB67" },
				2333	{ "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
				2334
				2335	{ "AIF1TX", NULL, "I2S1" },
				2336	{ "AIF1TX", NULL, "IF1 ADC1 Mux" },
				2337	{ "AIF1TX", NULL, "IF1 ADC2 Mux" },
				2338	{ "AIF1TX", NULL, "IF1 ADC3 Mux" },
				2339	{ "AIF1TX", NULL, "IF1 ADC4 Mux" },
				2340
				2341	{ "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
				2342	{ "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
				2343	{ "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
				2344
				2345	{ "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
				2346	{ "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
				2347
				2348	{ "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
				2349	{ "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
				2350	{ "IF2 ADC3 Mux", "OB45", "OB45" },
				2351
				2352	{ "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
				2353	{ "IF2 ADC4 Mux", "OB67", "OB67" },
				2354	{ "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
				2355
				2356	{ "AIF2TX", NULL, "I2S2" },
				2357	{ "AIF2TX", NULL, "IF2 ADC1 Mux" },
				2358	{ "AIF2TX", NULL, "IF2 ADC2 Mux" },
				2359	{ "AIF2TX", NULL, "IF2 ADC3 Mux" },
				2360	{ "AIF2TX", NULL, "IF2 ADC4 Mux" },
				2361
				2362	{ "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
				2363	{ "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
				2364	{ "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
				2365	{ "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
				2366	{ "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
				2367	{ "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
				2368	{ "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
				2369	{ "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
				2370
				2371	{ "AIF3TX", NULL, "I2S3" },
				2372	{ "AIF3TX", NULL, "IF3 ADC Mux" },
				2373
				2374	{ "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
				2375	{ "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
				2376	{ "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
				2377	{ "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
				2378	{ "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
				2379	{ "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
				2380	{ "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
				2381	{ "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
				2382
				2383	{ "AIF4TX", NULL, "I2S4" },
				2384	{ "AIF4TX", NULL, "IF4 ADC Mux" },
				2385
				2386	{ "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
				2387	{ "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
				2388	{ "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
				2389
				2390	{ "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
				2391	{ "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
				2392
				2393	{ "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
				2394	{ "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
				2395	{ "SLB ADC3 Mux", "OB45", "OB45" },
				2396
				2397	{ "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
				2398	{ "SLB ADC4 Mux", "OB67", "OB67" },
				2399	{ "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
				2400
				2401	{ "SLBTX", NULL, "SLB" },
				2402	{ "SLBTX", NULL, "SLB ADC1 Mux" },
				2403	{ "SLBTX", NULL, "SLB ADC2 Mux" },
				2404	{ "SLBTX", NULL, "SLB ADC3 Mux" },
				2405	{ "SLBTX", NULL, "SLB ADC4 Mux" },
				2406
				2407	{ "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
				2408	{ "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
				2409	{ "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
				2410	{ "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
				2411	{ "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
				2412
				2413	{ "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
				2414	{ "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
				2415
				2416	{ "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
				2417	{ "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
				2418	{ "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
				2419	{ "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
				2420	{ "IB23 Mux", "DAC1 FS", "DAC1 FS" },
				2421	{ "IB23 Mux", "IF4 DAC", "IF4 DAC" },
				2422
				2423	{ "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
				2424	{ "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
				2425
				2426	{ "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
				2427	{ "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
				2428	{ "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
				2429	{ "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
				2430	{ "IB45 Mux", "IF3 DAC", "IF3 DAC" },
				2431
				2432	{ "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
				2433	{ "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
				2434
				2435	{ "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
				2436	{ "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
				2437	{ "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
				2438	{ "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
				2439	{ "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
				2440	{ "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
				2441	{ "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
				2442	{ "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
				2443
				2444	{ "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
				2445	{ "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
				2446	{ "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
				2447	{ "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
				2448	{ "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
				2449	{ "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
				2450	{ "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
				2451	{ "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
				2452
				2453	{ "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
				2454	{ "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
				2455	{ "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
				2456	{ "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
				2457	{ "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
				2458	{ "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
				2459
				2460	{ "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
				2461	{ "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
				2462	{ "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
				2463	{ "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
				2464	{ "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
				2465	{ "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
				2466	{ "IB9 Mux", "DAC1 FS", "DAC1 FS" },
				2467
				2468	{ "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
				2469	{ "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
				2470	{ "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
				2471	{ "OB01 MIX", "IB6 Switch", "IB6 Mux" },
				2472	{ "OB01 MIX", "IB7 Switch", "IB7 Mux" },
				2473	{ "OB01 MIX", "IB8 Switch", "IB8 Mux" },
				2474	{ "OB01 MIX", "IB9 Switch", "IB9 Mux" },
				2475
				2476	{ "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
				2477	{ "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
				2478	{ "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
				2479	{ "OB23 MIX", "IB6 Switch", "IB6 Mux" },
				2480	{ "OB23 MIX", "IB7 Switch", "IB7 Mux" },
				2481	{ "OB23 MIX", "IB8 Switch", "IB8 Mux" },
				2482	{ "OB23 MIX", "IB9 Switch", "IB9 Mux" },
				2483
				2484	{ "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
				2485	{ "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
				2486	{ "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
				2487	{ "OB4 MIX", "IB6 Switch", "IB6 Mux" },
				2488	{ "OB4 MIX", "IB7 Switch", "IB7 Mux" },
				2489	{ "OB4 MIX", "IB8 Switch", "IB8 Mux" },
				2490	{ "OB4 MIX", "IB9 Switch", "IB9 Mux" },
				2491
				2492	{ "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
				2493	{ "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
				2494	{ "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
				2495	{ "OB5 MIX", "IB6 Switch", "IB6 Mux" },
				2496	{ "OB5 MIX", "IB7 Switch", "IB7 Mux" },
				2497	{ "OB5 MIX", "IB8 Switch", "IB8 Mux" },
				2498	{ "OB5 MIX", "IB9 Switch", "IB9 Mux" },
				2499
				2500	{ "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
				2501	{ "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
				2502	{ "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
				2503	{ "OB6 MIX", "IB6 Switch", "IB6 Mux" },
				2504	{ "OB6 MIX", "IB7 Switch", "IB7 Mux" },
				2505	{ "OB6 MIX", "IB8 Switch", "IB8 Mux" },
				2506	{ "OB6 MIX", "IB9 Switch", "IB9 Mux" },
				2507
				2508	{ "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
				2509	{ "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
				2510	{ "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
				2511	{ "OB7 MIX", "IB6 Switch", "IB6 Mux" },
				2512	{ "OB7 MIX", "IB7 Switch", "IB7 Mux" },
				2513	{ "OB7 MIX", "IB8 Switch", "IB8 Mux" },
				2514	{ "OB7 MIX", "IB9 Switch", "IB9 Mux" },
				2515
				2516	{ "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
				2517	{ "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
				2518	{ "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
				2519	{ "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
				2520
				2521	{ "OutBound2", NULL, "OB23 Bypass Mux" },
				2522	{ "OutBound3", NULL, "OB23 Bypass Mux" },
				2523	{ "OutBound4", NULL, "OB4 MIX" },
				2524	{ "OutBound5", NULL, "OB5 MIX" },
				2525	{ "OutBound6", NULL, "OB6 MIX" },
				2526	{ "OutBound7", NULL, "OB7 MIX" },
				2527
				2528	{ "OB45", NULL, "OutBound4" },
				2529	{ "OB45", NULL, "OutBound5" },
				2530	{ "OB67", NULL, "OutBound6" },
				2531	{ "OB67", NULL, "OutBound7" },
				2532
				2533	{ "IF1 DAC0", NULL, "AIF1RX" },
				2534	{ "IF1 DAC1", NULL, "AIF1RX" },
				2535	{ "IF1 DAC2", NULL, "AIF1RX" },
				2536	{ "IF1 DAC3", NULL, "AIF1RX" },
				2537	{ "IF1 DAC4", NULL, "AIF1RX" },
				2538	{ "IF1 DAC5", NULL, "AIF1RX" },
				2539	{ "IF1 DAC6", NULL, "AIF1RX" },
				2540	{ "IF1 DAC7", NULL, "AIF1RX" },
				2541	{ "IF1 DAC0", NULL, "I2S1" },
				2542	{ "IF1 DAC1", NULL, "I2S1" },
				2543	{ "IF1 DAC2", NULL, "I2S1" },
				2544	{ "IF1 DAC3", NULL, "I2S1" },
				2545	{ "IF1 DAC4", NULL, "I2S1" },
				2546	{ "IF1 DAC5", NULL, "I2S1" },
				2547	{ "IF1 DAC6", NULL, "I2S1" },
				2548	{ "IF1 DAC7", NULL, "I2S1" },
				2549
				2550	{ "IF1 DAC01", NULL, "IF1 DAC0" },
				2551	{ "IF1 DAC01", NULL, "IF1 DAC1" },
				2552	{ "IF1 DAC23", NULL, "IF1 DAC2" },
				2553	{ "IF1 DAC23", NULL, "IF1 DAC3" },
				2554	{ "IF1 DAC45", NULL, "IF1 DAC4" },
				2555	{ "IF1 DAC45", NULL, "IF1 DAC5" },
				2556	{ "IF1 DAC67", NULL, "IF1 DAC6" },
				2557	{ "IF1 DAC67", NULL, "IF1 DAC7" },
				2558
				2559	{ "IF2 DAC0", NULL, "AIF2RX" },
				2560	{ "IF2 DAC1", NULL, "AIF2RX" },
				2561	{ "IF2 DAC2", NULL, "AIF2RX" },
				2562	{ "IF2 DAC3", NULL, "AIF2RX" },
				2563	{ "IF2 DAC4", NULL, "AIF2RX" },
				2564	{ "IF2 DAC5", NULL, "AIF2RX" },
				2565	{ "IF2 DAC6", NULL, "AIF2RX" },
				2566	{ "IF2 DAC7", NULL, "AIF2RX" },
				2567	{ "IF2 DAC0", NULL, "I2S2" },
				2568	{ "IF2 DAC1", NULL, "I2S2" },
				2569	{ "IF2 DAC2", NULL, "I2S2" },
				2570	{ "IF2 DAC3", NULL, "I2S2" },
				2571	{ "IF2 DAC4", NULL, "I2S2" },
				2572	{ "IF2 DAC5", NULL, "I2S2" },
				2573	{ "IF2 DAC6", NULL, "I2S2" },
				2574	{ "IF2 DAC7", NULL, "I2S2" },
				2575
				2576	{ "IF2 DAC01", NULL, "IF2 DAC0" },
				2577	{ "IF2 DAC01", NULL, "IF2 DAC1" },
				2578	{ "IF2 DAC23", NULL, "IF2 DAC2" },
				2579	{ "IF2 DAC23", NULL, "IF2 DAC3" },
				2580	{ "IF2 DAC45", NULL, "IF2 DAC4" },
				2581	{ "IF2 DAC45", NULL, "IF2 DAC5" },
				2582	{ "IF2 DAC67", NULL, "IF2 DAC6" },
				2583	{ "IF2 DAC67", NULL, "IF2 DAC7" },
				2584
				2585	{ "IF3 DAC", NULL, "AIF3RX" },
				2586	{ "IF3 DAC", NULL, "I2S3" },
				2587
				2588	{ "IF4 DAC", NULL, "AIF4RX" },
				2589	{ "IF4 DAC", NULL, "I2S4" },
				2590
				2591	{ "IF3 DAC L", NULL, "IF3 DAC" },
				2592	{ "IF3 DAC R", NULL, "IF3 DAC" },
				2593
				2594	{ "IF4 DAC L", NULL, "IF4 DAC" },
				2595	{ "IF4 DAC R", NULL, "IF4 DAC" },
				2596
				2597	{ "SLB DAC0", NULL, "SLBRX" },
				2598	{ "SLB DAC1", NULL, "SLBRX" },
				2599	{ "SLB DAC2", NULL, "SLBRX" },
				2600	{ "SLB DAC3", NULL, "SLBRX" },
				2601	{ "SLB DAC4", NULL, "SLBRX" },
				2602	{ "SLB DAC5", NULL, "SLBRX" },
				2603	{ "SLB DAC6", NULL, "SLBRX" },
				2604	{ "SLB DAC7", NULL, "SLBRX" },
				2605	{ "SLB DAC0", NULL, "SLB" },
				2606	{ "SLB DAC1", NULL, "SLB" },
				2607	{ "SLB DAC2", NULL, "SLB" },
				2608	{ "SLB DAC3", NULL, "SLB" },
				2609	{ "SLB DAC4", NULL, "SLB" },
				2610	{ "SLB DAC5", NULL, "SLB" },
				2611	{ "SLB DAC6", NULL, "SLB" },
				2612	{ "SLB DAC7", NULL, "SLB" },
				2613
				2614	{ "SLB DAC01", NULL, "SLB DAC0" },
				2615	{ "SLB DAC01", NULL, "SLB DAC1" },
				2616	{ "SLB DAC23", NULL, "SLB DAC2" },
				2617	{ "SLB DAC23", NULL, "SLB DAC3" },
				2618	{ "SLB DAC45", NULL, "SLB DAC4" },
				2619	{ "SLB DAC45", NULL, "SLB DAC5" },
				2620	{ "SLB DAC67", NULL, "SLB DAC6" },
				2621	{ "SLB DAC67", NULL, "SLB DAC7" },
				2622
				2623	{ "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
				2624	{ "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
				2625	{ "ADDA1 Mux", "OB 67", "OB67" },
				2626
				2627	{ "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
				2628	{ "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
				2629	{ "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
				2630	{ "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
				2631	{ "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
				2632	{ "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
				2633
				2634	{ "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
				2635	{ "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
				2636	{ "DAC1 MIXL", NULL, "dac stereo1 filter" },
				2637	{ "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
				2638	{ "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
				2639	{ "DAC1 MIXR", NULL, "dac stereo1 filter" },
				2640
				2641	{ "DAC1 FS", NULL, "DAC1 MIXL" },
				2642	{ "DAC1 FS", NULL, "DAC1 MIXR" },
				2643
				2644	{ "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
				2645	{ "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
				2646	{ "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
				2647	{ "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
				2648	{ "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
				2649	{ "DAC2 L Mux", "OB 2", "OutBound2" },
				2650
				2651	{ "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
				2652	{ "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
				2653	{ "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
				2654	{ "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
				2655	{ "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
				2656	{ "DAC2 R Mux", "OB 3", "OutBound3" },
				2657	{ "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
				2658	{ "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
				2659
				2660	{ "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
				2661	{ "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
				2662	{ "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
				2663	{ "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
				2664	{ "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
				2665	{ "DAC3 L Mux", "OB 4", "OutBound4" },
				2666
				2667	{ "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
				2668	{ "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
				2669	{ "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
				2670	{ "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
				2671	{ "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
				2672	{ "DAC3 R Mux", "OB 5", "OutBound5" },
				2673
				2674	{ "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
				2675	{ "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
				2676	{ "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
				2677	{ "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
				2678	{ "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
				2679	{ "DAC4 L Mux", "OB 6", "OutBound6" },
				2680
				2681	{ "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
				2682	{ "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
				2683	{ "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
				2684	{ "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
				2685	{ "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
				2686	{ "DAC4 R Mux", "OB 7", "OutBound7" },
				2687
				2688	{ "Sidetone Mux", "DMIC1 L", "DMIC L1" },
				2689	{ "Sidetone Mux", "DMIC2 L", "DMIC L2" },
				2690	{ "Sidetone Mux", "DMIC3 L", "DMIC L3" },
				2691	{ "Sidetone Mux", "DMIC4 L", "DMIC L4" },
				2692	{ "Sidetone Mux", "ADC1", "ADC 1" },
				2693	{ "Sidetone Mux", "ADC2", "ADC 2" },
				2694
				2695	{ "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
				2696	{ "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
				2697	{ "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
				2698	{ "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
				2699	{ "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
				2700	{ "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
				2701	{ "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
				2702	{ "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
				2703	{ "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
				2704	{ "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
				2705
				2706	{ "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
				2707	{ "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
				2708	{ "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
				2709	{ "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
				2710	{ "Mono DAC MIXL", NULL, "dac mono left filter" },
				2711	{ "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
				2712	{ "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
				2713	{ "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
				2714	{ "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
				2715	{ "Mono DAC MIXR", NULL, "dac mono right filter" },
				2716
				2717	{ "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
				2718	{ "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
				2719	{ "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
				2720	{ "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
				2721	{ "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
				2722	{ "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
				2723	{ "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
				2724	{ "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
				2725
				2726	{ "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
				2727	{ "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
				2728	{ "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
				2729	{ "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
				2730	{ "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
				2731	{ "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
				2732	{ "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
				2733	{ "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
				2734
				2735	{ "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
				2736	{ "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
				2737	{ "Mono DAC MIX", NULL, "Mono DAC MIXL" },
				2738	{ "Mono DAC MIX", NULL, "Mono DAC MIXR" },
				2739	{ "DD1 MIX", NULL, "DD1 MIXL" },
				2740	{ "DD1 MIX", NULL, "DD1 MIXR" },
				2741	{ "DD2 MIX", NULL, "DD2 MIXL" },
				2742	{ "DD2 MIX", NULL, "DD2 MIXR" },
				2743
				2744	{ "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
				2745	{ "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
				2746	{ "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
				2747	{ "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
				2748
				2749	{ "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
				2750	{ "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
				2751	{ "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
				2752	{ "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
				2753
				2754	{ "DAC 1", NULL, "DAC12 SRC Mux" },
				2755	{ "DAC 1", NULL, "PLL1", is_sys_clk_from_pll },
				2756	{ "DAC 2", NULL, "DAC12 SRC Mux" },
				2757	{ "DAC 2", NULL, "PLL1", is_sys_clk_from_pll },
				2758	{ "DAC 3", NULL, "DAC3 SRC Mux" },
				2759	{ "DAC 3", NULL, "PLL1", is_sys_clk_from_pll },
				2760
				2761	{ "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
				2762	{ "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
				2763	{ "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
				2764	{ "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
				2765	{ "PDM1 L Mux", NULL, "PDM1 Power" },
				2766	{ "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
				2767	{ "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
				2768	{ "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
				2769	{ "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
				2770	{ "PDM1 R Mux", NULL, "PDM1 Power" },
				2771	{ "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
				2772	{ "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
				2773	{ "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
				2774	{ "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
				2775	{ "PDM2 L Mux", NULL, "PDM2 Power" },
				2776	{ "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
				2777	{ "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
				2778	{ "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
				2779	{ "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
				2780	{ "PDM2 R Mux", NULL, "PDM2 Power" },
				2781
				2782	{ "LOUT1 amp", NULL, "DAC 1" },
				2783	{ "LOUT2 amp", NULL, "DAC 2" },
				2784	{ "LOUT3 amp", NULL, "DAC 3" },
				2785
				2786	{ "LOUT1", NULL, "LOUT1 amp" },
				2787	{ "LOUT2", NULL, "LOUT2 amp" },
				2788	{ "LOUT3", NULL, "LOUT3 amp" },
				2789
				2790	{ "PDM1L", NULL, "PDM1 L Mux" },
				2791	{ "PDM1R", NULL, "PDM1 R Mux" },
				2792	{ "PDM2L", NULL, "PDM2 L Mux" },
				2793	{ "PDM2R", NULL, "PDM2 R Mux" },
				2794	};
				2795
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	2796	static int rt5677_hw_params(struct snd_pcm_substream *substream,
				2797	struct snd_pcm_hw_params params, struct snd_soc_dai dai)
				2798	{
				2799	struct snd_soc_codec *codec = dai->codec;
				2800	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
				2801	unsigned int val_len = 0, val_clk, mask_clk;
				2802	int pre_div, bclk_ms, frame_size;
				2803
				2804	rt5677->lrck[dai->id] = params_rate(params);
Axel Lin	30f14b4	2014-06-10 08:57:36 +0800	[diff] [blame]	2805	pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	2806	if (pre_div < 0) {
				2807	dev_err(codec->dev, "Unsupported clock setting\n");
				2808	return -EINVAL;
				2809	}
				2810	frame_size = snd_soc_params_to_frame_size(params);
				2811	if (frame_size < 0) {
				2812	dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
				2813	return -EINVAL;
				2814	}
				2815	bclk_ms = frame_size > 32;
				2816	rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
				2817
				2818	dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
				2819	rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
				2820	dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
				2821	bclk_ms, pre_div, dai->id);
				2822
				2823	switch (params_width(params)) {
				2824	case 16:
				2825	break;
				2826	case 20:
				2827	val_len \|= RT5677_I2S_DL_20;
				2828	break;
				2829	case 24:
				2830	val_len \|= RT5677_I2S_DL_24;
				2831	break;
				2832	case 8:
				2833	val_len \|= RT5677_I2S_DL_8;
				2834	break;
				2835	default:
				2836	return -EINVAL;
				2837	}
				2838
				2839	switch (dai->id) {
				2840	case RT5677_AIF1:
				2841	mask_clk = RT5677_I2S_PD1_MASK;
				2842	val_clk = pre_div << RT5677_I2S_PD1_SFT;
				2843	regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
				2844	RT5677_I2S_DL_MASK, val_len);
				2845	regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
				2846	mask_clk, val_clk);
				2847	break;
				2848	case RT5677_AIF2:
				2849	mask_clk = RT5677_I2S_PD2_MASK;
				2850	val_clk = pre_div << RT5677_I2S_PD2_SFT;
				2851	regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
				2852	RT5677_I2S_DL_MASK, val_len);
				2853	regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
				2854	mask_clk, val_clk);
				2855	break;
				2856	case RT5677_AIF3:
				2857	mask_clk = RT5677_I2S_BCLK_MS3_MASK \| RT5677_I2S_PD3_MASK;
				2858	val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT \|
				2859	pre_div << RT5677_I2S_PD3_SFT;
				2860	regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
				2861	RT5677_I2S_DL_MASK, val_len);
				2862	regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
				2863	mask_clk, val_clk);
				2864	break;
				2865	case RT5677_AIF4:
				2866	mask_clk = RT5677_I2S_BCLK_MS4_MASK \| RT5677_I2S_PD4_MASK;
				2867	val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT \|
				2868	pre_div << RT5677_I2S_PD4_SFT;
				2869	regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
				2870	RT5677_I2S_DL_MASK, val_len);
				2871	regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
				2872	mask_clk, val_clk);
				2873	break;
				2874	default:
				2875	break;
				2876	}
				2877
				2878	return 0;
				2879	}
				2880
				2881	static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
				2882	{
				2883	struct snd_soc_codec *codec = dai->codec;
				2884	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
				2885	unsigned int reg_val = 0;
				2886
				2887	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
				2888	case SND_SOC_DAIFMT_CBM_CFM:
				2889	rt5677->master[dai->id] = 1;
				2890	break;
				2891	case SND_SOC_DAIFMT_CBS_CFS:
				2892	reg_val \|= RT5677_I2S_MS_S;
				2893	rt5677->master[dai->id] = 0;
				2894	break;
				2895	default:
				2896	return -EINVAL;
				2897	}
				2898
				2899	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
				2900	case SND_SOC_DAIFMT_NB_NF:
				2901	break;
				2902	case SND_SOC_DAIFMT_IB_NF:
				2903	reg_val \|= RT5677_I2S_BP_INV;
				2904	break;
				2905	default:
				2906	return -EINVAL;
				2907	}
				2908
				2909	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
				2910	case SND_SOC_DAIFMT_I2S:
				2911	break;
				2912	case SND_SOC_DAIFMT_LEFT_J:
				2913	reg_val \|= RT5677_I2S_DF_LEFT;
				2914	break;
				2915	case SND_SOC_DAIFMT_DSP_A:
				2916	reg_val \|= RT5677_I2S_DF_PCM_A;
				2917	break;
				2918	case SND_SOC_DAIFMT_DSP_B:
				2919	reg_val \|= RT5677_I2S_DF_PCM_B;
				2920	break;
				2921	default:
				2922	return -EINVAL;
				2923	}
				2924
				2925	switch (dai->id) {
				2926	case RT5677_AIF1:
				2927	regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
				2928	RT5677_I2S_MS_MASK \| RT5677_I2S_BP_MASK \|
				2929	RT5677_I2S_DF_MASK, reg_val);
				2930	break;
				2931	case RT5677_AIF2:
				2932	regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
				2933	RT5677_I2S_MS_MASK \| RT5677_I2S_BP_MASK \|
				2934	RT5677_I2S_DF_MASK, reg_val);
				2935	break;
				2936	case RT5677_AIF3:
				2937	regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
				2938	RT5677_I2S_MS_MASK \| RT5677_I2S_BP_MASK \|
				2939	RT5677_I2S_DF_MASK, reg_val);
				2940	break;
				2941	case RT5677_AIF4:
				2942	regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
				2943	RT5677_I2S_MS_MASK \| RT5677_I2S_BP_MASK \|
				2944	RT5677_I2S_DF_MASK, reg_val);
				2945	break;
				2946	default:
				2947	break;
				2948	}
				2949
				2950
				2951	return 0;
				2952	}
				2953
				2954	static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
				2955	int clk_id, unsigned int freq, int dir)
				2956	{
				2957	struct snd_soc_codec *codec = dai->codec;
				2958	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
				2959	unsigned int reg_val = 0;
				2960
				2961	if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
				2962	return 0;
				2963
				2964	switch (clk_id) {
				2965	case RT5677_SCLK_S_MCLK:
				2966	reg_val \|= RT5677_SCLK_SRC_MCLK;
				2967	break;
				2968	case RT5677_SCLK_S_PLL1:
				2969	reg_val \|= RT5677_SCLK_SRC_PLL1;
				2970	break;
				2971	case RT5677_SCLK_S_RCCLK:
				2972	reg_val \|= RT5677_SCLK_SRC_RCCLK;
				2973	break;
				2974	default:
				2975	dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
				2976	return -EINVAL;
				2977	}
				2978	regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
				2979	RT5677_SCLK_SRC_MASK, reg_val);
				2980	rt5677->sysclk = freq;
				2981	rt5677->sysclk_src = clk_id;
				2982
				2983	dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
				2984
				2985	return 0;
				2986	}
				2987
				2988	/**
				2989	* rt5677_pll_calc - Calcualte PLL M/N/K code.
				2990	* @freq_in: external clock provided to codec.
				2991	* @freq_out: target clock which codec works on.
				2992	* @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
				2993	*
				2994	* Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
				2995	*
				2996	* Returns 0 for success or negative error code.
				2997	*/
				2998	static int rt5677_pll_calc(const unsigned int freq_in,
Axel Lin	099d334	2014-06-17 12:41:31 +0800	[diff] [blame]	2999	const unsigned int freq_out, struct rl6231_pll_code *pll_code)
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	3000	{
Axel Lin	099d334	2014-06-17 12:41:31 +0800	[diff] [blame]	3001	if (RT5677_PLL_INP_MIN > freq_in)
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	3002	return -EINVAL;
				3003
Axel Lin	099d334	2014-06-17 12:41:31 +0800	[diff] [blame]	3004	return rl6231_pll_calc(freq_in, freq_out, pll_code);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	3005	}
				3006
				3007	static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
				3008	unsigned int freq_in, unsigned int freq_out)
				3009	{
				3010	struct snd_soc_codec *codec = dai->codec;
				3011	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
Axel Lin	099d334	2014-06-17 12:41:31 +0800	[diff] [blame]	3012	struct rl6231_pll_code pll_code;
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	3013	int ret;
				3014
				3015	if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
				3016	freq_out == rt5677->pll_out)
				3017	return 0;
				3018
				3019	if (!freq_in \|\| !freq_out) {
				3020	dev_dbg(codec->dev, "PLL disabled\n");
				3021
				3022	rt5677->pll_in = 0;
				3023	rt5677->pll_out = 0;
				3024	regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
				3025	RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
				3026	return 0;
				3027	}
				3028
				3029	switch (source) {
				3030	case RT5677_PLL1_S_MCLK:
				3031	regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
				3032	RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
				3033	break;
				3034	case RT5677_PLL1_S_BCLK1:
				3035	case RT5677_PLL1_S_BCLK2:
				3036	case RT5677_PLL1_S_BCLK3:
				3037	case RT5677_PLL1_S_BCLK4:
				3038	switch (dai->id) {
				3039	case RT5677_AIF1:
				3040	regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
				3041	RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
				3042	break;
				3043	case RT5677_AIF2:
				3044	regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
				3045	RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
				3046	break;
				3047	case RT5677_AIF3:
				3048	regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
				3049	RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
				3050	break;
				3051	case RT5677_AIF4:
				3052	regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
				3053	RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
				3054	break;
				3055	default:
				3056	break;
				3057	}
				3058	break;
				3059	default:
				3060	dev_err(codec->dev, "Unknown PLL source %d\n", source);
				3061	return -EINVAL;
				3062	}
				3063
				3064	ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
				3065	if (ret < 0) {
				3066	dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
				3067	return ret;
				3068	}
				3069
Axel Lin	099d334	2014-06-17 12:41:31 +0800	[diff] [blame]	3070	dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
				3071	pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
				3072	pll_code.n_code, pll_code.k_code);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	3073
				3074	regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
Axel Lin	099d334	2014-06-17 12:41:31 +0800	[diff] [blame]	3075	pll_code.n_code << RT5677_PLL_N_SFT \| pll_code.k_code);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	3076	regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
				3077	(pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT \|
				3078	pll_code.m_bp << RT5677_PLL_M_BP_SFT);
				3079
				3080	rt5677->pll_in = freq_in;
				3081	rt5677->pll_out = freq_out;
				3082	rt5677->pll_src = source;
				3083
				3084	return 0;
				3085	}
				3086
				3087	static int rt5677_set_bias_level(struct snd_soc_codec *codec,
				3088	enum snd_soc_bias_level level)
				3089	{
				3090	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
				3091
				3092	switch (level) {
				3093	case SND_SOC_BIAS_ON:
				3094	break;
				3095
				3096	case SND_SOC_BIAS_PREPARE:
				3097	if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
				3098	regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
				3099	RT5677_LDO1_SEL_MASK \| RT5677_LDO2_SEL_MASK,
				3100	0x0055);
				3101	regmap_update_bits(rt5677->regmap,
				3102	RT5677_PR_BASE + RT5677_BIAS_CUR4,
				3103	0x0f00, 0x0f00);
				3104	regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
				3105	RT5677_PWR_VREF1 \| RT5677_PWR_MB \|
				3106	RT5677_PWR_BG \| RT5677_PWR_VREF2,
				3107	RT5677_PWR_VREF1 \| RT5677_PWR_MB \|
				3108	RT5677_PWR_BG \| RT5677_PWR_VREF2);
				3109	mdelay(20);
				3110	regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
				3111	RT5677_PWR_FV1 \| RT5677_PWR_FV2,
				3112	RT5677_PWR_FV1 \| RT5677_PWR_FV2);
				3113	regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
				3114	RT5677_PWR_CORE, RT5677_PWR_CORE);
				3115	regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
				3116	0x1, 0x1);
				3117	}
				3118	break;
				3119
				3120	case SND_SOC_BIAS_STANDBY:
				3121	break;
				3122
				3123	case SND_SOC_BIAS_OFF:
				3124	regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
				3125	regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
				3126	regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
Oder Chiou	f18803a	2014-07-07 15:37:00 +0800	[diff] [blame^]	3127	regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	3128	regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
				3129	regmap_update_bits(rt5677->regmap,
				3130	RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
				3131	break;
				3132
				3133	default:
				3134	break;
				3135	}
				3136	codec->dapm.bias_level = level;
				3137
				3138	return 0;
				3139	}
				3140
				3141	static int rt5677_probe(struct snd_soc_codec *codec)
				3142	{
				3143	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
				3144
				3145	rt5677->codec = codec;
				3146
				3147	rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
				3148
				3149	regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
				3150	regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
				3151
				3152	return 0;
				3153	}
				3154
				3155	static int rt5677_remove(struct snd_soc_codec *codec)
				3156	{
				3157	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
				3158
				3159	regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
				3160
				3161	return 0;
				3162	}
				3163
				3164	#ifdef CONFIG_PM
				3165	static int rt5677_suspend(struct snd_soc_codec *codec)
				3166	{
				3167	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
				3168
				3169	regcache_cache_only(rt5677->regmap, true);
				3170	regcache_mark_dirty(rt5677->regmap);
				3171
				3172	return 0;
				3173	}
				3174
				3175	static int rt5677_resume(struct snd_soc_codec *codec)
				3176	{
				3177	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
				3178
				3179	regcache_cache_only(rt5677->regmap, false);
				3180	regcache_sync(rt5677->regmap);
				3181
				3182	return 0;
				3183	}
				3184	#else
				3185	#define rt5677_suspend NULL
				3186	#define rt5677_resume NULL
				3187	#endif
				3188
				3189	#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
				3190	#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_S20_3LE \| \
				3191	SNDRV_PCM_FMTBIT_S24_LE \| SNDRV_PCM_FMTBIT_S8)
				3192
				3193	static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
				3194	.hw_params = rt5677_hw_params,
				3195	.set_fmt = rt5677_set_dai_fmt,
				3196	.set_sysclk = rt5677_set_dai_sysclk,
				3197	.set_pll = rt5677_set_dai_pll,
				3198	};
				3199
				3200	static struct snd_soc_dai_driver rt5677_dai[] = {
				3201	{
				3202	.name = "rt5677-aif1",
				3203	.id = RT5677_AIF1,
				3204	.playback = {
				3205	.stream_name = "AIF1 Playback",
				3206	.channels_min = 1,
				3207	.channels_max = 2,
				3208	.rates = RT5677_STEREO_RATES,
				3209	.formats = RT5677_FORMATS,
				3210	},
				3211	.capture = {
				3212	.stream_name = "AIF1 Capture",
				3213	.channels_min = 1,
				3214	.channels_max = 2,
				3215	.rates = RT5677_STEREO_RATES,
				3216	.formats = RT5677_FORMATS,
				3217	},
				3218	.ops = &rt5677_aif_dai_ops,
				3219	},
				3220	{
				3221	.name = "rt5677-aif2",
				3222	.id = RT5677_AIF2,
				3223	.playback = {
				3224	.stream_name = "AIF2 Playback",
				3225	.channels_min = 1,
				3226	.channels_max = 2,
				3227	.rates = RT5677_STEREO_RATES,
				3228	.formats = RT5677_FORMATS,
				3229	},
				3230	.capture = {
				3231	.stream_name = "AIF2 Capture",
				3232	.channels_min = 1,
				3233	.channels_max = 2,
				3234	.rates = RT5677_STEREO_RATES,
				3235	.formats = RT5677_FORMATS,
				3236	},
				3237	.ops = &rt5677_aif_dai_ops,
				3238	},
				3239	{
				3240	.name = "rt5677-aif3",
				3241	.id = RT5677_AIF3,
				3242	.playback = {
				3243	.stream_name = "AIF3 Playback",
				3244	.channels_min = 1,
				3245	.channels_max = 2,
				3246	.rates = RT5677_STEREO_RATES,
				3247	.formats = RT5677_FORMATS,
				3248	},
				3249	.capture = {
				3250	.stream_name = "AIF3 Capture",
				3251	.channels_min = 1,
				3252	.channels_max = 2,
				3253	.rates = RT5677_STEREO_RATES,
				3254	.formats = RT5677_FORMATS,
				3255	},
				3256	.ops = &rt5677_aif_dai_ops,
				3257	},
				3258	{
				3259	.name = "rt5677-aif4",
				3260	.id = RT5677_AIF4,
				3261	.playback = {
				3262	.stream_name = "AIF4 Playback",
				3263	.channels_min = 1,
				3264	.channels_max = 2,
				3265	.rates = RT5677_STEREO_RATES,
				3266	.formats = RT5677_FORMATS,
				3267	},
				3268	.capture = {
				3269	.stream_name = "AIF4 Capture",
				3270	.channels_min = 1,
				3271	.channels_max = 2,
				3272	.rates = RT5677_STEREO_RATES,
				3273	.formats = RT5677_FORMATS,
				3274	},
				3275	.ops = &rt5677_aif_dai_ops,
				3276	},
				3277	{
				3278	.name = "rt5677-slimbus",
				3279	.id = RT5677_AIF5,
				3280	.playback = {
				3281	.stream_name = "SLIMBus Playback",
				3282	.channels_min = 1,
				3283	.channels_max = 2,
				3284	.rates = RT5677_STEREO_RATES,
				3285	.formats = RT5677_FORMATS,
				3286	},
				3287	.capture = {
				3288	.stream_name = "SLIMBus Capture",
				3289	.channels_min = 1,
				3290	.channels_max = 2,
				3291	.rates = RT5677_STEREO_RATES,
				3292	.formats = RT5677_FORMATS,
				3293	},
				3294	.ops = &rt5677_aif_dai_ops,
				3295	},
				3296	};
				3297
				3298	static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
				3299	.probe = rt5677_probe,
				3300	.remove = rt5677_remove,
				3301	.suspend = rt5677_suspend,
				3302	.resume = rt5677_resume,
				3303	.set_bias_level = rt5677_set_bias_level,
				3304	.idle_bias_off = true,
				3305	.controls = rt5677_snd_controls,
				3306	.num_controls = ARRAY_SIZE(rt5677_snd_controls),
				3307	.dapm_widgets = rt5677_dapm_widgets,
				3308	.num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
				3309	.dapm_routes = rt5677_dapm_routes,
				3310	.num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
				3311	};
				3312
				3313	static const struct regmap_config rt5677_regmap = {
				3314	.reg_bits = 8,
				3315	.val_bits = 16,
				3316
				3317	.max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
				3318	RT5677_PR_SPACING),
				3319
				3320	.volatile_reg = rt5677_volatile_register,
				3321	.readable_reg = rt5677_readable_register,
				3322
				3323	.cache_type = REGCACHE_RBTREE,
				3324	.reg_defaults = rt5677_reg,
				3325	.num_reg_defaults = ARRAY_SIZE(rt5677_reg),
				3326	.ranges = rt5677_ranges,
				3327	.num_ranges = ARRAY_SIZE(rt5677_ranges),
				3328	};
				3329
				3330	static const struct i2c_device_id rt5677_i2c_id[] = {
				3331	{ "rt5677", 0 },
				3332	{ }
				3333	};
				3334	MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
				3335
				3336	static int rt5677_i2c_probe(struct i2c_client *i2c,
				3337	const struct i2c_device_id *id)
				3338	{
				3339	struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
				3340	struct rt5677_priv *rt5677;
				3341	int ret;
				3342	unsigned int val;
				3343
				3344	rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
				3345	GFP_KERNEL);
				3346	if (rt5677 == NULL)
				3347	return -ENOMEM;
				3348
				3349	i2c_set_clientdata(i2c, rt5677);
				3350
				3351	if (pdata)
				3352	rt5677->pdata = *pdata;
				3353
				3354	rt5677->regmap = devm_regmap_init_i2c(i2c, &rt5677_regmap);
				3355	if (IS_ERR(rt5677->regmap)) {
				3356	ret = PTR_ERR(rt5677->regmap);
				3357	dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
				3358	ret);
				3359	return ret;
				3360	}
				3361
				3362	regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
				3363	if (val != RT5677_DEVICE_ID) {
				3364	dev_err(&i2c->dev,
				3365	"Device with ID register %x is not rt5677\n", val);
				3366	return -ENODEV;
				3367	}
				3368
				3369	regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
				3370
				3371	ret = regmap_register_patch(rt5677->regmap, init_list,
				3372	ARRAY_SIZE(init_list));
				3373	if (ret != 0)
				3374	dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
				3375
				3376	if (rt5677->pdata.in1_diff)
				3377	regmap_update_bits(rt5677->regmap, RT5677_IN1,
				3378	RT5677_IN_DF1, RT5677_IN_DF1);
				3379
				3380	if (rt5677->pdata.in2_diff)
				3381	regmap_update_bits(rt5677->regmap, RT5677_IN1,
				3382	RT5677_IN_DF2, RT5677_IN_DF2);
				3383
Axel Lin	d0bdcb9	2014-06-10 11:37:24 +0800	[diff] [blame]	3384	return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
				3385	rt5677_dai, ARRAY_SIZE(rt5677_dai));
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	3386	}
				3387
				3388	static int rt5677_i2c_remove(struct i2c_client *i2c)
				3389	{
				3390	snd_soc_unregister_codec(&i2c->dev);
				3391
				3392	return 0;
				3393	}
				3394
				3395	static struct i2c_driver rt5677_i2c_driver = {
				3396	.driver = {
				3397	.name = "rt5677",
				3398	.owner = THIS_MODULE,
				3399	},
				3400	.probe = rt5677_i2c_probe,
				3401	.remove = rt5677_i2c_remove,
				3402	.id_table = rt5677_i2c_id,
				3403	};
Axel Lin	c8cfbec	2014-06-03 10:56:41 +0800	[diff] [blame]	3404	module_i2c_driver(rt5677_i2c_driver);
Oder Chiou	0e826e8	2014-05-26 20:32:33 +0800	[diff] [blame]	3405
				3406	MODULE_DESCRIPTION("ASoC RT5677 driver");
				3407	MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
				3408	MODULE_LICENSE("GPL v2");