Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2011 Linaro Ltd. |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
| 13 | /include/ "skeleton.dtsi" |
| 14 | |
| 15 | / { |
| 16 | aliases { |
Richard Zhao | 8f9ffec | 2011-12-14 09:26:45 +0800 | [diff] [blame] | 17 | serial0 = &uart1; |
| 18 | serial1 = &uart2; |
| 19 | serial2 = &uart3; |
| 20 | serial3 = &uart4; |
| 21 | serial4 = &uart5; |
Shawn Guo | 5230f8f | 2012-08-05 14:01:28 +0800 | [diff] [blame] | 22 | gpio0 = &gpio1; |
| 23 | gpio1 = &gpio2; |
| 24 | gpio2 = &gpio3; |
| 25 | gpio3 = &gpio4; |
| 26 | gpio4 = &gpio5; |
| 27 | gpio5 = &gpio6; |
| 28 | gpio6 = &gpio7; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 29 | }; |
| 30 | |
| 31 | cpus { |
| 32 | #address-cells = <1>; |
| 33 | #size-cells = <0>; |
| 34 | |
| 35 | cpu@0 { |
| 36 | compatible = "arm,cortex-a9"; |
| 37 | reg = <0>; |
| 38 | next-level-cache = <&L2>; |
Shawn Guo | d90df97 | 2012-07-19 23:16:30 +0800 | [diff] [blame] | 39 | operating-points = < |
| 40 | /* kHz uV */ |
Shawn Guo | 96574a6 | 2013-01-08 14:25:14 +0800 | [diff] [blame] | 41 | 1200000 1275000 |
| 42 | 996000 1250000 |
| 43 | 792000 1150000 |
Shawn Guo | d90df97 | 2012-07-19 23:16:30 +0800 | [diff] [blame] | 44 | 396000 950000 |
Shawn Guo | d90df97 | 2012-07-19 23:16:30 +0800 | [diff] [blame] | 45 | >; |
| 46 | clock-latency = <61036>; /* two CLK32 periods */ |
Shawn Guo | 96574a6 | 2013-01-08 14:25:14 +0800 | [diff] [blame] | 47 | clocks = <&clks 104>, <&clks 6>, <&clks 16>, |
| 48 | <&clks 17>, <&clks 170>; |
| 49 | clock-names = "arm", "pll2_pfd2_396m", "step", |
| 50 | "pll1_sw", "pll1_sys"; |
| 51 | arm-supply = <®_arm>; |
| 52 | pu-supply = <®_pu>; |
| 53 | soc-supply = <®_soc>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 54 | }; |
| 55 | |
| 56 | cpu@1 { |
| 57 | compatible = "arm,cortex-a9"; |
| 58 | reg = <1>; |
| 59 | next-level-cache = <&L2>; |
| 60 | }; |
| 61 | |
| 62 | cpu@2 { |
| 63 | compatible = "arm,cortex-a9"; |
| 64 | reg = <2>; |
| 65 | next-level-cache = <&L2>; |
| 66 | }; |
| 67 | |
| 68 | cpu@3 { |
| 69 | compatible = "arm,cortex-a9"; |
| 70 | reg = <3>; |
| 71 | next-level-cache = <&L2>; |
| 72 | }; |
| 73 | }; |
| 74 | |
| 75 | intc: interrupt-controller@00a01000 { |
| 76 | compatible = "arm,cortex-a9-gic"; |
| 77 | #interrupt-cells = <3>; |
| 78 | #address-cells = <1>; |
| 79 | #size-cells = <1>; |
| 80 | interrupt-controller; |
| 81 | reg = <0x00a01000 0x1000>, |
| 82 | <0x00a00100 0x100>; |
| 83 | }; |
| 84 | |
| 85 | clocks { |
| 86 | #address-cells = <1>; |
| 87 | #size-cells = <0>; |
| 88 | |
| 89 | ckil { |
| 90 | compatible = "fsl,imx-ckil", "fixed-clock"; |
| 91 | clock-frequency = <32768>; |
| 92 | }; |
| 93 | |
| 94 | ckih1 { |
| 95 | compatible = "fsl,imx-ckih1", "fixed-clock"; |
| 96 | clock-frequency = <0>; |
| 97 | }; |
| 98 | |
| 99 | osc { |
| 100 | compatible = "fsl,imx-osc", "fixed-clock"; |
| 101 | clock-frequency = <24000000>; |
| 102 | }; |
| 103 | }; |
| 104 | |
| 105 | soc { |
| 106 | #address-cells = <1>; |
| 107 | #size-cells = <1>; |
| 108 | compatible = "simple-bus"; |
| 109 | interrupt-parent = <&intc>; |
| 110 | ranges; |
| 111 | |
Huang Shijie | e5d0f9f | 2012-06-06 21:22:57 -0400 | [diff] [blame] | 112 | dma-apbh@00110000 { |
| 113 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
| 114 | reg = <0x00110000 0x2000>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 115 | clocks = <&clks 106>; |
Huang Shijie | e5d0f9f | 2012-06-06 21:22:57 -0400 | [diff] [blame] | 116 | }; |
| 117 | |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 118 | gpmi: gpmi-nand@00112000 { |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 119 | compatible = "fsl,imx6q-gpmi-nand"; |
| 120 | #address-cells = <1>; |
| 121 | #size-cells = <1>; |
| 122 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; |
| 123 | reg-names = "gpmi-nand", "bch"; |
| 124 | interrupts = <0 13 0x04>, <0 15 0x04>; |
| 125 | interrupt-names = "gpmi-dma", "bch"; |
| 126 | clocks = <&clks 152>, <&clks 153>, <&clks 151>, |
| 127 | <&clks 150>, <&clks 149>; |
| 128 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", |
| 129 | "gpmi_bch_apb", "per1_bch"; |
| 130 | fsl,gpmi-dma-channel = <0>; |
| 131 | status = "disabled"; |
Huang Shijie | cf922fa | 2012-07-01 23:38:46 -0400 | [diff] [blame] | 132 | }; |
| 133 | |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 134 | timer@00a00600 { |
Marc Zyngier | 58458e0 | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 135 | compatible = "arm,cortex-a9-twd-timer"; |
| 136 | reg = <0x00a00600 0x20>; |
| 137 | interrupts = <1 13 0xf01>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 138 | }; |
| 139 | |
| 140 | L2: l2-cache@00a02000 { |
| 141 | compatible = "arm,pl310-cache"; |
| 142 | reg = <0x00a02000 0x1000>; |
| 143 | interrupts = <0 92 0x04>; |
| 144 | cache-unified; |
| 145 | cache-level = <2>; |
| 146 | }; |
| 147 | |
| 148 | aips-bus@02000000 { /* AIPS1 */ |
| 149 | compatible = "fsl,aips-bus", "simple-bus"; |
| 150 | #address-cells = <1>; |
| 151 | #size-cells = <1>; |
| 152 | reg = <0x02000000 0x100000>; |
| 153 | ranges; |
| 154 | |
| 155 | spba-bus@02000000 { |
| 156 | compatible = "fsl,spba-bus", "simple-bus"; |
| 157 | #address-cells = <1>; |
| 158 | #size-cells = <1>; |
| 159 | reg = <0x02000000 0x40000>; |
| 160 | ranges; |
| 161 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 162 | spdif: spdif@02004000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 163 | reg = <0x02004000 0x4000>; |
| 164 | interrupts = <0 52 0x04>; |
| 165 | }; |
| 166 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 167 | ecspi1: ecspi@02008000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 168 | #address-cells = <1>; |
| 169 | #size-cells = <0>; |
| 170 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 171 | reg = <0x02008000 0x4000>; |
| 172 | interrupts = <0 31 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 173 | clocks = <&clks 112>, <&clks 112>; |
| 174 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 175 | status = "disabled"; |
| 176 | }; |
| 177 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 178 | ecspi2: ecspi@0200c000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 179 | #address-cells = <1>; |
| 180 | #size-cells = <0>; |
| 181 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 182 | reg = <0x0200c000 0x4000>; |
| 183 | interrupts = <0 32 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 184 | clocks = <&clks 113>, <&clks 113>; |
| 185 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 186 | status = "disabled"; |
| 187 | }; |
| 188 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 189 | ecspi3: ecspi@02010000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 190 | #address-cells = <1>; |
| 191 | #size-cells = <0>; |
| 192 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 193 | reg = <0x02010000 0x4000>; |
| 194 | interrupts = <0 33 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 195 | clocks = <&clks 114>, <&clks 114>; |
| 196 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 197 | status = "disabled"; |
| 198 | }; |
| 199 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 200 | ecspi4: ecspi@02014000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 201 | #address-cells = <1>; |
| 202 | #size-cells = <0>; |
| 203 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 204 | reg = <0x02014000 0x4000>; |
| 205 | interrupts = <0 34 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 206 | clocks = <&clks 115>, <&clks 115>; |
| 207 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 208 | status = "disabled"; |
| 209 | }; |
| 210 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 211 | ecspi5: ecspi@02018000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 212 | #address-cells = <1>; |
| 213 | #size-cells = <0>; |
| 214 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; |
| 215 | reg = <0x02018000 0x4000>; |
| 216 | interrupts = <0 35 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 217 | clocks = <&clks 116>, <&clks 116>; |
| 218 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 219 | status = "disabled"; |
| 220 | }; |
| 221 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 222 | uart1: serial@02020000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 223 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 224 | reg = <0x02020000 0x4000>; |
| 225 | interrupts = <0 26 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 226 | clocks = <&clks 160>, <&clks 161>; |
| 227 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 228 | status = "disabled"; |
| 229 | }; |
| 230 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 231 | esai: esai@02024000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 232 | reg = <0x02024000 0x4000>; |
| 233 | interrupts = <0 51 0x04>; |
| 234 | }; |
| 235 | |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 236 | ssi1: ssi@02028000 { |
| 237 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 238 | reg = <0x02028000 0x4000>; |
| 239 | interrupts = <0 46 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 240 | clocks = <&clks 178>; |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 241 | fsl,fifo-depth = <15>; |
| 242 | fsl,ssi-dma-events = <38 37>; |
| 243 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 244 | }; |
| 245 | |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 246 | ssi2: ssi@0202c000 { |
| 247 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 248 | reg = <0x0202c000 0x4000>; |
| 249 | interrupts = <0 47 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 250 | clocks = <&clks 179>; |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 251 | fsl,fifo-depth = <15>; |
| 252 | fsl,ssi-dma-events = <42 41>; |
| 253 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 254 | }; |
| 255 | |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 256 | ssi3: ssi@02030000 { |
| 257 | compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 258 | reg = <0x02030000 0x4000>; |
| 259 | interrupts = <0 48 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 260 | clocks = <&clks 180>; |
Richard Zhao | b1a5da8 | 2012-05-02 10:29:10 +0800 | [diff] [blame] | 261 | fsl,fifo-depth = <15>; |
| 262 | fsl,ssi-dma-events = <46 45>; |
| 263 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 264 | }; |
| 265 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 266 | asrc: asrc@02034000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 267 | reg = <0x02034000 0x4000>; |
| 268 | interrupts = <0 50 0x04>; |
| 269 | }; |
| 270 | |
| 271 | spba@0203c000 { |
| 272 | reg = <0x0203c000 0x4000>; |
| 273 | }; |
| 274 | }; |
| 275 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 276 | vpu: vpu@02040000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 277 | reg = <0x02040000 0x3c000>; |
| 278 | interrupts = <0 3 0x04 0 12 0x04>; |
| 279 | }; |
| 280 | |
| 281 | aipstz@0207c000 { /* AIPSTZ1 */ |
| 282 | reg = <0x0207c000 0x4000>; |
| 283 | }; |
| 284 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 285 | pwm1: pwm@02080000 { |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 286 | #pwm-cells = <2>; |
| 287 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 288 | reg = <0x02080000 0x4000>; |
| 289 | interrupts = <0 83 0x04>; |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 290 | clocks = <&clks 62>, <&clks 145>; |
| 291 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 292 | }; |
| 293 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 294 | pwm2: pwm@02084000 { |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 295 | #pwm-cells = <2>; |
| 296 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 297 | reg = <0x02084000 0x4000>; |
| 298 | interrupts = <0 84 0x04>; |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 299 | clocks = <&clks 62>, <&clks 146>; |
| 300 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 301 | }; |
| 302 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 303 | pwm3: pwm@02088000 { |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 304 | #pwm-cells = <2>; |
| 305 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 306 | reg = <0x02088000 0x4000>; |
| 307 | interrupts = <0 85 0x04>; |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 308 | clocks = <&clks 62>, <&clks 147>; |
| 309 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 310 | }; |
| 311 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 312 | pwm4: pwm@0208c000 { |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 313 | #pwm-cells = <2>; |
| 314 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 315 | reg = <0x0208c000 0x4000>; |
| 316 | interrupts = <0 86 0x04>; |
Sascha Hauer | 33b3858 | 2012-11-21 12:18:28 +0100 | [diff] [blame] | 317 | clocks = <&clks 62>, <&clks 148>; |
| 318 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 319 | }; |
| 320 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 321 | can1: flexcan@02090000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 322 | reg = <0x02090000 0x4000>; |
| 323 | interrupts = <0 110 0x04>; |
| 324 | }; |
| 325 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 326 | can2: flexcan@02094000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 327 | reg = <0x02094000 0x4000>; |
| 328 | interrupts = <0 111 0x04>; |
| 329 | }; |
| 330 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 331 | gpt: gpt@02098000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 332 | compatible = "fsl,imx6q-gpt"; |
| 333 | reg = <0x02098000 0x4000>; |
| 334 | interrupts = <0 55 0x04>; |
| 335 | }; |
| 336 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 337 | gpio1: gpio@0209c000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 338 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 339 | reg = <0x0209c000 0x4000>; |
| 340 | interrupts = <0 66 0x04 0 67 0x04>; |
| 341 | gpio-controller; |
| 342 | #gpio-cells = <2>; |
| 343 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 344 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 345 | }; |
| 346 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 347 | gpio2: gpio@020a0000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 348 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 349 | reg = <0x020a0000 0x4000>; |
| 350 | interrupts = <0 68 0x04 0 69 0x04>; |
| 351 | gpio-controller; |
| 352 | #gpio-cells = <2>; |
| 353 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 354 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 355 | }; |
| 356 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 357 | gpio3: gpio@020a4000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 358 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 359 | reg = <0x020a4000 0x4000>; |
| 360 | interrupts = <0 70 0x04 0 71 0x04>; |
| 361 | gpio-controller; |
| 362 | #gpio-cells = <2>; |
| 363 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 364 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 365 | }; |
| 366 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 367 | gpio4: gpio@020a8000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 368 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 369 | reg = <0x020a8000 0x4000>; |
| 370 | interrupts = <0 72 0x04 0 73 0x04>; |
| 371 | gpio-controller; |
| 372 | #gpio-cells = <2>; |
| 373 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 374 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 375 | }; |
| 376 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 377 | gpio5: gpio@020ac000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 378 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 379 | reg = <0x020ac000 0x4000>; |
| 380 | interrupts = <0 74 0x04 0 75 0x04>; |
| 381 | gpio-controller; |
| 382 | #gpio-cells = <2>; |
| 383 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 384 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 385 | }; |
| 386 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 387 | gpio6: gpio@020b0000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 388 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 389 | reg = <0x020b0000 0x4000>; |
| 390 | interrupts = <0 76 0x04 0 77 0x04>; |
| 391 | gpio-controller; |
| 392 | #gpio-cells = <2>; |
| 393 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 394 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 395 | }; |
| 396 | |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 397 | gpio7: gpio@020b4000 { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 398 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 399 | reg = <0x020b4000 0x4000>; |
| 400 | interrupts = <0 78 0x04 0 79 0x04>; |
| 401 | gpio-controller; |
| 402 | #gpio-cells = <2>; |
| 403 | interrupt-controller; |
Shawn Guo | 88cde8b | 2012-07-06 20:03:37 +0800 | [diff] [blame] | 404 | #interrupt-cells = <2>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 405 | }; |
| 406 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 407 | kpp: kpp@020b8000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 408 | reg = <0x020b8000 0x4000>; |
| 409 | interrupts = <0 82 0x04>; |
| 410 | }; |
| 411 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 412 | wdog1: wdog@020bc000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 413 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 414 | reg = <0x020bc000 0x4000>; |
| 415 | interrupts = <0 80 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 416 | clocks = <&clks 0>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 417 | }; |
| 418 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 419 | wdog2: wdog@020c0000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 420 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 421 | reg = <0x020c0000 0x4000>; |
| 422 | interrupts = <0 81 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 423 | clocks = <&clks 0>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 424 | status = "disabled"; |
| 425 | }; |
| 426 | |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 427 | clks: ccm@020c4000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 428 | compatible = "fsl,imx6q-ccm"; |
| 429 | reg = <0x020c4000 0x4000>; |
| 430 | interrupts = <0 87 0x04 0 88 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 431 | #clock-cells = <1>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 432 | }; |
| 433 | |
Dong Aisheng | baa6415 | 2012-09-05 10:57:15 +0800 | [diff] [blame] | 434 | anatop: anatop@020c8000 { |
| 435 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 436 | reg = <0x020c8000 0x1000>; |
| 437 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 438 | |
| 439 | regulator-1p1@110 { |
| 440 | compatible = "fsl,anatop-regulator"; |
| 441 | regulator-name = "vdd1p1"; |
| 442 | regulator-min-microvolt = <800000>; |
| 443 | regulator-max-microvolt = <1375000>; |
| 444 | regulator-always-on; |
| 445 | anatop-reg-offset = <0x110>; |
| 446 | anatop-vol-bit-shift = <8>; |
| 447 | anatop-vol-bit-width = <5>; |
| 448 | anatop-min-bit-val = <4>; |
| 449 | anatop-min-voltage = <800000>; |
| 450 | anatop-max-voltage = <1375000>; |
| 451 | }; |
| 452 | |
| 453 | regulator-3p0@120 { |
| 454 | compatible = "fsl,anatop-regulator"; |
| 455 | regulator-name = "vdd3p0"; |
| 456 | regulator-min-microvolt = <2800000>; |
| 457 | regulator-max-microvolt = <3150000>; |
| 458 | regulator-always-on; |
| 459 | anatop-reg-offset = <0x120>; |
| 460 | anatop-vol-bit-shift = <8>; |
| 461 | anatop-vol-bit-width = <5>; |
| 462 | anatop-min-bit-val = <0>; |
| 463 | anatop-min-voltage = <2625000>; |
| 464 | anatop-max-voltage = <3400000>; |
| 465 | }; |
| 466 | |
| 467 | regulator-2p5@130 { |
| 468 | compatible = "fsl,anatop-regulator"; |
| 469 | regulator-name = "vdd2p5"; |
| 470 | regulator-min-microvolt = <2000000>; |
| 471 | regulator-max-microvolt = <2750000>; |
| 472 | regulator-always-on; |
| 473 | anatop-reg-offset = <0x130>; |
| 474 | anatop-vol-bit-shift = <8>; |
| 475 | anatop-vol-bit-width = <5>; |
| 476 | anatop-min-bit-val = <0>; |
| 477 | anatop-min-voltage = <2000000>; |
| 478 | anatop-max-voltage = <2750000>; |
| 479 | }; |
| 480 | |
Shawn Guo | 96574a6 | 2013-01-08 14:25:14 +0800 | [diff] [blame] | 481 | reg_arm: regulator-vddcore@140 { |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 482 | compatible = "fsl,anatop-regulator"; |
| 483 | regulator-name = "cpu"; |
| 484 | regulator-min-microvolt = <725000>; |
| 485 | regulator-max-microvolt = <1450000>; |
| 486 | regulator-always-on; |
| 487 | anatop-reg-offset = <0x140>; |
| 488 | anatop-vol-bit-shift = <0>; |
| 489 | anatop-vol-bit-width = <5>; |
Anson Huang | 46743dd | 2013-01-30 17:33:44 -0500 | [diff] [blame^] | 490 | anatop-delay-reg-offset = <0x170>; |
| 491 | anatop-delay-bit-shift = <24>; |
| 492 | anatop-delay-bit-width = <2>; |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 493 | anatop-min-bit-val = <1>; |
| 494 | anatop-min-voltage = <725000>; |
| 495 | anatop-max-voltage = <1450000>; |
| 496 | }; |
| 497 | |
Shawn Guo | 96574a6 | 2013-01-08 14:25:14 +0800 | [diff] [blame] | 498 | reg_pu: regulator-vddpu@140 { |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 499 | compatible = "fsl,anatop-regulator"; |
| 500 | regulator-name = "vddpu"; |
| 501 | regulator-min-microvolt = <725000>; |
| 502 | regulator-max-microvolt = <1450000>; |
| 503 | regulator-always-on; |
| 504 | anatop-reg-offset = <0x140>; |
| 505 | anatop-vol-bit-shift = <9>; |
| 506 | anatop-vol-bit-width = <5>; |
Anson Huang | 46743dd | 2013-01-30 17:33:44 -0500 | [diff] [blame^] | 507 | anatop-delay-reg-offset = <0x170>; |
| 508 | anatop-delay-bit-shift = <26>; |
| 509 | anatop-delay-bit-width = <2>; |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 510 | anatop-min-bit-val = <1>; |
| 511 | anatop-min-voltage = <725000>; |
| 512 | anatop-max-voltage = <1450000>; |
| 513 | }; |
| 514 | |
Shawn Guo | 96574a6 | 2013-01-08 14:25:14 +0800 | [diff] [blame] | 515 | reg_soc: regulator-vddsoc@140 { |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 516 | compatible = "fsl,anatop-regulator"; |
| 517 | regulator-name = "vddsoc"; |
| 518 | regulator-min-microvolt = <725000>; |
| 519 | regulator-max-microvolt = <1450000>; |
| 520 | regulator-always-on; |
| 521 | anatop-reg-offset = <0x140>; |
| 522 | anatop-vol-bit-shift = <18>; |
| 523 | anatop-vol-bit-width = <5>; |
Anson Huang | 46743dd | 2013-01-30 17:33:44 -0500 | [diff] [blame^] | 524 | anatop-delay-reg-offset = <0x170>; |
| 525 | anatop-delay-bit-shift = <28>; |
| 526 | anatop-delay-bit-width = <2>; |
Ying-Chun Liu (PaulLiu) | a1e327e | 2012-03-30 21:46:53 +0800 | [diff] [blame] | 527 | anatop-min-bit-val = <1>; |
| 528 | anatop-min-voltage = <725000>; |
| 529 | anatop-max-voltage = <1450000>; |
| 530 | }; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 531 | }; |
| 532 | |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 533 | usbphy1: usbphy@020c9000 { |
| 534 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 535 | reg = <0x020c9000 0x1000>; |
| 536 | interrupts = <0 44 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 537 | clocks = <&clks 182>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 538 | }; |
| 539 | |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 540 | usbphy2: usbphy@020ca000 { |
| 541 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 542 | reg = <0x020ca000 0x1000>; |
| 543 | interrupts = <0 45 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 544 | clocks = <&clks 183>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 545 | }; |
| 546 | |
| 547 | snvs@020cc000 { |
Shawn Guo | c925038 | 2012-07-02 20:13:03 +0800 | [diff] [blame] | 548 | compatible = "fsl,sec-v4.0-mon", "simple-bus"; |
| 549 | #address-cells = <1>; |
| 550 | #size-cells = <1>; |
| 551 | ranges = <0 0x020cc000 0x4000>; |
| 552 | |
| 553 | snvs-rtc-lp@34 { |
| 554 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
| 555 | reg = <0x34 0x58>; |
| 556 | interrupts = <0 19 0x04 0 20 0x04>; |
| 557 | }; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 558 | }; |
| 559 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 560 | epit1: epit@020d0000 { /* EPIT1 */ |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 561 | reg = <0x020d0000 0x4000>; |
| 562 | interrupts = <0 56 0x04>; |
| 563 | }; |
| 564 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 565 | epit2: epit@020d4000 { /* EPIT2 */ |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 566 | reg = <0x020d4000 0x4000>; |
| 567 | interrupts = <0 57 0x04>; |
| 568 | }; |
| 569 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 570 | src: src@020d8000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 571 | compatible = "fsl,imx6q-src"; |
| 572 | reg = <0x020d8000 0x4000>; |
| 573 | interrupts = <0 91 0x04 0 96 0x04>; |
| 574 | }; |
| 575 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 576 | gpc: gpc@020dc000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 577 | compatible = "fsl,imx6q-gpc"; |
| 578 | reg = <0x020dc000 0x4000>; |
| 579 | interrupts = <0 89 0x04 0 90 0x04>; |
| 580 | }; |
| 581 | |
Dong Aisheng | df37e0c | 2012-09-05 10:57:14 +0800 | [diff] [blame] | 582 | gpr: iomuxc-gpr@020e0000 { |
| 583 | compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; |
| 584 | reg = <0x020e0000 0x38>; |
| 585 | }; |
| 586 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 587 | iomuxc: iomuxc@020e0000 { |
Dong Aisheng | 551fd20 | 2012-05-11 14:58:00 +0800 | [diff] [blame] | 588 | compatible = "fsl,imx6q-iomuxc"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 589 | reg = <0x020e0000 0x4000>; |
Dong Aisheng | 551fd20 | 2012-05-11 14:58:00 +0800 | [diff] [blame] | 590 | |
| 591 | /* shared pinctrl settings */ |
Richard Zhao | 5ca65c1 | 2012-05-09 11:21:11 +0800 | [diff] [blame] | 592 | audmux { |
| 593 | pinctrl_audmux_1: audmux-1 { |
Shawn Guo | 44a509f | 2012-08-10 17:17:56 +0800 | [diff] [blame] | 594 | fsl,pins = < |
| 595 | 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ |
| 596 | 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ |
| 597 | 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ |
| 598 | 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ |
| 599 | >; |
Richard Zhao | 5ca65c1 | 2012-05-09 11:21:11 +0800 | [diff] [blame] | 600 | }; |
| 601 | }; |
| 602 | |
Shawn Guo | 52ccd49 | 2012-08-11 11:17:42 +0800 | [diff] [blame] | 603 | ecspi1 { |
| 604 | pinctrl_ecspi1_1: ecspi1grp-1 { |
| 605 | fsl,pins = < |
| 606 | 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ |
| 607 | 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ |
| 608 | 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ |
| 609 | >; |
| 610 | }; |
| 611 | }; |
| 612 | |
Shawn Guo | 99d5f0c | 2012-08-11 10:47:14 +0800 | [diff] [blame] | 613 | enet { |
| 614 | pinctrl_enet_1: enetgrp-1 { |
| 615 | fsl,pins = < |
| 616 | 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ |
| 617 | 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */ |
| 618 | 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ |
| 619 | 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ |
| 620 | 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ |
| 621 | 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ |
| 622 | 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ |
| 623 | 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ |
| 624 | 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ |
| 625 | 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ |
| 626 | 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ |
| 627 | 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ |
| 628 | 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ |
| 629 | 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ |
| 630 | 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ |
Frank Li | 7629838 | 2012-10-30 18:24:57 +0000 | [diff] [blame] | 631 | 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/ |
Shawn Guo | 99d5f0c | 2012-08-11 10:47:14 +0800 | [diff] [blame] | 632 | >; |
| 633 | }; |
Shawn Guo | 9e3c006 | 2012-08-11 12:49:11 +0800 | [diff] [blame] | 634 | |
| 635 | pinctrl_enet_2: enetgrp-2 { |
| 636 | fsl,pins = < |
| 637 | 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ |
| 638 | 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */ |
| 639 | 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ |
| 640 | 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ |
| 641 | 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ |
| 642 | 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ |
| 643 | 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ |
| 644 | 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ |
| 645 | 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ |
| 646 | 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ |
| 647 | 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ |
| 648 | 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ |
| 649 | 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ |
| 650 | 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ |
| 651 | 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ |
| 652 | >; |
| 653 | }; |
Shawn Guo | 99d5f0c | 2012-08-11 10:47:14 +0800 | [diff] [blame] | 654 | }; |
| 655 | |
Huang Shijie | cf922fa | 2012-07-01 23:38:46 -0400 | [diff] [blame] | 656 | gpmi-nand { |
| 657 | pinctrl_gpmi_nand_1: gpmi-nand-1 { |
Shawn Guo | 44a509f | 2012-08-10 17:17:56 +0800 | [diff] [blame] | 658 | fsl,pins = < |
| 659 | 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ |
| 660 | 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ |
| 661 | 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ |
| 662 | 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ |
| 663 | 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ |
| 664 | 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ |
| 665 | 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ |
| 666 | 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ |
| 667 | 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ |
| 668 | 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ |
| 669 | 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ |
| 670 | 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ |
| 671 | 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ |
| 672 | 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ |
| 673 | 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ |
| 674 | 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ |
| 675 | 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ |
| 676 | 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ |
| 677 | 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ |
| 678 | >; |
Huang Shijie | cf922fa | 2012-07-01 23:38:46 -0400 | [diff] [blame] | 679 | }; |
| 680 | }; |
| 681 | |
Richard Zhao | d99a79f | 2012-05-09 10:47:20 +0800 | [diff] [blame] | 682 | i2c1 { |
| 683 | pinctrl_i2c1_1: i2c1grp-1 { |
Shawn Guo | 44a509f | 2012-08-10 17:17:56 +0800 | [diff] [blame] | 684 | fsl,pins = < |
| 685 | 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ |
| 686 | 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */ |
| 687 | >; |
Richard Zhao | d99a79f | 2012-05-09 10:47:20 +0800 | [diff] [blame] | 688 | }; |
| 689 | }; |
| 690 | |
Shawn Guo | 497ae17 | 2012-08-11 22:06:26 +0800 | [diff] [blame] | 691 | uart1 { |
| 692 | pinctrl_uart1_1: uart1grp-1 { |
| 693 | fsl,pins = < |
| 694 | 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ |
| 695 | 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ |
| 696 | >; |
| 697 | }; |
| 698 | }; |
| 699 | |
Shawn Guo | e30ba89 | 2012-08-11 12:33:51 +0800 | [diff] [blame] | 700 | uart2 { |
| 701 | pinctrl_uart2_1: uart2grp-1 { |
Shawn Guo | 44a509f | 2012-08-10 17:17:56 +0800 | [diff] [blame] | 702 | fsl,pins = < |
| 703 | 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ |
| 704 | 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */ |
| 705 | >; |
Richard Zhao | c3001b2 | 2012-05-09 14:44:47 +0800 | [diff] [blame] | 706 | }; |
| 707 | }; |
| 708 | |
Shawn Guo | 9e3c006 | 2012-08-11 12:49:11 +0800 | [diff] [blame] | 709 | uart4 { |
| 710 | pinctrl_uart4_1: uart4grp-1 { |
| 711 | fsl,pins = < |
| 712 | 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */ |
| 713 | 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ |
| 714 | >; |
| 715 | }; |
| 716 | }; |
| 717 | |
Richard Zhao | 97a5309 | 2012-09-19 11:25:16 +0800 | [diff] [blame] | 718 | usbotg { |
| 719 | pinctrl_usbotg_1: usbotggrp-1 { |
| 720 | fsl,pins = < |
| 721 | 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */ |
| 722 | >; |
| 723 | }; |
| 724 | }; |
| 725 | |
Shawn Guo | 497ae17 | 2012-08-11 22:06:26 +0800 | [diff] [blame] | 726 | usdhc2 { |
| 727 | pinctrl_usdhc2_1: usdhc2grp-1 { |
| 728 | fsl,pins = < |
| 729 | 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ |
| 730 | 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ |
| 731 | 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ |
| 732 | 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ |
| 733 | 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ |
| 734 | 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ |
| 735 | 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ |
| 736 | 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ |
| 737 | 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ |
| 738 | 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ |
| 739 | >; |
| 740 | }; |
| 741 | }; |
| 742 | |
Dong Aisheng | 551fd20 | 2012-05-11 14:58:00 +0800 | [diff] [blame] | 743 | usdhc3 { |
| 744 | pinctrl_usdhc3_1: usdhc3grp-1 { |
Shawn Guo | 44a509f | 2012-08-10 17:17:56 +0800 | [diff] [blame] | 745 | fsl,pins = < |
| 746 | 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ |
| 747 | 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ |
| 748 | 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ |
| 749 | 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ |
| 750 | 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ |
| 751 | 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ |
| 752 | 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ |
| 753 | 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ |
| 754 | 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ |
| 755 | 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ |
| 756 | >; |
Dong Aisheng | 551fd20 | 2012-05-11 14:58:00 +0800 | [diff] [blame] | 757 | }; |
Shawn Guo | 99d5f0c | 2012-08-11 10:47:14 +0800 | [diff] [blame] | 758 | |
| 759 | pinctrl_usdhc3_2: usdhc3grp-2 { |
| 760 | fsl,pins = < |
| 761 | 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ |
| 762 | 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ |
| 763 | 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ |
| 764 | 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ |
| 765 | 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ |
| 766 | 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ |
| 767 | >; |
| 768 | }; |
Dong Aisheng | 551fd20 | 2012-05-11 14:58:00 +0800 | [diff] [blame] | 769 | }; |
| 770 | |
| 771 | usdhc4 { |
| 772 | pinctrl_usdhc4_1: usdhc4grp-1 { |
Shawn Guo | 44a509f | 2012-08-10 17:17:56 +0800 | [diff] [blame] | 773 | fsl,pins = < |
| 774 | 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ |
| 775 | 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ |
| 776 | 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ |
| 777 | 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ |
| 778 | 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ |
| 779 | 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ |
| 780 | 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ |
| 781 | 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ |
| 782 | 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ |
| 783 | 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ |
| 784 | >; |
Dong Aisheng | 551fd20 | 2012-05-11 14:58:00 +0800 | [diff] [blame] | 785 | }; |
Shawn Guo | 99d5f0c | 2012-08-11 10:47:14 +0800 | [diff] [blame] | 786 | |
| 787 | pinctrl_usdhc4_2: usdhc4grp-2 { |
| 788 | fsl,pins = < |
| 789 | 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ |
| 790 | 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ |
| 791 | 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ |
| 792 | 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ |
| 793 | 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ |
| 794 | 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ |
| 795 | >; |
| 796 | }; |
Dong Aisheng | 551fd20 | 2012-05-11 14:58:00 +0800 | [diff] [blame] | 797 | }; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 798 | }; |
| 799 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 800 | dcic1: dcic@020e4000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 801 | reg = <0x020e4000 0x4000>; |
| 802 | interrupts = <0 124 0x04>; |
| 803 | }; |
| 804 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 805 | dcic2: dcic@020e8000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 806 | reg = <0x020e8000 0x4000>; |
| 807 | interrupts = <0 125 0x04>; |
| 808 | }; |
| 809 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 810 | sdma: sdma@020ec000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 811 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
| 812 | reg = <0x020ec000 0x4000>; |
| 813 | interrupts = <0 2 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 814 | clocks = <&clks 155>, <&clks 155>; |
| 815 | clock-names = "ipg", "ahb"; |
Fabio Estevam | d6b9c59 | 2013-01-17 12:13:25 -0200 | [diff] [blame] | 816 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 817 | }; |
| 818 | }; |
| 819 | |
| 820 | aips-bus@02100000 { /* AIPS2 */ |
| 821 | compatible = "fsl,aips-bus", "simple-bus"; |
| 822 | #address-cells = <1>; |
| 823 | #size-cells = <1>; |
| 824 | reg = <0x02100000 0x100000>; |
| 825 | ranges; |
| 826 | |
| 827 | caam@02100000 { |
| 828 | reg = <0x02100000 0x40000>; |
| 829 | interrupts = <0 105 0x04 0 106 0x04>; |
| 830 | }; |
| 831 | |
| 832 | aipstz@0217c000 { /* AIPSTZ2 */ |
| 833 | reg = <0x0217c000 0x4000>; |
| 834 | }; |
| 835 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 836 | usbotg: usb@02184000 { |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 837 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 838 | reg = <0x02184000 0x200>; |
| 839 | interrupts = <0 43 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 840 | clocks = <&clks 162>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 841 | fsl,usbphy = <&usbphy1>; |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 842 | fsl,usbmisc = <&usbmisc 0>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 843 | status = "disabled"; |
| 844 | }; |
| 845 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 846 | usbh1: usb@02184200 { |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 847 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 848 | reg = <0x02184200 0x200>; |
| 849 | interrupts = <0 40 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 850 | clocks = <&clks 162>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 851 | fsl,usbphy = <&usbphy2>; |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 852 | fsl,usbmisc = <&usbmisc 1>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 853 | status = "disabled"; |
| 854 | }; |
| 855 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 856 | usbh2: usb@02184400 { |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 857 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 858 | reg = <0x02184400 0x200>; |
| 859 | interrupts = <0 41 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 860 | clocks = <&clks 162>; |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 861 | fsl,usbmisc = <&usbmisc 2>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 862 | status = "disabled"; |
| 863 | }; |
| 864 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 865 | usbh3: usb@02184600 { |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 866 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 867 | reg = <0x02184600 0x200>; |
| 868 | interrupts = <0 42 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 869 | clocks = <&clks 162>; |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 870 | fsl,usbmisc = <&usbmisc 3>; |
Richard Zhao | 74bd88f | 2012-07-12 14:21:41 +0800 | [diff] [blame] | 871 | status = "disabled"; |
| 872 | }; |
| 873 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 874 | usbmisc: usbmisc: usbmisc@02184800 { |
Richard Zhao | 28342c6 | 2012-09-14 14:42:45 +0800 | [diff] [blame] | 875 | #index-cells = <1>; |
| 876 | compatible = "fsl,imx6q-usbmisc"; |
| 877 | reg = <0x02184800 0x200>; |
| 878 | clocks = <&clks 162>; |
| 879 | }; |
| 880 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 881 | fec: ethernet@02188000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 882 | compatible = "fsl,imx6q-fec"; |
| 883 | reg = <0x02188000 0x4000>; |
| 884 | interrupts = <0 118 0x04 0 119 0x04>; |
Frank Li | 8dd5c66 | 2013-02-05 14:21:06 +0800 | [diff] [blame] | 885 | clocks = <&clks 117>, <&clks 117>, <&clks 190>; |
Frank Li | 7629838 | 2012-10-30 18:24:57 +0000 | [diff] [blame] | 886 | clock-names = "ipg", "ahb", "ptp"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 887 | status = "disabled"; |
| 888 | }; |
| 889 | |
| 890 | mlb@0218c000 { |
| 891 | reg = <0x0218c000 0x4000>; |
| 892 | interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; |
| 893 | }; |
| 894 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 895 | usdhc1: usdhc@02190000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 896 | compatible = "fsl,imx6q-usdhc"; |
| 897 | reg = <0x02190000 0x4000>; |
| 898 | interrupts = <0 22 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 899 | clocks = <&clks 163>, <&clks 163>, <&clks 163>; |
| 900 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 901 | bus-width = <4>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 902 | status = "disabled"; |
| 903 | }; |
| 904 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 905 | usdhc2: usdhc@02194000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 906 | compatible = "fsl,imx6q-usdhc"; |
| 907 | reg = <0x02194000 0x4000>; |
| 908 | interrupts = <0 23 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 909 | clocks = <&clks 164>, <&clks 164>, <&clks 164>; |
| 910 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 911 | bus-width = <4>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 912 | status = "disabled"; |
| 913 | }; |
| 914 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 915 | usdhc3: usdhc@02198000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 916 | compatible = "fsl,imx6q-usdhc"; |
| 917 | reg = <0x02198000 0x4000>; |
| 918 | interrupts = <0 24 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 919 | clocks = <&clks 165>, <&clks 165>, <&clks 165>; |
| 920 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 921 | bus-width = <4>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 922 | status = "disabled"; |
| 923 | }; |
| 924 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 925 | usdhc4: usdhc@0219c000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 926 | compatible = "fsl,imx6q-usdhc"; |
| 927 | reg = <0x0219c000 0x4000>; |
| 928 | interrupts = <0 25 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 929 | clocks = <&clks 166>, <&clks 166>, <&clks 166>; |
| 930 | clock-names = "ipg", "ahb", "per"; |
Sascha Hauer | c104b6a | 2012-09-25 11:49:33 +0200 | [diff] [blame] | 931 | bus-width = <4>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 932 | status = "disabled"; |
| 933 | }; |
| 934 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 935 | i2c1: i2c@021a0000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 936 | #address-cells = <1>; |
| 937 | #size-cells = <0>; |
Shawn Guo | 5bdfba2 | 2012-09-14 15:19:00 +0800 | [diff] [blame] | 938 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 939 | reg = <0x021a0000 0x4000>; |
| 940 | interrupts = <0 36 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 941 | clocks = <&clks 125>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 942 | status = "disabled"; |
| 943 | }; |
| 944 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 945 | i2c2: i2c@021a4000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 946 | #address-cells = <1>; |
| 947 | #size-cells = <0>; |
Shawn Guo | 5bdfba2 | 2012-09-14 15:19:00 +0800 | [diff] [blame] | 948 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 949 | reg = <0x021a4000 0x4000>; |
| 950 | interrupts = <0 37 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 951 | clocks = <&clks 126>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 952 | status = "disabled"; |
| 953 | }; |
| 954 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 955 | i2c3: i2c@021a8000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 956 | #address-cells = <1>; |
| 957 | #size-cells = <0>; |
Shawn Guo | 5bdfba2 | 2012-09-14 15:19:00 +0800 | [diff] [blame] | 958 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 959 | reg = <0x021a8000 0x4000>; |
| 960 | interrupts = <0 38 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 961 | clocks = <&clks 127>; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 962 | status = "disabled"; |
| 963 | }; |
| 964 | |
| 965 | romcp@021ac000 { |
| 966 | reg = <0x021ac000 0x4000>; |
| 967 | }; |
| 968 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 969 | mmdc0: mmdc@021b0000 { /* MMDC0 */ |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 970 | compatible = "fsl,imx6q-mmdc"; |
| 971 | reg = <0x021b0000 0x4000>; |
| 972 | }; |
| 973 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 974 | mmdc1: mmdc@021b4000 { /* MMDC1 */ |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 975 | reg = <0x021b4000 0x4000>; |
| 976 | }; |
| 977 | |
| 978 | weim@021b8000 { |
| 979 | reg = <0x021b8000 0x4000>; |
| 980 | interrupts = <0 14 0x04>; |
| 981 | }; |
| 982 | |
| 983 | ocotp@021bc000 { |
Shawn Guo | 96574a6 | 2013-01-08 14:25:14 +0800 | [diff] [blame] | 984 | compatible = "fsl,imx6q-ocotp"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 985 | reg = <0x021bc000 0x4000>; |
| 986 | }; |
| 987 | |
| 988 | ocotp@021c0000 { |
| 989 | reg = <0x021c0000 0x4000>; |
| 990 | interrupts = <0 21 0x04>; |
| 991 | }; |
| 992 | |
| 993 | tzasc@021d0000 { /* TZASC1 */ |
| 994 | reg = <0x021d0000 0x4000>; |
| 995 | interrupts = <0 108 0x04>; |
| 996 | }; |
| 997 | |
| 998 | tzasc@021d4000 { /* TZASC2 */ |
| 999 | reg = <0x021d4000 0x4000>; |
| 1000 | interrupts = <0 109 0x04>; |
| 1001 | }; |
| 1002 | |
Sascha Hauer | 7b7d672 | 2012-11-15 09:31:52 +0100 | [diff] [blame] | 1003 | audmux: audmux@021d8000 { |
Richard Zhao | f965cd5 | 2012-05-02 10:32:26 +0800 | [diff] [blame] | 1004 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1005 | reg = <0x021d8000 0x4000>; |
Richard Zhao | f965cd5 | 2012-05-02 10:32:26 +0800 | [diff] [blame] | 1006 | status = "disabled"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1007 | }; |
| 1008 | |
| 1009 | mipi@021dc000 { /* MIPI-CSI */ |
| 1010 | reg = <0x021dc000 0x4000>; |
| 1011 | }; |
| 1012 | |
| 1013 | mipi@021e0000 { /* MIPI-DSI */ |
| 1014 | reg = <0x021e0000 0x4000>; |
| 1015 | }; |
| 1016 | |
| 1017 | vdoa@021e4000 { |
| 1018 | reg = <0x021e4000 0x4000>; |
| 1019 | interrupts = <0 18 0x04>; |
| 1020 | }; |
| 1021 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 1022 | uart2: serial@021e8000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1023 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1024 | reg = <0x021e8000 0x4000>; |
| 1025 | interrupts = <0 27 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1026 | clocks = <&clks 160>, <&clks 161>; |
| 1027 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1028 | status = "disabled"; |
| 1029 | }; |
| 1030 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 1031 | uart3: serial@021ec000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1032 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1033 | reg = <0x021ec000 0x4000>; |
| 1034 | interrupts = <0 28 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1035 | clocks = <&clks 160>, <&clks 161>; |
| 1036 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1037 | status = "disabled"; |
| 1038 | }; |
| 1039 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 1040 | uart4: serial@021f0000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1041 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1042 | reg = <0x021f0000 0x4000>; |
| 1043 | interrupts = <0 29 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1044 | clocks = <&clks 160>, <&clks 161>; |
| 1045 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1046 | status = "disabled"; |
| 1047 | }; |
| 1048 | |
Shawn Guo | 0c456cf | 2012-04-02 14:39:26 +0800 | [diff] [blame] | 1049 | uart5: serial@021f4000 { |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1050 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1051 | reg = <0x021f4000 0x4000>; |
| 1052 | interrupts = <0 30 0x04>; |
Shawn Guo | 0e87e04 | 2012-08-22 21:36:28 +0800 | [diff] [blame] | 1053 | clocks = <&clks 160>, <&clks 161>; |
| 1054 | clock-names = "ipg", "per"; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1055 | status = "disabled"; |
| 1056 | }; |
| 1057 | }; |
Sascha Hauer | 91660d7 | 2012-11-12 15:52:21 +0100 | [diff] [blame] | 1058 | |
| 1059 | ipu1: ipu@02400000 { |
| 1060 | #crtc-cells = <1>; |
| 1061 | compatible = "fsl,imx6q-ipu"; |
| 1062 | reg = <0x02400000 0x400000>; |
| 1063 | interrupts = <0 6 0x4 0 5 0x4>; |
| 1064 | clocks = <&clks 130>, <&clks 131>, <&clks 132>; |
| 1065 | clock-names = "bus", "di0", "di1"; |
| 1066 | }; |
| 1067 | |
| 1068 | ipu2: ipu@02800000 { |
| 1069 | #crtc-cells = <1>; |
| 1070 | compatible = "fsl,imx6q-ipu"; |
| 1071 | reg = <0x02800000 0x400000>; |
| 1072 | interrupts = <0 8 0x4 0 7 0x4>; |
| 1073 | clocks = <&clks 133>, <&clks 134>, <&clks 137>; |
| 1074 | clock-names = "bus", "di0", "di1"; |
| 1075 | }; |
Shawn Guo | 7d740f8 | 2011-09-06 13:53:26 +0800 | [diff] [blame] | 1076 | }; |
| 1077 | }; |