Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1 | /* |
| 2 | * TI EDMA DMA engine driver |
| 3 | * |
| 4 | * Copyright 2012 Texas Instruments |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation version 2. |
| 9 | * |
| 10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 11 | * kind, whether express or implied; without even the implied warranty |
| 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/dmaengine.h> |
| 17 | #include <linux/dma-mapping.h> |
Lad, Prabhakar | b7a4fd5 | 2015-02-04 13:03:27 +0000 | [diff] [blame] | 18 | #include <linux/edma.h> |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 19 | #include <linux/err.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/interrupt.h> |
| 22 | #include <linux/list.h> |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/slab.h> |
| 26 | #include <linux/spinlock.h> |
Peter Ujfalusi | ed64610 | 2014-07-31 13:12:38 +0300 | [diff] [blame] | 27 | #include <linux/of.h> |
Peter Ujfalusi | dc9b6055 | 2015-10-14 14:42:47 +0300 | [diff] [blame] | 28 | #include <linux/of_dma.h> |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 29 | #include <linux/of_irq.h> |
| 30 | #include <linux/of_address.h> |
| 31 | #include <linux/of_device.h> |
| 32 | #include <linux/pm_runtime.h> |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 33 | |
Matt Porter | 3ad7a42 | 2013-03-06 11:15:31 -0500 | [diff] [blame] | 34 | #include <linux/platform_data/edma.h> |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 35 | |
| 36 | #include "dmaengine.h" |
| 37 | #include "virt-dma.h" |
| 38 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 39 | /* Offsets matching "struct edmacc_param" */ |
| 40 | #define PARM_OPT 0x00 |
| 41 | #define PARM_SRC 0x04 |
| 42 | #define PARM_A_B_CNT 0x08 |
| 43 | #define PARM_DST 0x0c |
| 44 | #define PARM_SRC_DST_BIDX 0x10 |
| 45 | #define PARM_LINK_BCNTRLD 0x14 |
| 46 | #define PARM_SRC_DST_CIDX 0x18 |
| 47 | #define PARM_CCNT 0x1c |
| 48 | |
| 49 | #define PARM_SIZE 0x20 |
| 50 | |
| 51 | /* Offsets for EDMA CC global channel registers and their shadows */ |
| 52 | #define SH_ER 0x00 /* 64 bits */ |
| 53 | #define SH_ECR 0x08 /* 64 bits */ |
| 54 | #define SH_ESR 0x10 /* 64 bits */ |
| 55 | #define SH_CER 0x18 /* 64 bits */ |
| 56 | #define SH_EER 0x20 /* 64 bits */ |
| 57 | #define SH_EECR 0x28 /* 64 bits */ |
| 58 | #define SH_EESR 0x30 /* 64 bits */ |
| 59 | #define SH_SER 0x38 /* 64 bits */ |
| 60 | #define SH_SECR 0x40 /* 64 bits */ |
| 61 | #define SH_IER 0x50 /* 64 bits */ |
| 62 | #define SH_IECR 0x58 /* 64 bits */ |
| 63 | #define SH_IESR 0x60 /* 64 bits */ |
| 64 | #define SH_IPR 0x68 /* 64 bits */ |
| 65 | #define SH_ICR 0x70 /* 64 bits */ |
| 66 | #define SH_IEVAL 0x78 |
| 67 | #define SH_QER 0x80 |
| 68 | #define SH_QEER 0x84 |
| 69 | #define SH_QEECR 0x88 |
| 70 | #define SH_QEESR 0x8c |
| 71 | #define SH_QSER 0x90 |
| 72 | #define SH_QSECR 0x94 |
| 73 | #define SH_SIZE 0x200 |
| 74 | |
| 75 | /* Offsets for EDMA CC global registers */ |
| 76 | #define EDMA_REV 0x0000 |
| 77 | #define EDMA_CCCFG 0x0004 |
| 78 | #define EDMA_QCHMAP 0x0200 /* 8 registers */ |
| 79 | #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ |
| 80 | #define EDMA_QDMAQNUM 0x0260 |
| 81 | #define EDMA_QUETCMAP 0x0280 |
| 82 | #define EDMA_QUEPRI 0x0284 |
| 83 | #define EDMA_EMR 0x0300 /* 64 bits */ |
| 84 | #define EDMA_EMCR 0x0308 /* 64 bits */ |
| 85 | #define EDMA_QEMR 0x0310 |
| 86 | #define EDMA_QEMCR 0x0314 |
| 87 | #define EDMA_CCERR 0x0318 |
| 88 | #define EDMA_CCERRCLR 0x031c |
| 89 | #define EDMA_EEVAL 0x0320 |
| 90 | #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ |
| 91 | #define EDMA_QRAE 0x0380 /* 4 registers */ |
| 92 | #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ |
| 93 | #define EDMA_QSTAT 0x0600 /* 2 registers */ |
| 94 | #define EDMA_QWMTHRA 0x0620 |
| 95 | #define EDMA_QWMTHRB 0x0624 |
| 96 | #define EDMA_CCSTAT 0x0640 |
| 97 | |
| 98 | #define EDMA_M 0x1000 /* global channel registers */ |
| 99 | #define EDMA_ECR 0x1008 |
| 100 | #define EDMA_ECRH 0x100C |
| 101 | #define EDMA_SHADOW0 0x2000 /* 4 shadow regions */ |
| 102 | #define EDMA_PARM 0x4000 /* PaRAM entries */ |
| 103 | |
| 104 | #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) |
| 105 | |
| 106 | #define EDMA_DCHMAP 0x0100 /* 64 registers */ |
| 107 | |
| 108 | /* CCCFG register */ |
| 109 | #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */ |
Dan Carpenter | f5ea7ad | 2015-11-04 16:38:31 +0300 | [diff] [blame] | 110 | #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */ |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 111 | #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */ |
| 112 | #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */ |
| 113 | #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */ |
| 114 | #define CHMAP_EXIST BIT(24) |
| 115 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 116 | /* |
Joel Fernandes | 2abd5f1 | 2013-09-23 18:05:15 -0500 | [diff] [blame] | 117 | * Max of 20 segments per channel to conserve PaRAM slots |
| 118 | * Also note that MAX_NR_SG should be atleast the no.of periods |
| 119 | * that are required for ASoC, otherwise DMA prep calls will |
| 120 | * fail. Today davinci-pcm is the only user of this driver and |
| 121 | * requires atleast 17 slots, so we setup the default to 20. |
| 122 | */ |
| 123 | #define MAX_NR_SG 20 |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 124 | #define EDMA_MAX_SLOTS MAX_NR_SG |
| 125 | #define EDMA_DESCRIPTORS 16 |
| 126 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 127 | #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ |
| 128 | #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ |
| 129 | #define EDMA_CONT_PARAMS_ANY 1001 |
| 130 | #define EDMA_CONT_PARAMS_FIXED_EXACT 1002 |
| 131 | #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 |
| 132 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 133 | /* PaRAM slots are laid out like this */ |
| 134 | struct edmacc_param { |
| 135 | u32 opt; |
| 136 | u32 src; |
| 137 | u32 a_b_cnt; |
| 138 | u32 dst; |
| 139 | u32 src_dst_bidx; |
| 140 | u32 link_bcntrld; |
| 141 | u32 src_dst_cidx; |
| 142 | u32 ccnt; |
| 143 | } __packed; |
| 144 | |
| 145 | /* fields in edmacc_param.opt */ |
| 146 | #define SAM BIT(0) |
| 147 | #define DAM BIT(1) |
| 148 | #define SYNCDIM BIT(2) |
| 149 | #define STATIC BIT(3) |
| 150 | #define EDMA_FWID (0x07 << 8) |
| 151 | #define TCCMODE BIT(11) |
| 152 | #define EDMA_TCC(t) ((t) << 12) |
| 153 | #define TCINTEN BIT(20) |
| 154 | #define ITCINTEN BIT(21) |
| 155 | #define TCCHEN BIT(22) |
| 156 | #define ITCCHEN BIT(23) |
| 157 | |
Thomas Gleixner | b5088ad | 2014-04-28 14:23:55 -0500 | [diff] [blame] | 158 | struct edma_pset { |
Thomas Gleixner | c2da234 | 2014-04-28 14:29:57 -0500 | [diff] [blame] | 159 | u32 len; |
| 160 | dma_addr_t addr; |
Thomas Gleixner | b5088ad | 2014-04-28 14:23:55 -0500 | [diff] [blame] | 161 | struct edmacc_param param; |
| 162 | }; |
| 163 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 164 | struct edma_desc { |
| 165 | struct virt_dma_desc vdesc; |
| 166 | struct list_head node; |
Thomas Gleixner | c2da234 | 2014-04-28 14:29:57 -0500 | [diff] [blame] | 167 | enum dma_transfer_direction direction; |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 168 | int cyclic; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 169 | int absync; |
| 170 | int pset_nr; |
Thomas Gleixner | 740b41f | 2014-04-28 14:34:11 -0500 | [diff] [blame] | 171 | struct edma_chan *echan; |
Joel Fernandes | 04361d8 | 2014-04-28 15:19:31 -0500 | [diff] [blame] | 172 | int processed; |
| 173 | |
| 174 | /* |
| 175 | * The following 4 elements are used for residue accounting. |
| 176 | * |
| 177 | * - processed_stat: the number of SG elements we have traversed |
| 178 | * so far to cover accounting. This is updated directly to processed |
| 179 | * during edma_callback and is always <= processed, because processed |
| 180 | * refers to the number of pending transfer (programmed to EDMA |
| 181 | * controller), where as processed_stat tracks number of transfers |
| 182 | * accounted for so far. |
| 183 | * |
| 184 | * - residue: The amount of bytes we have left to transfer for this desc |
| 185 | * |
| 186 | * - residue_stat: The residue in bytes of data we have covered |
| 187 | * so far for accounting. This is updated directly to residue |
| 188 | * during callbacks to keep it current. |
| 189 | * |
| 190 | * - sg_len: Tracks the length of the current intermediate transfer, |
| 191 | * this is required to update the residue during intermediate transfer |
| 192 | * completion callback. |
| 193 | */ |
| 194 | int processed_stat; |
| 195 | u32 sg_len; |
| 196 | u32 residue; |
| 197 | u32 residue_stat; |
| 198 | |
Thomas Gleixner | b5088ad | 2014-04-28 14:23:55 -0500 | [diff] [blame] | 199 | struct edma_pset pset[0]; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 200 | }; |
| 201 | |
| 202 | struct edma_cc; |
| 203 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 204 | struct edma_tc { |
| 205 | struct device_node *node; |
| 206 | u16 id; |
| 207 | }; |
| 208 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 209 | struct edma_chan { |
| 210 | struct virt_dma_chan vchan; |
| 211 | struct list_head node; |
| 212 | struct edma_desc *edesc; |
| 213 | struct edma_cc *ecc; |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 214 | struct edma_tc *tc; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 215 | int ch_num; |
| 216 | bool alloced; |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 217 | bool hw_triggered; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 218 | int slot[EDMA_MAX_SLOTS]; |
Joel Fernandes | c5f4799 | 2013-08-29 18:05:43 -0500 | [diff] [blame] | 219 | int missed; |
Matt Porter | 661f7cb | 2013-01-10 13:41:04 -0500 | [diff] [blame] | 220 | struct dma_slave_config cfg; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 221 | }; |
| 222 | |
| 223 | struct edma_cc { |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 224 | struct device *dev; |
| 225 | struct edma_soc_info *info; |
| 226 | void __iomem *base; |
| 227 | int id; |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 228 | bool legacy_mode; |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 229 | |
| 230 | /* eDMA3 resource information */ |
| 231 | unsigned num_channels; |
Peter Ujfalusi | 633e42b | 2015-10-16 10:18:04 +0300 | [diff] [blame] | 232 | unsigned num_qchannels; |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 233 | unsigned num_region; |
| 234 | unsigned num_slots; |
| 235 | unsigned num_tc; |
Peter Ujfalusi | 4ab54f6 | 2015-10-14 14:43:04 +0300 | [diff] [blame] | 236 | bool chmap_exist; |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 237 | enum dma_event_q default_queue; |
| 238 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 239 | /* |
| 240 | * The slot_inuse bit for each PaRAM slot is clear unless the slot is |
| 241 | * in use by Linux or if it is allocated to be used by DSP. |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 242 | */ |
Peter Ujfalusi | 7a73b13 | 2015-10-14 14:43:05 +0300 | [diff] [blame] | 243 | unsigned long *slot_inuse; |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 244 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 245 | struct dma_device dma_slave; |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 246 | struct dma_device *dma_memcpy; |
Peter Ujfalusi | cb78205 | 2015-10-14 14:42:54 +0300 | [diff] [blame] | 247 | struct edma_chan *slave_chans; |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 248 | struct edma_tc *tc_list; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 249 | int dummy_slot; |
| 250 | }; |
| 251 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 252 | /* dummy param set used to (re)initialize parameter RAM slots */ |
| 253 | static const struct edmacc_param dummy_paramset = { |
| 254 | .link_bcntrld = 0xffff, |
| 255 | .ccnt = 1, |
| 256 | }; |
| 257 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 258 | #define EDMA_BINDING_LEGACY 0 |
| 259 | #define EDMA_BINDING_TPCC 1 |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 260 | static const struct of_device_id edma_of_ids[] = { |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 261 | { |
| 262 | .compatible = "ti,edma3", |
| 263 | .data = (void *)EDMA_BINDING_LEGACY, |
| 264 | }, |
| 265 | { |
| 266 | .compatible = "ti,edma3-tpcc", |
| 267 | .data = (void *)EDMA_BINDING_TPCC, |
| 268 | }, |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 269 | {} |
| 270 | }; |
| 271 | |
Peter Ujfalusi | 34635b1a | 2015-11-02 15:21:40 +0200 | [diff] [blame] | 272 | static const struct of_device_id edma_tptc_of_ids[] = { |
| 273 | { .compatible = "ti,edma3-tptc", }, |
| 274 | {} |
| 275 | }; |
| 276 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 277 | static inline unsigned int edma_read(struct edma_cc *ecc, int offset) |
| 278 | { |
| 279 | return (unsigned int)__raw_readl(ecc->base + offset); |
| 280 | } |
| 281 | |
| 282 | static inline void edma_write(struct edma_cc *ecc, int offset, int val) |
| 283 | { |
| 284 | __raw_writel(val, ecc->base + offset); |
| 285 | } |
| 286 | |
| 287 | static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, |
| 288 | unsigned or) |
| 289 | { |
| 290 | unsigned val = edma_read(ecc, offset); |
| 291 | |
| 292 | val &= and; |
| 293 | val |= or; |
| 294 | edma_write(ecc, offset, val); |
| 295 | } |
| 296 | |
| 297 | static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and) |
| 298 | { |
| 299 | unsigned val = edma_read(ecc, offset); |
| 300 | |
| 301 | val &= and; |
| 302 | edma_write(ecc, offset, val); |
| 303 | } |
| 304 | |
| 305 | static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) |
| 306 | { |
| 307 | unsigned val = edma_read(ecc, offset); |
| 308 | |
| 309 | val |= or; |
| 310 | edma_write(ecc, offset, val); |
| 311 | } |
| 312 | |
| 313 | static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset, |
| 314 | int i) |
| 315 | { |
| 316 | return edma_read(ecc, offset + (i << 2)); |
| 317 | } |
| 318 | |
| 319 | static inline void edma_write_array(struct edma_cc *ecc, int offset, int i, |
| 320 | unsigned val) |
| 321 | { |
| 322 | edma_write(ecc, offset + (i << 2), val); |
| 323 | } |
| 324 | |
| 325 | static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i, |
| 326 | unsigned and, unsigned or) |
| 327 | { |
| 328 | edma_modify(ecc, offset + (i << 2), and, or); |
| 329 | } |
| 330 | |
| 331 | static inline void edma_or_array(struct edma_cc *ecc, int offset, int i, |
| 332 | unsigned or) |
| 333 | { |
| 334 | edma_or(ecc, offset + (i << 2), or); |
| 335 | } |
| 336 | |
| 337 | static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j, |
| 338 | unsigned or) |
| 339 | { |
| 340 | edma_or(ecc, offset + ((i * 2 + j) << 2), or); |
| 341 | } |
| 342 | |
| 343 | static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i, |
| 344 | int j, unsigned val) |
| 345 | { |
| 346 | edma_write(ecc, offset + ((i * 2 + j) << 2), val); |
| 347 | } |
| 348 | |
| 349 | static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset) |
| 350 | { |
| 351 | return edma_read(ecc, EDMA_SHADOW0 + offset); |
| 352 | } |
| 353 | |
| 354 | static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc, |
| 355 | int offset, int i) |
| 356 | { |
| 357 | return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2)); |
| 358 | } |
| 359 | |
| 360 | static inline void edma_shadow0_write(struct edma_cc *ecc, int offset, |
| 361 | unsigned val) |
| 362 | { |
| 363 | edma_write(ecc, EDMA_SHADOW0 + offset, val); |
| 364 | } |
| 365 | |
| 366 | static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, |
| 367 | int i, unsigned val) |
| 368 | { |
| 369 | edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val); |
| 370 | } |
| 371 | |
Peter Ujfalusi | d9c345d | 2015-10-16 10:18:02 +0300 | [diff] [blame] | 372 | static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset, |
| 373 | int param_no) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 374 | { |
| 375 | return edma_read(ecc, EDMA_PARM + offset + (param_no << 5)); |
| 376 | } |
| 377 | |
Peter Ujfalusi | d9c345d | 2015-10-16 10:18:02 +0300 | [diff] [blame] | 378 | static inline void edma_param_write(struct edma_cc *ecc, int offset, |
| 379 | int param_no, unsigned val) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 380 | { |
| 381 | edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val); |
| 382 | } |
| 383 | |
Peter Ujfalusi | d9c345d | 2015-10-16 10:18:02 +0300 | [diff] [blame] | 384 | static inline void edma_param_modify(struct edma_cc *ecc, int offset, |
| 385 | int param_no, unsigned and, unsigned or) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 386 | { |
| 387 | edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or); |
| 388 | } |
| 389 | |
Peter Ujfalusi | d9c345d | 2015-10-16 10:18:02 +0300 | [diff] [blame] | 390 | static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no, |
| 391 | unsigned and) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 392 | { |
| 393 | edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and); |
| 394 | } |
| 395 | |
Peter Ujfalusi | d9c345d | 2015-10-16 10:18:02 +0300 | [diff] [blame] | 396 | static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no, |
| 397 | unsigned or) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 398 | { |
| 399 | edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or); |
| 400 | } |
| 401 | |
| 402 | static inline void set_bits(int offset, int len, unsigned long *p) |
| 403 | { |
| 404 | for (; len > 0; len--) |
| 405 | set_bit(offset + (len - 1), p); |
| 406 | } |
| 407 | |
| 408 | static inline void clear_bits(int offset, int len, unsigned long *p) |
| 409 | { |
| 410 | for (; len > 0; len--) |
| 411 | clear_bit(offset + (len - 1), p); |
| 412 | } |
| 413 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 414 | static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, |
| 415 | int priority) |
| 416 | { |
| 417 | int bit = queue_no * 4; |
| 418 | |
| 419 | edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); |
| 420 | } |
| 421 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 422 | static void edma_set_chmap(struct edma_chan *echan, int slot) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 423 | { |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 424 | struct edma_cc *ecc = echan->ecc; |
| 425 | int channel = EDMA_CHAN_SLOT(echan->ch_num); |
| 426 | |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 427 | if (ecc->chmap_exist) { |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 428 | slot = EDMA_CHAN_SLOT(slot); |
| 429 | edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5)); |
| 430 | } |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 431 | } |
| 432 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 433 | static void edma_setup_interrupt(struct edma_chan *echan, bool enable) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 434 | { |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 435 | struct edma_cc *ecc = echan->ecc; |
| 436 | int channel = EDMA_CHAN_SLOT(echan->ch_num); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 437 | |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 438 | if (enable) { |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 439 | edma_shadow0_write_array(ecc, SH_ICR, channel >> 5, |
| 440 | BIT(channel & 0x1f)); |
| 441 | edma_shadow0_write_array(ecc, SH_IESR, channel >> 5, |
| 442 | BIT(channel & 0x1f)); |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 443 | } else { |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 444 | edma_shadow0_write_array(ecc, SH_IECR, channel >> 5, |
| 445 | BIT(channel & 0x1f)); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 446 | } |
| 447 | } |
| 448 | |
| 449 | /* |
Peter Ujfalusi | 11c1573 | 2015-10-14 14:43:00 +0300 | [diff] [blame] | 450 | * paRAM slot management functions |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 451 | */ |
| 452 | static void edma_write_slot(struct edma_cc *ecc, unsigned slot, |
| 453 | const struct edmacc_param *param) |
| 454 | { |
| 455 | slot = EDMA_CHAN_SLOT(slot); |
| 456 | if (slot >= ecc->num_slots) |
| 457 | return; |
| 458 | memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE); |
| 459 | } |
| 460 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 461 | static void edma_read_slot(struct edma_cc *ecc, unsigned slot, |
| 462 | struct edmacc_param *param) |
| 463 | { |
| 464 | slot = EDMA_CHAN_SLOT(slot); |
| 465 | if (slot >= ecc->num_slots) |
| 466 | return; |
| 467 | memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE); |
| 468 | } |
| 469 | |
| 470 | /** |
| 471 | * edma_alloc_slot - allocate DMA parameter RAM |
| 472 | * @ecc: pointer to edma_cc struct |
| 473 | * @slot: specific slot to allocate; negative for "any unused slot" |
| 474 | * |
| 475 | * This allocates a parameter RAM slot, initializing it to hold a |
| 476 | * dummy transfer. Slots allocated using this routine have not been |
| 477 | * mapped to a hardware DMA channel, and will normally be used by |
| 478 | * linking to them from a slot associated with a DMA channel. |
| 479 | * |
| 480 | * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific |
| 481 | * slots may be allocated on behalf of DSP firmware. |
| 482 | * |
| 483 | * Returns the number of the slot, else negative errno. |
| 484 | */ |
| 485 | static int edma_alloc_slot(struct edma_cc *ecc, int slot) |
| 486 | { |
Peter Ujfalusi | d20313b | 2016-01-11 10:38:01 +0200 | [diff] [blame] | 487 | if (slot >= 0) { |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 488 | slot = EDMA_CHAN_SLOT(slot); |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 489 | /* Requesting entry paRAM slot for a HW triggered channel. */ |
| 490 | if (ecc->chmap_exist && slot < ecc->num_channels) |
| 491 | slot = EDMA_SLOT_ANY; |
| 492 | } |
| 493 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 494 | if (slot < 0) { |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 495 | if (ecc->chmap_exist) |
| 496 | slot = 0; |
| 497 | else |
| 498 | slot = ecc->num_channels; |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 499 | for (;;) { |
Peter Ujfalusi | 7a73b13 | 2015-10-14 14:43:05 +0300 | [diff] [blame] | 500 | slot = find_next_zero_bit(ecc->slot_inuse, |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 501 | ecc->num_slots, |
| 502 | slot); |
| 503 | if (slot == ecc->num_slots) |
| 504 | return -ENOMEM; |
Peter Ujfalusi | 7a73b13 | 2015-10-14 14:43:05 +0300 | [diff] [blame] | 505 | if (!test_and_set_bit(slot, ecc->slot_inuse)) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 506 | break; |
| 507 | } |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 508 | } else if (slot >= ecc->num_slots) { |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 509 | return -EINVAL; |
Peter Ujfalusi | 7a73b13 | 2015-10-14 14:43:05 +0300 | [diff] [blame] | 510 | } else if (test_and_set_bit(slot, ecc->slot_inuse)) { |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 511 | return -EBUSY; |
| 512 | } |
| 513 | |
| 514 | edma_write_slot(ecc, slot, &dummy_paramset); |
| 515 | |
| 516 | return EDMA_CTLR_CHAN(ecc->id, slot); |
| 517 | } |
| 518 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 519 | static void edma_free_slot(struct edma_cc *ecc, unsigned slot) |
| 520 | { |
| 521 | slot = EDMA_CHAN_SLOT(slot); |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 522 | if (slot >= ecc->num_slots) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 523 | return; |
| 524 | |
| 525 | edma_write_slot(ecc, slot, &dummy_paramset); |
Peter Ujfalusi | 7a73b13 | 2015-10-14 14:43:05 +0300 | [diff] [blame] | 526 | clear_bit(slot, ecc->slot_inuse); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 527 | } |
| 528 | |
| 529 | /** |
| 530 | * edma_link - link one parameter RAM slot to another |
| 531 | * @ecc: pointer to edma_cc struct |
| 532 | * @from: parameter RAM slot originating the link |
| 533 | * @to: parameter RAM slot which is the link target |
| 534 | * |
| 535 | * The originating slot should not be part of any active DMA transfer. |
| 536 | */ |
| 537 | static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to) |
| 538 | { |
Peter Ujfalusi | fc01409 | 2015-10-14 14:42:59 +0300 | [diff] [blame] | 539 | if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to))) |
| 540 | dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n"); |
| 541 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 542 | from = EDMA_CHAN_SLOT(from); |
| 543 | to = EDMA_CHAN_SLOT(to); |
| 544 | if (from >= ecc->num_slots || to >= ecc->num_slots) |
| 545 | return; |
| 546 | |
Peter Ujfalusi | d9c345d | 2015-10-16 10:18:02 +0300 | [diff] [blame] | 547 | edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000, |
| 548 | PARM_OFFSET(to)); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 549 | } |
| 550 | |
| 551 | /** |
| 552 | * edma_get_position - returns the current transfer point |
| 553 | * @ecc: pointer to edma_cc struct |
| 554 | * @slot: parameter RAM slot being examined |
| 555 | * @dst: true selects the dest position, false the source |
| 556 | * |
| 557 | * Returns the position of the current active slot |
| 558 | */ |
| 559 | static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot, |
| 560 | bool dst) |
| 561 | { |
| 562 | u32 offs; |
| 563 | |
| 564 | slot = EDMA_CHAN_SLOT(slot); |
| 565 | offs = PARM_OFFSET(slot); |
| 566 | offs += dst ? PARM_DST : PARM_SRC; |
| 567 | |
| 568 | return edma_read(ecc, offs); |
| 569 | } |
| 570 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 571 | /* |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 572 | * Channels with event associations will be triggered by their hardware |
| 573 | * events, and channels without such associations will be triggered by |
| 574 | * software. (At this writing there is no interface for using software |
| 575 | * triggers except with channels that don't support hardware triggers.) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 576 | */ |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 577 | static void edma_start(struct edma_chan *echan) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 578 | { |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 579 | struct edma_cc *ecc = echan->ecc; |
| 580 | int channel = EDMA_CHAN_SLOT(echan->ch_num); |
| 581 | int j = (channel >> 5); |
| 582 | unsigned int mask = BIT(channel & 0x1f); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 583 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 584 | if (!echan->hw_triggered) { |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 585 | /* EDMA channels without event association */ |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 586 | dev_dbg(ecc->dev, "ESR%d %08x\n", j, |
| 587 | edma_shadow0_read_array(ecc, SH_ESR, j)); |
| 588 | edma_shadow0_write_array(ecc, SH_ESR, j, mask); |
| 589 | } else { |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 590 | /* EDMA channel with event association */ |
Peter Ujfalusi | 3287fb4 | 2015-10-14 14:42:57 +0300 | [diff] [blame] | 591 | dev_dbg(ecc->dev, "ER%d %08x\n", j, |
| 592 | edma_shadow0_read_array(ecc, SH_ER, j)); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 593 | /* Clear any pending event or error */ |
| 594 | edma_write_array(ecc, EDMA_ECR, j, mask); |
| 595 | edma_write_array(ecc, EDMA_EMCR, j, mask); |
| 596 | /* Clear any SER */ |
| 597 | edma_shadow0_write_array(ecc, SH_SECR, j, mask); |
| 598 | edma_shadow0_write_array(ecc, SH_EESR, j, mask); |
Peter Ujfalusi | 3287fb4 | 2015-10-14 14:42:57 +0300 | [diff] [blame] | 599 | dev_dbg(ecc->dev, "EER%d %08x\n", j, |
| 600 | edma_shadow0_read_array(ecc, SH_EER, j)); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 601 | } |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 602 | } |
| 603 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 604 | static void edma_stop(struct edma_chan *echan) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 605 | { |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 606 | struct edma_cc *ecc = echan->ecc; |
| 607 | int channel = EDMA_CHAN_SLOT(echan->ch_num); |
| 608 | int j = (channel >> 5); |
| 609 | unsigned int mask = BIT(channel & 0x1f); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 610 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 611 | edma_shadow0_write_array(ecc, SH_EECR, j, mask); |
| 612 | edma_shadow0_write_array(ecc, SH_ECR, j, mask); |
| 613 | edma_shadow0_write_array(ecc, SH_SECR, j, mask); |
| 614 | edma_write_array(ecc, EDMA_EMCR, j, mask); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 615 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 616 | /* clear possibly pending completion interrupt */ |
| 617 | edma_shadow0_write_array(ecc, SH_ICR, j, mask); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 618 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 619 | dev_dbg(ecc->dev, "EER%d %08x\n", j, |
| 620 | edma_shadow0_read_array(ecc, SH_EER, j)); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 621 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 622 | /* REVISIT: consider guarding against inappropriate event |
| 623 | * chaining by overwriting with dummy_paramset. |
| 624 | */ |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 625 | } |
| 626 | |
Peter Ujfalusi | 11c1573 | 2015-10-14 14:43:00 +0300 | [diff] [blame] | 627 | /* |
| 628 | * Temporarily disable EDMA hardware events on the specified channel, |
| 629 | * preventing them from triggering new transfers |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 630 | */ |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 631 | static void edma_pause(struct edma_chan *echan) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 632 | { |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 633 | int channel = EDMA_CHAN_SLOT(echan->ch_num); |
| 634 | unsigned int mask = BIT(channel & 0x1f); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 635 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 636 | edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 637 | } |
| 638 | |
Peter Ujfalusi | 11c1573 | 2015-10-14 14:43:00 +0300 | [diff] [blame] | 639 | /* Re-enable EDMA hardware events on the specified channel. */ |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 640 | static void edma_resume(struct edma_chan *echan) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 641 | { |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 642 | int channel = EDMA_CHAN_SLOT(echan->ch_num); |
| 643 | unsigned int mask = BIT(channel & 0x1f); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 644 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 645 | edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 646 | } |
| 647 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 648 | static void edma_trigger_channel(struct edma_chan *echan) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 649 | { |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 650 | struct edma_cc *ecc = echan->ecc; |
| 651 | int channel = EDMA_CHAN_SLOT(echan->ch_num); |
| 652 | unsigned int mask = BIT(channel & 0x1f); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 653 | |
| 654 | edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); |
| 655 | |
Peter Ujfalusi | 3287fb4 | 2015-10-14 14:42:57 +0300 | [diff] [blame] | 656 | dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5), |
| 657 | edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 658 | } |
| 659 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 660 | static void edma_clean_channel(struct edma_chan *echan) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 661 | { |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 662 | struct edma_cc *ecc = echan->ecc; |
| 663 | int channel = EDMA_CHAN_SLOT(echan->ch_num); |
| 664 | int j = (channel >> 5); |
| 665 | unsigned int mask = BIT(channel & 0x1f); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 666 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 667 | dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j)); |
| 668 | edma_shadow0_write_array(ecc, SH_ECR, j, mask); |
| 669 | /* Clear the corresponding EMR bits */ |
| 670 | edma_write_array(ecc, EDMA_EMCR, j, mask); |
| 671 | /* Clear any SER */ |
| 672 | edma_shadow0_write_array(ecc, SH_SECR, j, mask); |
| 673 | edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 674 | } |
| 675 | |
Peter Ujfalusi | f9425de | 2015-10-16 10:18:03 +0300 | [diff] [blame] | 676 | /* Move channel to a specific event queue */ |
| 677 | static void edma_assign_channel_eventq(struct edma_chan *echan, |
| 678 | enum dma_event_q eventq_no) |
| 679 | { |
| 680 | struct edma_cc *ecc = echan->ecc; |
| 681 | int channel = EDMA_CHAN_SLOT(echan->ch_num); |
| 682 | int bit = (channel & 0x7) * 4; |
| 683 | |
| 684 | /* default to low priority queue */ |
| 685 | if (eventq_no == EVENTQ_DEFAULT) |
| 686 | eventq_no = ecc->default_queue; |
| 687 | if (eventq_no >= ecc->num_tc) |
| 688 | return; |
| 689 | |
| 690 | eventq_no &= 7; |
| 691 | edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), |
| 692 | eventq_no << bit); |
| 693 | } |
| 694 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 695 | static int edma_alloc_channel(struct edma_chan *echan, |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 696 | enum dma_event_q eventq_no) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 697 | { |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 698 | struct edma_cc *ecc = echan->ecc; |
| 699 | int channel = EDMA_CHAN_SLOT(echan->ch_num); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 700 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 701 | /* ensure access through shadow region 0 */ |
| 702 | edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); |
| 703 | |
| 704 | /* ensure no events are pending */ |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 705 | edma_stop(echan); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 706 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 707 | edma_setup_interrupt(echan, true); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 708 | |
Peter Ujfalusi | f9425de | 2015-10-16 10:18:03 +0300 | [diff] [blame] | 709 | edma_assign_channel_eventq(echan, eventq_no); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 710 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 711 | return 0; |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 712 | } |
| 713 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 714 | static void edma_free_channel(struct edma_chan *echan) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 715 | { |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 716 | /* ensure no events are pending */ |
| 717 | edma_stop(echan); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 718 | /* REVISIT should probably take out of shadow region 0 */ |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 719 | edma_setup_interrupt(echan, false); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 720 | } |
| 721 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 722 | static inline struct edma_cc *to_edma_cc(struct dma_device *d) |
| 723 | { |
| 724 | return container_of(d, struct edma_cc, dma_slave); |
| 725 | } |
| 726 | |
| 727 | static inline struct edma_chan *to_edma_chan(struct dma_chan *c) |
| 728 | { |
| 729 | return container_of(c, struct edma_chan, vchan.chan); |
| 730 | } |
| 731 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 732 | static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx) |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 733 | { |
| 734 | return container_of(tx, struct edma_desc, vdesc.tx); |
| 735 | } |
| 736 | |
| 737 | static void edma_desc_free(struct virt_dma_desc *vdesc) |
| 738 | { |
| 739 | kfree(container_of(vdesc, struct edma_desc, vdesc)); |
| 740 | } |
| 741 | |
| 742 | /* Dispatch a queued descriptor to the controller (caller holds lock) */ |
| 743 | static void edma_execute(struct edma_chan *echan) |
| 744 | { |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 745 | struct edma_cc *ecc = echan->ecc; |
Joel Fernandes | 5340706 | 2013-09-03 10:02:46 -0500 | [diff] [blame] | 746 | struct virt_dma_desc *vdesc; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 747 | struct edma_desc *edesc; |
Joel Fernandes | 5340706 | 2013-09-03 10:02:46 -0500 | [diff] [blame] | 748 | struct device *dev = echan->vchan.chan.device->dev; |
| 749 | int i, j, left, nslots; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 750 | |
Peter Ujfalusi | 8fa7ff4 | 2015-10-14 14:42:45 +0300 | [diff] [blame] | 751 | if (!echan->edesc) { |
| 752 | /* Setup is needed for the first transfer */ |
Joel Fernandes | 5340706 | 2013-09-03 10:02:46 -0500 | [diff] [blame] | 753 | vdesc = vchan_next_desc(&echan->vchan); |
Peter Ujfalusi | 8fa7ff4 | 2015-10-14 14:42:45 +0300 | [diff] [blame] | 754 | if (!vdesc) |
Joel Fernandes | 5340706 | 2013-09-03 10:02:46 -0500 | [diff] [blame] | 755 | return; |
Joel Fernandes | 5340706 | 2013-09-03 10:02:46 -0500 | [diff] [blame] | 756 | list_del(&vdesc->node); |
| 757 | echan->edesc = to_edma_desc(&vdesc->tx); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 758 | } |
| 759 | |
Joel Fernandes | 5340706 | 2013-09-03 10:02:46 -0500 | [diff] [blame] | 760 | edesc = echan->edesc; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 761 | |
Joel Fernandes | 5340706 | 2013-09-03 10:02:46 -0500 | [diff] [blame] | 762 | /* Find out how many left */ |
| 763 | left = edesc->pset_nr - edesc->processed; |
| 764 | nslots = min(MAX_NR_SG, left); |
Thomas Gleixner | 740b41f | 2014-04-28 14:34:11 -0500 | [diff] [blame] | 765 | edesc->sg_len = 0; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 766 | |
| 767 | /* Write descriptor PaRAM set(s) */ |
Joel Fernandes | 5340706 | 2013-09-03 10:02:46 -0500 | [diff] [blame] | 768 | for (i = 0; i < nslots; i++) { |
| 769 | j = i + edesc->processed; |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 770 | edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param); |
Thomas Gleixner | 740b41f | 2014-04-28 14:34:11 -0500 | [diff] [blame] | 771 | edesc->sg_len += edesc->pset[j].len; |
Peter Ujfalusi | 907f74a | 2015-10-14 14:42:56 +0300 | [diff] [blame] | 772 | dev_vdbg(dev, |
| 773 | "\n pset[%d]:\n" |
| 774 | " chnum\t%d\n" |
| 775 | " slot\t%d\n" |
| 776 | " opt\t%08x\n" |
| 777 | " src\t%08x\n" |
| 778 | " dst\t%08x\n" |
| 779 | " abcnt\t%08x\n" |
| 780 | " ccnt\t%08x\n" |
| 781 | " bidx\t%08x\n" |
| 782 | " cidx\t%08x\n" |
| 783 | " lkrld\t%08x\n", |
| 784 | j, echan->ch_num, echan->slot[i], |
| 785 | edesc->pset[j].param.opt, |
| 786 | edesc->pset[j].param.src, |
| 787 | edesc->pset[j].param.dst, |
| 788 | edesc->pset[j].param.a_b_cnt, |
| 789 | edesc->pset[j].param.ccnt, |
| 790 | edesc->pset[j].param.src_dst_bidx, |
| 791 | edesc->pset[j].param.src_dst_cidx, |
| 792 | edesc->pset[j].param.link_bcntrld); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 793 | /* Link to the previous slot if not the last set */ |
Joel Fernandes | 5340706 | 2013-09-03 10:02:46 -0500 | [diff] [blame] | 794 | if (i != (nslots - 1)) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 795 | edma_link(ecc, echan->slot[i], echan->slot[i + 1]); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 796 | } |
| 797 | |
Joel Fernandes | 5340706 | 2013-09-03 10:02:46 -0500 | [diff] [blame] | 798 | edesc->processed += nslots; |
| 799 | |
Joel Fernandes | b267b3b | 2013-08-29 18:05:44 -0500 | [diff] [blame] | 800 | /* |
| 801 | * If this is either the last set in a set of SG-list transactions |
| 802 | * then setup a link to the dummy slot, this results in all future |
| 803 | * events being absorbed and that's OK because we're done |
| 804 | */ |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 805 | if (edesc->processed == edesc->pset_nr) { |
| 806 | if (edesc->cyclic) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 807 | edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]); |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 808 | else |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 809 | edma_link(ecc, echan->slot[nslots - 1], |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 810 | echan->ecc->dummy_slot); |
| 811 | } |
Joel Fernandes | b267b3b | 2013-08-29 18:05:44 -0500 | [diff] [blame] | 812 | |
Peter Ujfalusi | 8fa7ff4 | 2015-10-14 14:42:45 +0300 | [diff] [blame] | 813 | if (echan->missed) { |
| 814 | /* |
| 815 | * This happens due to setup times between intermediate |
| 816 | * transfers in long SG lists which have to be broken up into |
| 817 | * transfers of MAX_NR_SG |
| 818 | */ |
| 819 | dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 820 | edma_clean_channel(echan); |
| 821 | edma_stop(echan); |
| 822 | edma_start(echan); |
| 823 | edma_trigger_channel(echan); |
Peter Ujfalusi | 8fa7ff4 | 2015-10-14 14:42:45 +0300 | [diff] [blame] | 824 | echan->missed = 0; |
| 825 | } else if (edesc->processed <= MAX_NR_SG) { |
Peter Ujfalusi | 9aac909 | 2014-04-24 10:29:50 +0300 | [diff] [blame] | 826 | dev_dbg(dev, "first transfer starting on channel %d\n", |
| 827 | echan->ch_num); |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 828 | edma_start(echan); |
Sekhar Nori | 5fc68a6 | 2014-03-19 11:25:50 +0530 | [diff] [blame] | 829 | } else { |
| 830 | dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", |
| 831 | echan->ch_num, edesc->processed); |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 832 | edma_resume(echan); |
Joel Fernandes | 5340706 | 2013-09-03 10:02:46 -0500 | [diff] [blame] | 833 | } |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 834 | } |
| 835 | |
Maxime Ripard | aa7c09b | 2014-11-17 14:42:13 +0100 | [diff] [blame] | 836 | static int edma_terminate_all(struct dma_chan *chan) |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 837 | { |
Maxime Ripard | aa7c09b | 2014-11-17 14:42:13 +0100 | [diff] [blame] | 838 | struct edma_chan *echan = to_edma_chan(chan); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 839 | unsigned long flags; |
| 840 | LIST_HEAD(head); |
| 841 | |
| 842 | spin_lock_irqsave(&echan->vchan.lock, flags); |
| 843 | |
| 844 | /* |
| 845 | * Stop DMA activity: we assume the callback will not be called |
| 846 | * after edma_dma() returns (even if it does, it will see |
| 847 | * echan->edesc is NULL and exit.) |
| 848 | */ |
| 849 | if (echan->edesc) { |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 850 | edma_stop(echan); |
Peter Ujfalusi | 8fa7ff4 | 2015-10-14 14:42:45 +0300 | [diff] [blame] | 851 | /* Move the cyclic channel back to default queue */ |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 852 | if (!echan->tc && echan->edesc->cyclic) |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 853 | edma_assign_channel_eventq(echan, EVENTQ_DEFAULT); |
Petr Kulhavy | 5ca9e7c | 2015-03-27 13:35:51 +0200 | [diff] [blame] | 854 | /* |
| 855 | * free the running request descriptor |
| 856 | * since it is not in any of the vdesc lists |
| 857 | */ |
| 858 | edma_desc_free(&echan->edesc->vdesc); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 859 | echan->edesc = NULL; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 860 | } |
| 861 | |
| 862 | vchan_get_all_descriptors(&echan->vchan, &head); |
| 863 | spin_unlock_irqrestore(&echan->vchan.lock, flags); |
| 864 | vchan_dma_desc_free_list(&echan->vchan, &head); |
| 865 | |
| 866 | return 0; |
| 867 | } |
| 868 | |
Maxime Ripard | aa7c09b | 2014-11-17 14:42:13 +0100 | [diff] [blame] | 869 | static int edma_slave_config(struct dma_chan *chan, |
Matt Porter | 661f7cb | 2013-01-10 13:41:04 -0500 | [diff] [blame] | 870 | struct dma_slave_config *cfg) |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 871 | { |
Maxime Ripard | aa7c09b | 2014-11-17 14:42:13 +0100 | [diff] [blame] | 872 | struct edma_chan *echan = to_edma_chan(chan); |
| 873 | |
Matt Porter | 661f7cb | 2013-01-10 13:41:04 -0500 | [diff] [blame] | 874 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
| 875 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 876 | return -EINVAL; |
| 877 | |
Matt Porter | 661f7cb | 2013-01-10 13:41:04 -0500 | [diff] [blame] | 878 | memcpy(&echan->cfg, cfg, sizeof(echan->cfg)); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 879 | |
| 880 | return 0; |
| 881 | } |
| 882 | |
Maxime Ripard | aa7c09b | 2014-11-17 14:42:13 +0100 | [diff] [blame] | 883 | static int edma_dma_pause(struct dma_chan *chan) |
Peter Ujfalusi | 72c7b67 | 2014-04-14 14:41:59 +0300 | [diff] [blame] | 884 | { |
Maxime Ripard | aa7c09b | 2014-11-17 14:42:13 +0100 | [diff] [blame] | 885 | struct edma_chan *echan = to_edma_chan(chan); |
| 886 | |
John Ogness | 02ec604 | 2015-04-27 13:52:25 +0200 | [diff] [blame] | 887 | if (!echan->edesc) |
Peter Ujfalusi | 72c7b67 | 2014-04-14 14:41:59 +0300 | [diff] [blame] | 888 | return -EINVAL; |
| 889 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 890 | edma_pause(echan); |
Peter Ujfalusi | 72c7b67 | 2014-04-14 14:41:59 +0300 | [diff] [blame] | 891 | return 0; |
| 892 | } |
| 893 | |
Maxime Ripard | aa7c09b | 2014-11-17 14:42:13 +0100 | [diff] [blame] | 894 | static int edma_dma_resume(struct dma_chan *chan) |
Peter Ujfalusi | 72c7b67 | 2014-04-14 14:41:59 +0300 | [diff] [blame] | 895 | { |
Maxime Ripard | aa7c09b | 2014-11-17 14:42:13 +0100 | [diff] [blame] | 896 | struct edma_chan *echan = to_edma_chan(chan); |
| 897 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 898 | edma_resume(echan); |
Peter Ujfalusi | 72c7b67 | 2014-04-14 14:41:59 +0300 | [diff] [blame] | 899 | return 0; |
| 900 | } |
| 901 | |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 902 | /* |
| 903 | * A PaRAM set configuration abstraction used by other modes |
| 904 | * @chan: Channel who's PaRAM set we're configuring |
| 905 | * @pset: PaRAM set to initialize and setup. |
| 906 | * @src_addr: Source address of the DMA |
| 907 | * @dst_addr: Destination address of the DMA |
| 908 | * @burst: In units of dev_width, how much to send |
| 909 | * @dev_width: How much is the dev_width |
| 910 | * @dma_length: Total length of the DMA transfer |
| 911 | * @direction: Direction of the transfer |
| 912 | */ |
Thomas Gleixner | b5088ad | 2014-04-28 14:23:55 -0500 | [diff] [blame] | 913 | static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset, |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 914 | dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, |
Peter Ujfalusi | df6694f | 2015-10-16 10:18:00 +0300 | [diff] [blame] | 915 | unsigned int acnt, unsigned int dma_length, |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 916 | enum dma_transfer_direction direction) |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 917 | { |
| 918 | struct edma_chan *echan = to_edma_chan(chan); |
| 919 | struct device *dev = chan->device->dev; |
Thomas Gleixner | b5088ad | 2014-04-28 14:23:55 -0500 | [diff] [blame] | 920 | struct edmacc_param *param = &epset->param; |
Peter Ujfalusi | df6694f | 2015-10-16 10:18:00 +0300 | [diff] [blame] | 921 | int bcnt, ccnt, cidx; |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 922 | int src_bidx, dst_bidx, src_cidx, dst_cidx; |
| 923 | int absync; |
| 924 | |
Peter Ujfalusi | b2b617d | 2014-04-14 14:41:58 +0300 | [diff] [blame] | 925 | /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */ |
| 926 | if (!burst) |
| 927 | burst = 1; |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 928 | /* |
| 929 | * If the maxburst is equal to the fifo width, use |
| 930 | * A-synced transfers. This allows for large contiguous |
| 931 | * buffer transfers using only one PaRAM set. |
| 932 | */ |
| 933 | if (burst == 1) { |
| 934 | /* |
| 935 | * For the A-sync case, bcnt and ccnt are the remainder |
| 936 | * and quotient respectively of the division of: |
| 937 | * (dma_length / acnt) by (SZ_64K -1). This is so |
| 938 | * that in case bcnt over flows, we have ccnt to use. |
| 939 | * Note: In A-sync tranfer only, bcntrld is used, but it |
| 940 | * only applies for sg_dma_len(sg) >= SZ_64K. |
| 941 | * In this case, the best way adopted is- bccnt for the |
| 942 | * first frame will be the remainder below. Then for |
| 943 | * every successive frame, bcnt will be SZ_64K-1. This |
| 944 | * is assured as bcntrld = 0xffff in end of function. |
| 945 | */ |
| 946 | absync = false; |
| 947 | ccnt = dma_length / acnt / (SZ_64K - 1); |
| 948 | bcnt = dma_length / acnt - ccnt * (SZ_64K - 1); |
| 949 | /* |
| 950 | * If bcnt is non-zero, we have a remainder and hence an |
| 951 | * extra frame to transfer, so increment ccnt. |
| 952 | */ |
| 953 | if (bcnt) |
| 954 | ccnt++; |
| 955 | else |
| 956 | bcnt = SZ_64K - 1; |
| 957 | cidx = acnt; |
| 958 | } else { |
| 959 | /* |
| 960 | * If maxburst is greater than the fifo address_width, |
| 961 | * use AB-synced transfers where A count is the fifo |
| 962 | * address_width and B count is the maxburst. In this |
| 963 | * case, we are limited to transfers of C count frames |
| 964 | * of (address_width * maxburst) where C count is limited |
| 965 | * to SZ_64K-1. This places an upper bound on the length |
| 966 | * of an SG segment that can be handled. |
| 967 | */ |
| 968 | absync = true; |
| 969 | bcnt = burst; |
| 970 | ccnt = dma_length / (acnt * bcnt); |
| 971 | if (ccnt > (SZ_64K - 1)) { |
| 972 | dev_err(dev, "Exceeded max SG segment size\n"); |
| 973 | return -EINVAL; |
| 974 | } |
| 975 | cidx = acnt * bcnt; |
| 976 | } |
| 977 | |
Thomas Gleixner | c2da234 | 2014-04-28 14:29:57 -0500 | [diff] [blame] | 978 | epset->len = dma_length; |
| 979 | |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 980 | if (direction == DMA_MEM_TO_DEV) { |
| 981 | src_bidx = acnt; |
| 982 | src_cidx = cidx; |
| 983 | dst_bidx = 0; |
| 984 | dst_cidx = 0; |
Thomas Gleixner | c2da234 | 2014-04-28 14:29:57 -0500 | [diff] [blame] | 985 | epset->addr = src_addr; |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 986 | } else if (direction == DMA_DEV_TO_MEM) { |
| 987 | src_bidx = 0; |
| 988 | src_cidx = 0; |
| 989 | dst_bidx = acnt; |
| 990 | dst_cidx = cidx; |
Thomas Gleixner | c2da234 | 2014-04-28 14:29:57 -0500 | [diff] [blame] | 991 | epset->addr = dst_addr; |
Joel Fernandes | 8cc3e30 | 2014-04-18 21:50:33 -0500 | [diff] [blame] | 992 | } else if (direction == DMA_MEM_TO_MEM) { |
| 993 | src_bidx = acnt; |
| 994 | src_cidx = cidx; |
| 995 | dst_bidx = acnt; |
| 996 | dst_cidx = cidx; |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 997 | } else { |
| 998 | dev_err(dev, "%s: direction not implemented yet\n", __func__); |
| 999 | return -EINVAL; |
| 1000 | } |
| 1001 | |
Thomas Gleixner | b5088ad | 2014-04-28 14:23:55 -0500 | [diff] [blame] | 1002 | param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num)); |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 1003 | /* Configure A or AB synchronized transfers */ |
| 1004 | if (absync) |
Thomas Gleixner | b5088ad | 2014-04-28 14:23:55 -0500 | [diff] [blame] | 1005 | param->opt |= SYNCDIM; |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 1006 | |
Thomas Gleixner | b5088ad | 2014-04-28 14:23:55 -0500 | [diff] [blame] | 1007 | param->src = src_addr; |
| 1008 | param->dst = dst_addr; |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 1009 | |
Thomas Gleixner | b5088ad | 2014-04-28 14:23:55 -0500 | [diff] [blame] | 1010 | param->src_dst_bidx = (dst_bidx << 16) | src_bidx; |
| 1011 | param->src_dst_cidx = (dst_cidx << 16) | src_cidx; |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 1012 | |
Thomas Gleixner | b5088ad | 2014-04-28 14:23:55 -0500 | [diff] [blame] | 1013 | param->a_b_cnt = bcnt << 16 | acnt; |
| 1014 | param->ccnt = ccnt; |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 1015 | /* |
| 1016 | * Only time when (bcntrld) auto reload is required is for |
| 1017 | * A-sync case, and in this case, a requirement of reload value |
| 1018 | * of SZ_64K-1 only is assured. 'link' is initially set to NULL |
| 1019 | * and then later will be populated by edma_execute. |
| 1020 | */ |
Thomas Gleixner | b5088ad | 2014-04-28 14:23:55 -0500 | [diff] [blame] | 1021 | param->link_bcntrld = 0xffffffff; |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 1022 | return absync; |
| 1023 | } |
| 1024 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1025 | static struct dma_async_tx_descriptor *edma_prep_slave_sg( |
| 1026 | struct dma_chan *chan, struct scatterlist *sgl, |
| 1027 | unsigned int sg_len, enum dma_transfer_direction direction, |
| 1028 | unsigned long tx_flags, void *context) |
| 1029 | { |
| 1030 | struct edma_chan *echan = to_edma_chan(chan); |
| 1031 | struct device *dev = chan->device->dev; |
| 1032 | struct edma_desc *edesc; |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 1033 | dma_addr_t src_addr = 0, dst_addr = 0; |
Matt Porter | 661f7cb | 2013-01-10 13:41:04 -0500 | [diff] [blame] | 1034 | enum dma_slave_buswidth dev_width; |
| 1035 | u32 burst; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1036 | struct scatterlist *sg; |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 1037 | int i, nslots, ret; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1038 | |
| 1039 | if (unlikely(!echan || !sgl || !sg_len)) |
| 1040 | return NULL; |
| 1041 | |
Matt Porter | 661f7cb | 2013-01-10 13:41:04 -0500 | [diff] [blame] | 1042 | if (direction == DMA_DEV_TO_MEM) { |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 1043 | src_addr = echan->cfg.src_addr; |
Matt Porter | 661f7cb | 2013-01-10 13:41:04 -0500 | [diff] [blame] | 1044 | dev_width = echan->cfg.src_addr_width; |
| 1045 | burst = echan->cfg.src_maxburst; |
| 1046 | } else if (direction == DMA_MEM_TO_DEV) { |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 1047 | dst_addr = echan->cfg.dst_addr; |
Matt Porter | 661f7cb | 2013-01-10 13:41:04 -0500 | [diff] [blame] | 1048 | dev_width = echan->cfg.dst_addr_width; |
| 1049 | burst = echan->cfg.dst_maxburst; |
| 1050 | } else { |
Peter Ujfalusi | e6fad59 | 2014-04-14 14:42:05 +0300 | [diff] [blame] | 1051 | dev_err(dev, "%s: bad direction: %d\n", __func__, direction); |
Matt Porter | 661f7cb | 2013-01-10 13:41:04 -0500 | [diff] [blame] | 1052 | return NULL; |
| 1053 | } |
| 1054 | |
| 1055 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { |
Peter Ujfalusi | c594c89 | 2014-04-14 14:42:03 +0300 | [diff] [blame] | 1056 | dev_err(dev, "%s: Undefined slave buswidth\n", __func__); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1057 | return NULL; |
| 1058 | } |
| 1059 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1060 | edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]), |
| 1061 | GFP_ATOMIC); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1062 | if (!edesc) { |
Peter Ujfalusi | c594c89 | 2014-04-14 14:42:03 +0300 | [diff] [blame] | 1063 | dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1064 | return NULL; |
| 1065 | } |
| 1066 | |
| 1067 | edesc->pset_nr = sg_len; |
Thomas Gleixner | b6205c3 | 2014-04-28 14:18:45 -0500 | [diff] [blame] | 1068 | edesc->residue = 0; |
Thomas Gleixner | c2da234 | 2014-04-28 14:29:57 -0500 | [diff] [blame] | 1069 | edesc->direction = direction; |
Thomas Gleixner | 740b41f | 2014-04-28 14:34:11 -0500 | [diff] [blame] | 1070 | edesc->echan = echan; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1071 | |
Joel Fernandes | 6fbe24d | 2013-08-29 18:05:40 -0500 | [diff] [blame] | 1072 | /* Allocate a PaRAM slot, if needed */ |
| 1073 | nslots = min_t(unsigned, MAX_NR_SG, sg_len); |
| 1074 | |
| 1075 | for (i = 0; i < nslots; i++) { |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1076 | if (echan->slot[i] < 0) { |
| 1077 | echan->slot[i] = |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1078 | edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1079 | if (echan->slot[i] < 0) { |
Valentin Ilie | 4b6271a | 2013-10-24 16:14:22 +0300 | [diff] [blame] | 1080 | kfree(edesc); |
Peter Ujfalusi | c594c89 | 2014-04-14 14:42:03 +0300 | [diff] [blame] | 1081 | dev_err(dev, "%s: Failed to allocate slot\n", |
| 1082 | __func__); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1083 | return NULL; |
| 1084 | } |
| 1085 | } |
Joel Fernandes | 6fbe24d | 2013-08-29 18:05:40 -0500 | [diff] [blame] | 1086 | } |
| 1087 | |
| 1088 | /* Configure PaRAM sets for each SG */ |
| 1089 | for_each_sg(sgl, sg, sg_len, i) { |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 1090 | /* Get address for each SG */ |
| 1091 | if (direction == DMA_DEV_TO_MEM) |
| 1092 | dst_addr = sg_dma_address(sg); |
| 1093 | else |
| 1094 | src_addr = sg_dma_address(sg); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1095 | |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 1096 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, |
| 1097 | dst_addr, burst, dev_width, |
| 1098 | sg_dma_len(sg), direction); |
Vinod Koul | b967aec | 2013-10-30 13:07:18 +0530 | [diff] [blame] | 1099 | if (ret < 0) { |
| 1100 | kfree(edesc); |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 1101 | return NULL; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1102 | } |
| 1103 | |
Joel Fernandes | fd00903 | 2013-09-23 18:05:13 -0500 | [diff] [blame] | 1104 | edesc->absync = ret; |
Thomas Gleixner | b6205c3 | 2014-04-28 14:18:45 -0500 | [diff] [blame] | 1105 | edesc->residue += sg_dma_len(sg); |
Joel Fernandes | 6fbe24d | 2013-08-29 18:05:40 -0500 | [diff] [blame] | 1106 | |
| 1107 | /* If this is the last in a current SG set of transactions, |
| 1108 | enable interrupts so that next set is processed */ |
| 1109 | if (!((i+1) % MAX_NR_SG)) |
Thomas Gleixner | b5088ad | 2014-04-28 14:23:55 -0500 | [diff] [blame] | 1110 | edesc->pset[i].param.opt |= TCINTEN; |
Joel Fernandes | 6fbe24d | 2013-08-29 18:05:40 -0500 | [diff] [blame] | 1111 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1112 | /* If this is the last set, enable completion interrupt flag */ |
| 1113 | if (i == sg_len - 1) |
Thomas Gleixner | b5088ad | 2014-04-28 14:23:55 -0500 | [diff] [blame] | 1114 | edesc->pset[i].param.opt |= TCINTEN; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1115 | } |
Thomas Gleixner | 740b41f | 2014-04-28 14:34:11 -0500 | [diff] [blame] | 1116 | edesc->residue_stat = edesc->residue; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1117 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1118 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); |
| 1119 | } |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1120 | |
Lad, Prabhakar | b7a4fd5 | 2015-02-04 13:03:27 +0000 | [diff] [blame] | 1121 | static struct dma_async_tx_descriptor *edma_prep_dma_memcpy( |
Joel Fernandes | 8cc3e30 | 2014-04-18 21:50:33 -0500 | [diff] [blame] | 1122 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
| 1123 | size_t len, unsigned long tx_flags) |
| 1124 | { |
Peter Ujfalusi | df6694f | 2015-10-16 10:18:00 +0300 | [diff] [blame] | 1125 | int ret, nslots; |
Joel Fernandes | 8cc3e30 | 2014-04-18 21:50:33 -0500 | [diff] [blame] | 1126 | struct edma_desc *edesc; |
| 1127 | struct device *dev = chan->device->dev; |
| 1128 | struct edma_chan *echan = to_edma_chan(chan); |
Peter Ujfalusi | df6694f | 2015-10-16 10:18:00 +0300 | [diff] [blame] | 1129 | unsigned int width, pset_len; |
Joel Fernandes | 8cc3e30 | 2014-04-18 21:50:33 -0500 | [diff] [blame] | 1130 | |
| 1131 | if (unlikely(!echan || !len)) |
| 1132 | return NULL; |
| 1133 | |
Peter Ujfalusi | df6694f | 2015-10-16 10:18:00 +0300 | [diff] [blame] | 1134 | if (len < SZ_64K) { |
| 1135 | /* |
| 1136 | * Transfer size less than 64K can be handled with one paRAM |
| 1137 | * slot and with one burst. |
| 1138 | * ACNT = length |
| 1139 | */ |
| 1140 | width = len; |
| 1141 | pset_len = len; |
| 1142 | nslots = 1; |
| 1143 | } else { |
| 1144 | /* |
| 1145 | * Transfer size bigger than 64K will be handled with maximum of |
| 1146 | * two paRAM slots. |
| 1147 | * slot1: (full_length / 32767) times 32767 bytes bursts. |
| 1148 | * ACNT = 32767, length1: (full_length / 32767) * 32767 |
| 1149 | * slot2: the remaining amount of data after slot1. |
| 1150 | * ACNT = full_length - length1, length2 = ACNT |
| 1151 | * |
| 1152 | * When the full_length is multibple of 32767 one slot can be |
| 1153 | * used to complete the transfer. |
| 1154 | */ |
| 1155 | width = SZ_32K - 1; |
| 1156 | pset_len = rounddown(len, width); |
| 1157 | /* One slot is enough for lengths multiple of (SZ_32K -1) */ |
| 1158 | if (unlikely(pset_len == len)) |
| 1159 | nslots = 1; |
| 1160 | else |
| 1161 | nslots = 2; |
| 1162 | } |
| 1163 | |
| 1164 | edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]), |
| 1165 | GFP_ATOMIC); |
Joel Fernandes | 8cc3e30 | 2014-04-18 21:50:33 -0500 | [diff] [blame] | 1166 | if (!edesc) { |
| 1167 | dev_dbg(dev, "Failed to allocate a descriptor\n"); |
| 1168 | return NULL; |
| 1169 | } |
| 1170 | |
Peter Ujfalusi | df6694f | 2015-10-16 10:18:00 +0300 | [diff] [blame] | 1171 | edesc->pset_nr = nslots; |
| 1172 | edesc->residue = edesc->residue_stat = len; |
| 1173 | edesc->direction = DMA_MEM_TO_MEM; |
| 1174 | edesc->echan = echan; |
Peter Ujfalusi | 21a3184 | 2015-10-16 10:17:59 +0300 | [diff] [blame] | 1175 | |
Joel Fernandes | 8cc3e30 | 2014-04-18 21:50:33 -0500 | [diff] [blame] | 1176 | ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1, |
Peter Ujfalusi | df6694f | 2015-10-16 10:18:00 +0300 | [diff] [blame] | 1177 | width, pset_len, DMA_MEM_TO_MEM); |
| 1178 | if (ret < 0) { |
| 1179 | kfree(edesc); |
Joel Fernandes | 8cc3e30 | 2014-04-18 21:50:33 -0500 | [diff] [blame] | 1180 | return NULL; |
Peter Ujfalusi | df6694f | 2015-10-16 10:18:00 +0300 | [diff] [blame] | 1181 | } |
Joel Fernandes | 8cc3e30 | 2014-04-18 21:50:33 -0500 | [diff] [blame] | 1182 | |
| 1183 | edesc->absync = ret; |
| 1184 | |
Joel Fernandes | b0cce4c | 2014-04-28 15:30:32 -0500 | [diff] [blame] | 1185 | edesc->pset[0].param.opt |= ITCCHEN; |
Peter Ujfalusi | df6694f | 2015-10-16 10:18:00 +0300 | [diff] [blame] | 1186 | if (nslots == 1) { |
| 1187 | /* Enable transfer complete interrupt */ |
| 1188 | edesc->pset[0].param.opt |= TCINTEN; |
| 1189 | } else { |
| 1190 | /* Enable transfer complete chaining for the first slot */ |
| 1191 | edesc->pset[0].param.opt |= TCCHEN; |
| 1192 | |
| 1193 | if (echan->slot[1] < 0) { |
| 1194 | echan->slot[1] = edma_alloc_slot(echan->ecc, |
| 1195 | EDMA_SLOT_ANY); |
| 1196 | if (echan->slot[1] < 0) { |
| 1197 | kfree(edesc); |
| 1198 | dev_err(dev, "%s: Failed to allocate slot\n", |
| 1199 | __func__); |
| 1200 | return NULL; |
| 1201 | } |
| 1202 | } |
| 1203 | dest += pset_len; |
| 1204 | src += pset_len; |
| 1205 | pset_len = width = len % (SZ_32K - 1); |
| 1206 | |
| 1207 | ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1, |
| 1208 | width, pset_len, DMA_MEM_TO_MEM); |
| 1209 | if (ret < 0) { |
| 1210 | kfree(edesc); |
| 1211 | return NULL; |
| 1212 | } |
| 1213 | |
| 1214 | edesc->pset[1].param.opt |= ITCCHEN; |
| 1215 | edesc->pset[1].param.opt |= TCINTEN; |
| 1216 | } |
Joel Fernandes | 8cc3e30 | 2014-04-18 21:50:33 -0500 | [diff] [blame] | 1217 | |
| 1218 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); |
| 1219 | } |
| 1220 | |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1221 | static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( |
| 1222 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, |
| 1223 | size_t period_len, enum dma_transfer_direction direction, |
Laurent Pinchart | 31c1e5a | 2014-08-01 12:20:10 +0200 | [diff] [blame] | 1224 | unsigned long tx_flags) |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1225 | { |
| 1226 | struct edma_chan *echan = to_edma_chan(chan); |
| 1227 | struct device *dev = chan->device->dev; |
| 1228 | struct edma_desc *edesc; |
| 1229 | dma_addr_t src_addr, dst_addr; |
| 1230 | enum dma_slave_buswidth dev_width; |
| 1231 | u32 burst; |
| 1232 | int i, ret, nslots; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1233 | |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1234 | if (unlikely(!echan || !buf_len || !period_len)) |
| 1235 | return NULL; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1236 | |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1237 | if (direction == DMA_DEV_TO_MEM) { |
| 1238 | src_addr = echan->cfg.src_addr; |
| 1239 | dst_addr = buf_addr; |
| 1240 | dev_width = echan->cfg.src_addr_width; |
| 1241 | burst = echan->cfg.src_maxburst; |
| 1242 | } else if (direction == DMA_MEM_TO_DEV) { |
| 1243 | src_addr = buf_addr; |
| 1244 | dst_addr = echan->cfg.dst_addr; |
| 1245 | dev_width = echan->cfg.dst_addr_width; |
| 1246 | burst = echan->cfg.dst_maxburst; |
| 1247 | } else { |
Peter Ujfalusi | e6fad59 | 2014-04-14 14:42:05 +0300 | [diff] [blame] | 1248 | dev_err(dev, "%s: bad direction: %d\n", __func__, direction); |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1249 | return NULL; |
| 1250 | } |
| 1251 | |
| 1252 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { |
Peter Ujfalusi | c594c89 | 2014-04-14 14:42:03 +0300 | [diff] [blame] | 1253 | dev_err(dev, "%s: Undefined slave buswidth\n", __func__); |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1254 | return NULL; |
| 1255 | } |
| 1256 | |
| 1257 | if (unlikely(buf_len % period_len)) { |
| 1258 | dev_err(dev, "Period should be multiple of Buffer length\n"); |
| 1259 | return NULL; |
| 1260 | } |
| 1261 | |
| 1262 | nslots = (buf_len / period_len) + 1; |
| 1263 | |
| 1264 | /* |
| 1265 | * Cyclic DMA users such as audio cannot tolerate delays introduced |
| 1266 | * by cases where the number of periods is more than the maximum |
| 1267 | * number of SGs the EDMA driver can handle at a time. For DMA types |
| 1268 | * such as Slave SGs, such delays are tolerable and synchronized, |
| 1269 | * but the synchronization is difficult to achieve with Cyclic and |
| 1270 | * cannot be guaranteed, so we error out early. |
| 1271 | */ |
| 1272 | if (nslots > MAX_NR_SG) |
| 1273 | return NULL; |
| 1274 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1275 | edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]), |
| 1276 | GFP_ATOMIC); |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1277 | if (!edesc) { |
Peter Ujfalusi | c594c89 | 2014-04-14 14:42:03 +0300 | [diff] [blame] | 1278 | dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1279 | return NULL; |
| 1280 | } |
| 1281 | |
| 1282 | edesc->cyclic = 1; |
| 1283 | edesc->pset_nr = nslots; |
Thomas Gleixner | 740b41f | 2014-04-28 14:34:11 -0500 | [diff] [blame] | 1284 | edesc->residue = edesc->residue_stat = buf_len; |
Thomas Gleixner | c2da234 | 2014-04-28 14:29:57 -0500 | [diff] [blame] | 1285 | edesc->direction = direction; |
Thomas Gleixner | 740b41f | 2014-04-28 14:34:11 -0500 | [diff] [blame] | 1286 | edesc->echan = echan; |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1287 | |
Peter Ujfalusi | 83bb312 | 2014-04-14 14:42:02 +0300 | [diff] [blame] | 1288 | dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n", |
| 1289 | __func__, echan->ch_num, nslots, period_len, buf_len); |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1290 | |
| 1291 | for (i = 0; i < nslots; i++) { |
| 1292 | /* Allocate a PaRAM slot, if needed */ |
| 1293 | if (echan->slot[i] < 0) { |
| 1294 | echan->slot[i] = |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1295 | edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1296 | if (echan->slot[i] < 0) { |
Christian Engelmayer | e3ddc97 | 2013-12-30 20:48:39 +0100 | [diff] [blame] | 1297 | kfree(edesc); |
Peter Ujfalusi | c594c89 | 2014-04-14 14:42:03 +0300 | [diff] [blame] | 1298 | dev_err(dev, "%s: Failed to allocate slot\n", |
| 1299 | __func__); |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1300 | return NULL; |
| 1301 | } |
| 1302 | } |
| 1303 | |
| 1304 | if (i == nslots - 1) { |
| 1305 | memcpy(&edesc->pset[i], &edesc->pset[0], |
| 1306 | sizeof(edesc->pset[0])); |
| 1307 | break; |
| 1308 | } |
| 1309 | |
| 1310 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, |
| 1311 | dst_addr, burst, dev_width, period_len, |
| 1312 | direction); |
Christian Engelmayer | e3ddc97 | 2013-12-30 20:48:39 +0100 | [diff] [blame] | 1313 | if (ret < 0) { |
| 1314 | kfree(edesc); |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1315 | return NULL; |
Christian Engelmayer | e3ddc97 | 2013-12-30 20:48:39 +0100 | [diff] [blame] | 1316 | } |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1317 | |
| 1318 | if (direction == DMA_DEV_TO_MEM) |
| 1319 | dst_addr += period_len; |
| 1320 | else |
| 1321 | src_addr += period_len; |
| 1322 | |
Peter Ujfalusi | 83bb312 | 2014-04-14 14:42:02 +0300 | [diff] [blame] | 1323 | dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i); |
| 1324 | dev_vdbg(dev, |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1325 | "\n pset[%d]:\n" |
| 1326 | " chnum\t%d\n" |
| 1327 | " slot\t%d\n" |
| 1328 | " opt\t%08x\n" |
| 1329 | " src\t%08x\n" |
| 1330 | " dst\t%08x\n" |
| 1331 | " abcnt\t%08x\n" |
| 1332 | " ccnt\t%08x\n" |
| 1333 | " bidx\t%08x\n" |
| 1334 | " cidx\t%08x\n" |
| 1335 | " lkrld\t%08x\n", |
| 1336 | i, echan->ch_num, echan->slot[i], |
Thomas Gleixner | b5088ad | 2014-04-28 14:23:55 -0500 | [diff] [blame] | 1337 | edesc->pset[i].param.opt, |
| 1338 | edesc->pset[i].param.src, |
| 1339 | edesc->pset[i].param.dst, |
| 1340 | edesc->pset[i].param.a_b_cnt, |
| 1341 | edesc->pset[i].param.ccnt, |
| 1342 | edesc->pset[i].param.src_dst_bidx, |
| 1343 | edesc->pset[i].param.src_dst_cidx, |
| 1344 | edesc->pset[i].param.link_bcntrld); |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1345 | |
| 1346 | edesc->absync = ret; |
| 1347 | |
| 1348 | /* |
Peter Ujfalusi | a1f146f | 2014-07-16 15:29:21 +0300 | [diff] [blame] | 1349 | * Enable period interrupt only if it is requested |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1350 | */ |
Peter Ujfalusi | a1f146f | 2014-07-16 15:29:21 +0300 | [diff] [blame] | 1351 | if (tx_flags & DMA_PREP_INTERRUPT) |
| 1352 | edesc->pset[i].param.opt |= TCINTEN; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1353 | } |
| 1354 | |
Peter Ujfalusi | 8e8805d | 2014-07-08 13:46:38 +0300 | [diff] [blame] | 1355 | /* Place the cyclic channel to highest priority queue */ |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1356 | if (!echan->tc) |
| 1357 | edma_assign_channel_eventq(echan, EVENTQ_0); |
Peter Ujfalusi | 8e8805d | 2014-07-08 13:46:38 +0300 | [diff] [blame] | 1358 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1359 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); |
| 1360 | } |
| 1361 | |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1362 | static void edma_completion_handler(struct edma_chan *echan) |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1363 | { |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1364 | struct device *dev = echan->vchan.chan.device->dev; |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1365 | struct edma_desc *edesc = echan->edesc; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1366 | |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1367 | if (!edesc) |
| 1368 | return; |
Joel Fernandes | 50a9c70 | 2013-10-31 16:31:23 -0500 | [diff] [blame] | 1369 | |
Peter Ujfalusi | 8fa7ff4 | 2015-10-14 14:42:45 +0300 | [diff] [blame] | 1370 | spin_lock(&echan->vchan.lock); |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1371 | if (edesc->cyclic) { |
| 1372 | vchan_cyclic_callback(&edesc->vdesc); |
| 1373 | spin_unlock(&echan->vchan.lock); |
| 1374 | return; |
| 1375 | } else if (edesc->processed == edesc->pset_nr) { |
| 1376 | edesc->residue = 0; |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 1377 | edma_stop(echan); |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1378 | vchan_cookie_complete(&edesc->vdesc); |
| 1379 | echan->edesc = NULL; |
Thomas Gleixner | 740b41f | 2014-04-28 14:34:11 -0500 | [diff] [blame] | 1380 | |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1381 | dev_dbg(dev, "Transfer completed on channel %d\n", |
| 1382 | echan->ch_num); |
| 1383 | } else { |
| 1384 | dev_dbg(dev, "Sub transfer completed on channel %d\n", |
| 1385 | echan->ch_num); |
Peter Ujfalusi | 8fa7ff4 | 2015-10-14 14:42:45 +0300 | [diff] [blame] | 1386 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 1387 | edma_pause(echan); |
Joel Fernandes | c5f4799 | 2013-08-29 18:05:43 -0500 | [diff] [blame] | 1388 | |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1389 | /* Update statistics for tx_status */ |
| 1390 | edesc->residue -= edesc->sg_len; |
| 1391 | edesc->residue_stat = edesc->residue; |
| 1392 | edesc->processed_stat = edesc->processed; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1393 | } |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1394 | edma_execute(echan); |
| 1395 | |
Peter Ujfalusi | 8fa7ff4 | 2015-10-14 14:42:45 +0300 | [diff] [blame] | 1396 | spin_unlock(&echan->vchan.lock); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1397 | } |
| 1398 | |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1399 | /* eDMA interrupt handler */ |
| 1400 | static irqreturn_t dma_irq_handler(int irq, void *data) |
| 1401 | { |
| 1402 | struct edma_cc *ecc = data; |
| 1403 | int ctlr; |
| 1404 | u32 sh_ier; |
| 1405 | u32 sh_ipr; |
| 1406 | u32 bank; |
| 1407 | |
| 1408 | ctlr = ecc->id; |
| 1409 | if (ctlr < 0) |
| 1410 | return IRQ_NONE; |
| 1411 | |
| 1412 | dev_vdbg(ecc->dev, "dma_irq_handler\n"); |
| 1413 | |
| 1414 | sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0); |
| 1415 | if (!sh_ipr) { |
| 1416 | sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1); |
| 1417 | if (!sh_ipr) |
| 1418 | return IRQ_NONE; |
| 1419 | sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1); |
| 1420 | bank = 1; |
| 1421 | } else { |
| 1422 | sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0); |
| 1423 | bank = 0; |
| 1424 | } |
| 1425 | |
| 1426 | do { |
| 1427 | u32 slot; |
| 1428 | u32 channel; |
| 1429 | |
| 1430 | slot = __ffs(sh_ipr); |
| 1431 | sh_ipr &= ~(BIT(slot)); |
| 1432 | |
| 1433 | if (sh_ier & BIT(slot)) { |
| 1434 | channel = (bank << 5) | slot; |
| 1435 | /* Clear the corresponding IPR bits */ |
| 1436 | edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); |
| 1437 | edma_completion_handler(&ecc->slave_chans[channel]); |
| 1438 | } |
| 1439 | } while (sh_ipr); |
| 1440 | |
| 1441 | edma_shadow0_write(ecc, SH_IEVAL, 1); |
| 1442 | return IRQ_HANDLED; |
| 1443 | } |
| 1444 | |
| 1445 | static void edma_error_handler(struct edma_chan *echan) |
| 1446 | { |
| 1447 | struct edma_cc *ecc = echan->ecc; |
| 1448 | struct device *dev = echan->vchan.chan.device->dev; |
| 1449 | struct edmacc_param p; |
| 1450 | |
| 1451 | if (!echan->edesc) |
| 1452 | return; |
| 1453 | |
| 1454 | spin_lock(&echan->vchan.lock); |
| 1455 | |
| 1456 | edma_read_slot(ecc, echan->slot[0], &p); |
| 1457 | /* |
| 1458 | * Issue later based on missed flag which will be sure |
| 1459 | * to happen as: |
| 1460 | * (1) we finished transmitting an intermediate slot and |
| 1461 | * edma_execute is coming up. |
| 1462 | * (2) or we finished current transfer and issue will |
| 1463 | * call edma_execute. |
| 1464 | * |
| 1465 | * Important note: issuing can be dangerous here and |
| 1466 | * lead to some nasty recursion when we are in a NULL |
| 1467 | * slot. So we avoid doing so and set the missed flag. |
| 1468 | */ |
| 1469 | if (p.a_b_cnt == 0 && p.ccnt == 0) { |
| 1470 | dev_dbg(dev, "Error on null slot, setting miss\n"); |
| 1471 | echan->missed = 1; |
| 1472 | } else { |
| 1473 | /* |
| 1474 | * The slot is already programmed but the event got |
| 1475 | * missed, so its safe to issue it here. |
| 1476 | */ |
| 1477 | dev_dbg(dev, "Missed event, TRIGGERING\n"); |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 1478 | edma_clean_channel(echan); |
| 1479 | edma_stop(echan); |
| 1480 | edma_start(echan); |
| 1481 | edma_trigger_channel(echan); |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1482 | } |
| 1483 | spin_unlock(&echan->vchan.lock); |
| 1484 | } |
| 1485 | |
Peter Ujfalusi | 7c3b8b3 | 2015-10-14 14:43:02 +0300 | [diff] [blame] | 1486 | static inline bool edma_error_pending(struct edma_cc *ecc) |
| 1487 | { |
| 1488 | if (edma_read_array(ecc, EDMA_EMR, 0) || |
| 1489 | edma_read_array(ecc, EDMA_EMR, 1) || |
| 1490 | edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR)) |
| 1491 | return true; |
| 1492 | |
| 1493 | return false; |
| 1494 | } |
| 1495 | |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1496 | /* eDMA error interrupt handler */ |
| 1497 | static irqreturn_t dma_ccerr_handler(int irq, void *data) |
| 1498 | { |
| 1499 | struct edma_cc *ecc = data; |
Peter Ujfalusi | e4402a1 | 2015-10-14 14:43:03 +0300 | [diff] [blame] | 1500 | int i, j; |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1501 | int ctlr; |
| 1502 | unsigned int cnt = 0; |
Peter Ujfalusi | e4402a1 | 2015-10-14 14:43:03 +0300 | [diff] [blame] | 1503 | unsigned int val; |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1504 | |
| 1505 | ctlr = ecc->id; |
| 1506 | if (ctlr < 0) |
| 1507 | return IRQ_NONE; |
| 1508 | |
| 1509 | dev_vdbg(ecc->dev, "dma_ccerr_handler\n"); |
| 1510 | |
Peter Ujfalusi | 7c3b8b3 | 2015-10-14 14:43:02 +0300 | [diff] [blame] | 1511 | if (!edma_error_pending(ecc)) |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1512 | return IRQ_NONE; |
| 1513 | |
| 1514 | while (1) { |
Peter Ujfalusi | e4402a1 | 2015-10-14 14:43:03 +0300 | [diff] [blame] | 1515 | /* Event missed register(s) */ |
| 1516 | for (j = 0; j < 2; j++) { |
| 1517 | unsigned long emr; |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1518 | |
Peter Ujfalusi | e4402a1 | 2015-10-14 14:43:03 +0300 | [diff] [blame] | 1519 | val = edma_read_array(ecc, EDMA_EMR, j); |
| 1520 | if (!val) |
| 1521 | continue; |
| 1522 | |
| 1523 | dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val); |
| 1524 | emr = val; |
| 1525 | for (i = find_next_bit(&emr, 32, 0); i < 32; |
| 1526 | i = find_next_bit(&emr, 32, i + 1)) { |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1527 | int k = (j << 5) + i; |
| 1528 | |
Peter Ujfalusi | e4402a1 | 2015-10-14 14:43:03 +0300 | [diff] [blame] | 1529 | /* Clear the corresponding EMR bits */ |
| 1530 | edma_write_array(ecc, EDMA_EMCR, j, BIT(i)); |
| 1531 | /* Clear any SER */ |
| 1532 | edma_shadow0_write_array(ecc, SH_SECR, j, |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1533 | BIT(i)); |
Peter Ujfalusi | e4402a1 | 2015-10-14 14:43:03 +0300 | [diff] [blame] | 1534 | edma_error_handler(&ecc->slave_chans[k]); |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1535 | } |
| 1536 | } |
Peter Ujfalusi | e4402a1 | 2015-10-14 14:43:03 +0300 | [diff] [blame] | 1537 | |
| 1538 | val = edma_read(ecc, EDMA_QEMR); |
| 1539 | if (val) { |
| 1540 | dev_dbg(ecc->dev, "QEMR 0x%02x\n", val); |
| 1541 | /* Not reported, just clear the interrupt reason. */ |
| 1542 | edma_write(ecc, EDMA_QEMCR, val); |
| 1543 | edma_shadow0_write(ecc, SH_QSECR, val); |
| 1544 | } |
| 1545 | |
| 1546 | val = edma_read(ecc, EDMA_CCERR); |
| 1547 | if (val) { |
| 1548 | dev_warn(ecc->dev, "CCERR 0x%08x\n", val); |
| 1549 | /* Not reported, just clear the interrupt reason. */ |
| 1550 | edma_write(ecc, EDMA_CCERRCLR, val); |
| 1551 | } |
| 1552 | |
Peter Ujfalusi | 7c3b8b3 | 2015-10-14 14:43:02 +0300 | [diff] [blame] | 1553 | if (!edma_error_pending(ecc)) |
Peter Ujfalusi | 79ad2e3 | 2015-10-14 14:43:01 +0300 | [diff] [blame] | 1554 | break; |
| 1555 | cnt++; |
| 1556 | if (cnt > 10) |
| 1557 | break; |
| 1558 | } |
| 1559 | edma_write(ecc, EDMA_EEVAL, 1); |
| 1560 | return IRQ_HANDLED; |
| 1561 | } |
| 1562 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1563 | static void edma_tc_set_pm_state(struct edma_tc *tc, bool enable) |
| 1564 | { |
| 1565 | struct platform_device *tc_pdev; |
| 1566 | int ret; |
| 1567 | |
Arnd Bergmann | 638bdc8 | 2015-11-03 15:00:57 +0100 | [diff] [blame] | 1568 | if (!IS_ENABLED(CONFIG_OF) || !tc) |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1569 | return; |
| 1570 | |
| 1571 | tc_pdev = of_find_device_by_node(tc->node); |
| 1572 | if (!tc_pdev) { |
| 1573 | pr_err("%s: TPTC device is not found\n", __func__); |
| 1574 | return; |
| 1575 | } |
| 1576 | if (!pm_runtime_enabled(&tc_pdev->dev)) |
| 1577 | pm_runtime_enable(&tc_pdev->dev); |
| 1578 | |
| 1579 | if (enable) |
| 1580 | ret = pm_runtime_get_sync(&tc_pdev->dev); |
| 1581 | else |
| 1582 | ret = pm_runtime_put_sync(&tc_pdev->dev); |
| 1583 | |
| 1584 | if (ret < 0) |
| 1585 | pr_err("%s: pm_runtime_%s_sync() failed for %s\n", __func__, |
| 1586 | enable ? "get" : "put", dev_name(&tc_pdev->dev)); |
| 1587 | } |
| 1588 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1589 | /* Alloc channel resources */ |
| 1590 | static int edma_alloc_chan_resources(struct dma_chan *chan) |
| 1591 | { |
| 1592 | struct edma_chan *echan = to_edma_chan(chan); |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1593 | struct edma_cc *ecc = echan->ecc; |
| 1594 | struct device *dev = ecc->dev; |
| 1595 | enum dma_event_q eventq_no = EVENTQ_DEFAULT; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1596 | int ret; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1597 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1598 | if (echan->tc) { |
| 1599 | eventq_no = echan->tc->id; |
| 1600 | } else if (ecc->tc_list) { |
| 1601 | /* memcpy channel */ |
| 1602 | echan->tc = &ecc->tc_list[ecc->info->default_queue]; |
| 1603 | eventq_no = echan->tc->id; |
| 1604 | } |
| 1605 | |
| 1606 | ret = edma_alloc_channel(echan, eventq_no); |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 1607 | if (ret) |
| 1608 | return ret; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1609 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1610 | echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num); |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 1611 | if (echan->slot[0] < 0) { |
| 1612 | dev_err(dev, "Entry slot allocation failed for channel %u\n", |
| 1613 | EDMA_CHAN_SLOT(echan->ch_num)); |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 1614 | goto err_slot; |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 1615 | } |
| 1616 | |
| 1617 | /* Set up channel -> slot mapping for the entry slot */ |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 1618 | edma_set_chmap(echan, echan->slot[0]); |
| 1619 | echan->alloced = true; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1620 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1621 | dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n", |
| 1622 | EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id, |
| 1623 | echan->hw_triggered ? "HW" : "SW"); |
| 1624 | |
| 1625 | edma_tc_set_pm_state(echan->tc, true); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1626 | |
| 1627 | return 0; |
| 1628 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 1629 | err_slot: |
| 1630 | edma_free_channel(echan); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1631 | return ret; |
| 1632 | } |
| 1633 | |
| 1634 | /* Free channel resources */ |
| 1635 | static void edma_free_chan_resources(struct dma_chan *chan) |
| 1636 | { |
| 1637 | struct edma_chan *echan = to_edma_chan(chan); |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1638 | struct device *dev = echan->ecc->dev; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1639 | int i; |
| 1640 | |
| 1641 | /* Terminate transfers */ |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 1642 | edma_stop(echan); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1643 | |
| 1644 | vchan_free_chan_resources(&echan->vchan); |
| 1645 | |
| 1646 | /* Free EDMA PaRAM slots */ |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 1647 | for (i = 0; i < EDMA_MAX_SLOTS; i++) { |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1648 | if (echan->slot[i] >= 0) { |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1649 | edma_free_slot(echan->ecc, echan->slot[i]); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1650 | echan->slot[i] = -1; |
| 1651 | } |
| 1652 | } |
| 1653 | |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 1654 | /* Set entry slot to the dummy slot */ |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 1655 | edma_set_chmap(echan, echan->ecc->dummy_slot); |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 1656 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1657 | /* Free EDMA channel */ |
| 1658 | if (echan->alloced) { |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 1659 | edma_free_channel(echan); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1660 | echan->alloced = false; |
| 1661 | } |
| 1662 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1663 | edma_tc_set_pm_state(echan->tc, false); |
| 1664 | echan->tc = NULL; |
| 1665 | echan->hw_triggered = false; |
| 1666 | |
| 1667 | dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n", |
| 1668 | EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1669 | } |
| 1670 | |
| 1671 | /* Send pending descriptor to hardware */ |
| 1672 | static void edma_issue_pending(struct dma_chan *chan) |
| 1673 | { |
| 1674 | struct edma_chan *echan = to_edma_chan(chan); |
| 1675 | unsigned long flags; |
| 1676 | |
| 1677 | spin_lock_irqsave(&echan->vchan.lock, flags); |
| 1678 | if (vchan_issue_pending(&echan->vchan) && !echan->edesc) |
| 1679 | edma_execute(echan); |
| 1680 | spin_unlock_irqrestore(&echan->vchan.lock, flags); |
| 1681 | } |
| 1682 | |
Thomas Gleixner | 740b41f | 2014-04-28 14:34:11 -0500 | [diff] [blame] | 1683 | static u32 edma_residue(struct edma_desc *edesc) |
| 1684 | { |
| 1685 | bool dst = edesc->direction == DMA_DEV_TO_MEM; |
| 1686 | struct edma_pset *pset = edesc->pset; |
| 1687 | dma_addr_t done, pos; |
| 1688 | int i; |
| 1689 | |
| 1690 | /* |
| 1691 | * We always read the dst/src position from the first RamPar |
| 1692 | * pset. That's the one which is active now. |
| 1693 | */ |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1694 | pos = edma_get_position(edesc->echan->ecc, edesc->echan->slot[0], dst); |
Thomas Gleixner | 740b41f | 2014-04-28 14:34:11 -0500 | [diff] [blame] | 1695 | |
| 1696 | /* |
| 1697 | * Cyclic is simple. Just subtract pset[0].addr from pos. |
| 1698 | * |
| 1699 | * We never update edesc->residue in the cyclic case, so we |
| 1700 | * can tell the remaining room to the end of the circular |
| 1701 | * buffer. |
| 1702 | */ |
| 1703 | if (edesc->cyclic) { |
| 1704 | done = pos - pset->addr; |
| 1705 | edesc->residue_stat = edesc->residue - done; |
| 1706 | return edesc->residue_stat; |
| 1707 | } |
| 1708 | |
| 1709 | /* |
| 1710 | * For SG operation we catch up with the last processed |
| 1711 | * status. |
| 1712 | */ |
| 1713 | pset += edesc->processed_stat; |
| 1714 | |
| 1715 | for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) { |
| 1716 | /* |
| 1717 | * If we are inside this pset address range, we know |
| 1718 | * this is the active one. Get the current delta and |
| 1719 | * stop walking the psets. |
| 1720 | */ |
| 1721 | if (pos >= pset->addr && pos < pset->addr + pset->len) |
| 1722 | return edesc->residue_stat - (pos - pset->addr); |
| 1723 | |
| 1724 | /* Otherwise mark it done and update residue_stat. */ |
| 1725 | edesc->processed_stat++; |
| 1726 | edesc->residue_stat -= pset->len; |
| 1727 | } |
| 1728 | return edesc->residue_stat; |
| 1729 | } |
| 1730 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1731 | /* Check request completion status */ |
| 1732 | static enum dma_status edma_tx_status(struct dma_chan *chan, |
| 1733 | dma_cookie_t cookie, |
| 1734 | struct dma_tx_state *txstate) |
| 1735 | { |
| 1736 | struct edma_chan *echan = to_edma_chan(chan); |
| 1737 | struct virt_dma_desc *vdesc; |
| 1738 | enum dma_status ret; |
| 1739 | unsigned long flags; |
| 1740 | |
| 1741 | ret = dma_cookie_status(chan, cookie, txstate); |
Vinod Koul | 9d386ec | 2013-10-16 13:42:15 +0530 | [diff] [blame] | 1742 | if (ret == DMA_COMPLETE || !txstate) |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1743 | return ret; |
| 1744 | |
| 1745 | spin_lock_irqsave(&echan->vchan.lock, flags); |
Thomas Gleixner | de13593 | 2014-04-28 14:19:51 -0500 | [diff] [blame] | 1746 | if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) |
Thomas Gleixner | 740b41f | 2014-04-28 14:34:11 -0500 | [diff] [blame] | 1747 | txstate->residue = edma_residue(echan->edesc); |
Thomas Gleixner | de13593 | 2014-04-28 14:19:51 -0500 | [diff] [blame] | 1748 | else if ((vdesc = vchan_find_desc(&echan->vchan, cookie))) |
| 1749 | txstate->residue = to_edma_desc(&vdesc->tx)->residue; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1750 | spin_unlock_irqrestore(&echan->vchan.lock, flags); |
| 1751 | |
| 1752 | return ret; |
| 1753 | } |
| 1754 | |
Peter Ujfalusi | ecb7dec | 2015-12-09 10:18:10 +0200 | [diff] [blame] | 1755 | static bool edma_is_memcpy_channel(int ch_num, s32 *memcpy_channels) |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1756 | { |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1757 | if (!memcpy_channels) |
| 1758 | return false; |
Peter Ujfalusi | ecb7dec | 2015-12-09 10:18:10 +0200 | [diff] [blame] | 1759 | while (*memcpy_channels != -1) { |
| 1760 | if (*memcpy_channels == ch_num) |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1761 | return true; |
Peter Ujfalusi | ecb7dec | 2015-12-09 10:18:10 +0200 | [diff] [blame] | 1762 | memcpy_channels++; |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1763 | } |
| 1764 | return false; |
| 1765 | } |
| 1766 | |
Peter Ujfalusi | 2c88ee6 | 2014-04-14 14:42:01 +0300 | [diff] [blame] | 1767 | #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
| 1768 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ |
Peter Ujfalusi | e4a899d | 2014-07-03 07:51:56 +0300 | [diff] [blame] | 1769 | BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ |
Peter Ujfalusi | 2c88ee6 | 2014-04-14 14:42:01 +0300 | [diff] [blame] | 1770 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) |
| 1771 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1772 | static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode) |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1773 | { |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1774 | struct dma_device *s_ddev = &ecc->dma_slave; |
| 1775 | struct dma_device *m_ddev = NULL; |
Peter Ujfalusi | ecb7dec | 2015-12-09 10:18:10 +0200 | [diff] [blame] | 1776 | s32 *memcpy_channels = ecc->info->memcpy_channels; |
Peter Ujfalusi | 02f77ef | 2015-10-16 10:18:05 +0300 | [diff] [blame] | 1777 | int i, j; |
Maxime Ripard | 9f59cd0 | 2014-11-17 14:42:47 +0100 | [diff] [blame] | 1778 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1779 | dma_cap_zero(s_ddev->cap_mask); |
| 1780 | dma_cap_set(DMA_SLAVE, s_ddev->cap_mask); |
| 1781 | dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask); |
| 1782 | if (ecc->legacy_mode && !memcpy_channels) { |
| 1783 | dev_warn(ecc->dev, |
| 1784 | "Legacy memcpy is enabled, things might not work\n"); |
Maxime Ripard | 9f59cd0 | 2014-11-17 14:42:47 +0100 | [diff] [blame] | 1785 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1786 | dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask); |
| 1787 | s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; |
| 1788 | s_ddev->directions = BIT(DMA_MEM_TO_MEM); |
| 1789 | } |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1790 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1791 | s_ddev->device_prep_slave_sg = edma_prep_slave_sg; |
| 1792 | s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic; |
| 1793 | s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources; |
| 1794 | s_ddev->device_free_chan_resources = edma_free_chan_resources; |
| 1795 | s_ddev->device_issue_pending = edma_issue_pending; |
| 1796 | s_ddev->device_tx_status = edma_tx_status; |
| 1797 | s_ddev->device_config = edma_slave_config; |
| 1798 | s_ddev->device_pause = edma_dma_pause; |
| 1799 | s_ddev->device_resume = edma_dma_resume; |
| 1800 | s_ddev->device_terminate_all = edma_terminate_all; |
Peter Ujfalusi | 02f77ef | 2015-10-16 10:18:05 +0300 | [diff] [blame] | 1801 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1802 | s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; |
| 1803 | s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; |
| 1804 | s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV)); |
| 1805 | s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
Peter Ujfalusi | 02f77ef | 2015-10-16 10:18:05 +0300 | [diff] [blame] | 1806 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1807 | s_ddev->dev = ecc->dev; |
| 1808 | INIT_LIST_HEAD(&s_ddev->channels); |
| 1809 | |
| 1810 | if (memcpy_channels) { |
| 1811 | m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL); |
| 1812 | ecc->dma_memcpy = m_ddev; |
| 1813 | |
| 1814 | dma_cap_zero(m_ddev->cap_mask); |
| 1815 | dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask); |
| 1816 | |
| 1817 | m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; |
| 1818 | m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources; |
| 1819 | m_ddev->device_free_chan_resources = edma_free_chan_resources; |
| 1820 | m_ddev->device_issue_pending = edma_issue_pending; |
| 1821 | m_ddev->device_tx_status = edma_tx_status; |
| 1822 | m_ddev->device_config = edma_slave_config; |
| 1823 | m_ddev->device_pause = edma_dma_pause; |
| 1824 | m_ddev->device_resume = edma_dma_resume; |
| 1825 | m_ddev->device_terminate_all = edma_terminate_all; |
| 1826 | |
| 1827 | m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; |
| 1828 | m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; |
| 1829 | m_ddev->directions = BIT(DMA_MEM_TO_MEM); |
| 1830 | m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
| 1831 | |
| 1832 | m_ddev->dev = ecc->dev; |
| 1833 | INIT_LIST_HEAD(&m_ddev->channels); |
| 1834 | } else if (!ecc->legacy_mode) { |
| 1835 | dev_info(ecc->dev, "memcpy is disabled\n"); |
| 1836 | } |
Peter Ujfalusi | 02f77ef | 2015-10-16 10:18:05 +0300 | [diff] [blame] | 1837 | |
| 1838 | for (i = 0; i < ecc->num_channels; i++) { |
| 1839 | struct edma_chan *echan = &ecc->slave_chans[i]; |
| 1840 | echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); |
| 1841 | echan->ecc = ecc; |
| 1842 | echan->vchan.desc_free = edma_desc_free; |
| 1843 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1844 | if (m_ddev && edma_is_memcpy_channel(i, memcpy_channels)) |
| 1845 | vchan_init(&echan->vchan, m_ddev); |
| 1846 | else |
| 1847 | vchan_init(&echan->vchan, s_ddev); |
Peter Ujfalusi | 02f77ef | 2015-10-16 10:18:05 +0300 | [diff] [blame] | 1848 | |
| 1849 | INIT_LIST_HEAD(&echan->node); |
| 1850 | for (j = 0; j < EDMA_MAX_SLOTS; j++) |
| 1851 | echan->slot[j] = -1; |
| 1852 | } |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 1853 | } |
| 1854 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1855 | static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, |
| 1856 | struct edma_cc *ecc) |
| 1857 | { |
| 1858 | int i; |
| 1859 | u32 value, cccfg; |
| 1860 | s8 (*queue_priority_map)[2]; |
| 1861 | |
| 1862 | /* Decode the eDMA3 configuration from CCCFG register */ |
| 1863 | cccfg = edma_read(ecc, EDMA_CCCFG); |
| 1864 | |
| 1865 | value = GET_NUM_REGN(cccfg); |
| 1866 | ecc->num_region = BIT(value); |
| 1867 | |
| 1868 | value = GET_NUM_DMACH(cccfg); |
| 1869 | ecc->num_channels = BIT(value + 1); |
| 1870 | |
Peter Ujfalusi | 633e42b | 2015-10-16 10:18:04 +0300 | [diff] [blame] | 1871 | value = GET_NUM_QDMACH(cccfg); |
| 1872 | ecc->num_qchannels = value * 2; |
| 1873 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1874 | value = GET_NUM_PAENTRY(cccfg); |
| 1875 | ecc->num_slots = BIT(value + 4); |
| 1876 | |
| 1877 | value = GET_NUM_EVQUE(cccfg); |
| 1878 | ecc->num_tc = value + 1; |
| 1879 | |
Peter Ujfalusi | 4ab54f6 | 2015-10-14 14:43:04 +0300 | [diff] [blame] | 1880 | ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false; |
| 1881 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1882 | dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg); |
| 1883 | dev_dbg(dev, "num_region: %u\n", ecc->num_region); |
| 1884 | dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); |
Peter Ujfalusi | 633e42b | 2015-10-16 10:18:04 +0300 | [diff] [blame] | 1885 | dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1886 | dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); |
| 1887 | dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); |
Peter Ujfalusi | 4ab54f6 | 2015-10-14 14:43:04 +0300 | [diff] [blame] | 1888 | dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no"); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1889 | |
| 1890 | /* Nothing need to be done if queue priority is provided */ |
| 1891 | if (pdata->queue_priority_mapping) |
| 1892 | return 0; |
| 1893 | |
| 1894 | /* |
| 1895 | * Configure TC/queue priority as follows: |
| 1896 | * Q0 - priority 0 |
| 1897 | * Q1 - priority 1 |
| 1898 | * Q2 - priority 2 |
| 1899 | * ... |
| 1900 | * The meaning of priority numbers: 0 highest priority, 7 lowest |
| 1901 | * priority. So Q0 is the highest priority queue and the last queue has |
| 1902 | * the lowest priority. |
| 1903 | */ |
Peter Ujfalusi | 547c6e2 | 2015-10-14 14:42:55 +0300 | [diff] [blame] | 1904 | queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8), |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1905 | GFP_KERNEL); |
| 1906 | if (!queue_priority_map) |
| 1907 | return -ENOMEM; |
| 1908 | |
| 1909 | for (i = 0; i < ecc->num_tc; i++) { |
| 1910 | queue_priority_map[i][0] = i; |
| 1911 | queue_priority_map[i][1] = i; |
| 1912 | } |
| 1913 | queue_priority_map[i][0] = -1; |
| 1914 | queue_priority_map[i][1] = -1; |
| 1915 | |
| 1916 | pdata->queue_priority_mapping = queue_priority_map; |
| 1917 | /* Default queue has the lowest priority */ |
| 1918 | pdata->default_queue = i - 1; |
| 1919 | |
| 1920 | return 0; |
| 1921 | } |
| 1922 | |
| 1923 | #if IS_ENABLED(CONFIG_OF) |
| 1924 | static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata, |
| 1925 | size_t sz) |
| 1926 | { |
| 1927 | const char pname[] = "ti,edma-xbar-event-map"; |
| 1928 | struct resource res; |
| 1929 | void __iomem *xbar; |
| 1930 | s16 (*xbar_chans)[2]; |
| 1931 | size_t nelm = sz / sizeof(s16); |
| 1932 | u32 shift, offset, mux; |
| 1933 | int ret, i; |
| 1934 | |
Peter Ujfalusi | 547c6e2 | 2015-10-14 14:42:55 +0300 | [diff] [blame] | 1935 | xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1936 | if (!xbar_chans) |
| 1937 | return -ENOMEM; |
| 1938 | |
| 1939 | ret = of_address_to_resource(dev->of_node, 1, &res); |
| 1940 | if (ret) |
| 1941 | return -ENOMEM; |
| 1942 | |
| 1943 | xbar = devm_ioremap(dev, res.start, resource_size(&res)); |
| 1944 | if (!xbar) |
| 1945 | return -ENOMEM; |
| 1946 | |
| 1947 | ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans, |
| 1948 | nelm); |
| 1949 | if (ret) |
| 1950 | return -EIO; |
| 1951 | |
| 1952 | /* Invalidate last entry for the other user of this mess */ |
| 1953 | nelm >>= 1; |
| 1954 | xbar_chans[nelm][0] = -1; |
| 1955 | xbar_chans[nelm][1] = -1; |
| 1956 | |
| 1957 | for (i = 0; i < nelm; i++) { |
| 1958 | shift = (xbar_chans[i][1] & 0x03) << 3; |
| 1959 | offset = xbar_chans[i][1] & 0xfffffffc; |
| 1960 | mux = readl(xbar + offset); |
| 1961 | mux &= ~(0xff << shift); |
| 1962 | mux |= xbar_chans[i][0] << shift; |
| 1963 | writel(mux, (xbar + offset)); |
| 1964 | } |
| 1965 | |
| 1966 | pdata->xbar_chans = (const s16 (*)[2]) xbar_chans; |
| 1967 | return 0; |
| 1968 | } |
| 1969 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1970 | static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, |
| 1971 | bool legacy_mode) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1972 | { |
| 1973 | struct edma_soc_info *info; |
Peter Ujfalusi | 966a87b | 2015-10-16 10:18:07 +0300 | [diff] [blame] | 1974 | struct property *prop; |
| 1975 | size_t sz; |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 1976 | int ret; |
| 1977 | |
| 1978 | info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL); |
| 1979 | if (!info) |
| 1980 | return ERR_PTR(-ENOMEM); |
| 1981 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1982 | if (legacy_mode) { |
| 1983 | prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", |
| 1984 | &sz); |
| 1985 | if (prop) { |
| 1986 | ret = edma_xbar_event_map(dev, info, sz); |
| 1987 | if (ret) |
| 1988 | return ERR_PTR(ret); |
| 1989 | } |
| 1990 | return info; |
| 1991 | } |
| 1992 | |
| 1993 | /* Get the list of channels allocated to be used for memcpy */ |
| 1994 | prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz); |
Peter Ujfalusi | 966a87b | 2015-10-16 10:18:07 +0300 | [diff] [blame] | 1995 | if (prop) { |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1996 | const char pname[] = "ti,edma-memcpy-channels"; |
Peter Ujfalusi | ecb7dec | 2015-12-09 10:18:10 +0200 | [diff] [blame] | 1997 | size_t nelm = sz / sizeof(s32); |
| 1998 | s32 *memcpy_ch; |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 1999 | |
Peter Ujfalusi | ecb7dec | 2015-12-09 10:18:10 +0200 | [diff] [blame] | 2000 | memcpy_ch = devm_kcalloc(dev, nelm + 1, sizeof(s32), |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2001 | GFP_KERNEL); |
| 2002 | if (!memcpy_ch) |
| 2003 | return ERR_PTR(-ENOMEM); |
| 2004 | |
Peter Ujfalusi | ecb7dec | 2015-12-09 10:18:10 +0200 | [diff] [blame] | 2005 | ret = of_property_read_u32_array(dev->of_node, pname, |
| 2006 | (u32 *)memcpy_ch, nelm); |
Peter Ujfalusi | 966a87b | 2015-10-16 10:18:07 +0300 | [diff] [blame] | 2007 | if (ret) |
| 2008 | return ERR_PTR(ret); |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2009 | |
| 2010 | memcpy_ch[nelm] = -1; |
| 2011 | info->memcpy_channels = memcpy_ch; |
| 2012 | } |
| 2013 | |
| 2014 | prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges", |
| 2015 | &sz); |
| 2016 | if (prop) { |
| 2017 | const char pname[] = "ti,edma-reserved-slot-ranges"; |
Peter Ujfalusi | ae0add7 | 2015-12-09 10:18:11 +0200 | [diff] [blame] | 2018 | u32 (*tmp)[2]; |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2019 | s16 (*rsv_slots)[2]; |
Peter Ujfalusi | ae0add7 | 2015-12-09 10:18:11 +0200 | [diff] [blame] | 2020 | size_t nelm = sz / sizeof(*tmp); |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2021 | struct edma_rsv_info *rsv_info; |
Peter Ujfalusi | ae0add7 | 2015-12-09 10:18:11 +0200 | [diff] [blame] | 2022 | int i; |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2023 | |
| 2024 | if (!nelm) |
| 2025 | return info; |
| 2026 | |
Peter Ujfalusi | ae0add7 | 2015-12-09 10:18:11 +0200 | [diff] [blame] | 2027 | tmp = kcalloc(nelm, sizeof(*tmp), GFP_KERNEL); |
| 2028 | if (!tmp) |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2029 | return ERR_PTR(-ENOMEM); |
| 2030 | |
Peter Ujfalusi | ae0add7 | 2015-12-09 10:18:11 +0200 | [diff] [blame] | 2031 | rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL); |
| 2032 | if (!rsv_info) { |
| 2033 | kfree(tmp); |
| 2034 | return ERR_PTR(-ENOMEM); |
| 2035 | } |
| 2036 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2037 | rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots), |
| 2038 | GFP_KERNEL); |
Peter Ujfalusi | ae0add7 | 2015-12-09 10:18:11 +0200 | [diff] [blame] | 2039 | if (!rsv_slots) { |
| 2040 | kfree(tmp); |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2041 | return ERR_PTR(-ENOMEM); |
Peter Ujfalusi | ae0add7 | 2015-12-09 10:18:11 +0200 | [diff] [blame] | 2042 | } |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2043 | |
Peter Ujfalusi | ae0add7 | 2015-12-09 10:18:11 +0200 | [diff] [blame] | 2044 | ret = of_property_read_u32_array(dev->of_node, pname, |
| 2045 | (u32 *)tmp, nelm * 2); |
| 2046 | if (ret) { |
| 2047 | kfree(tmp); |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2048 | return ERR_PTR(ret); |
Peter Ujfalusi | ae0add7 | 2015-12-09 10:18:11 +0200 | [diff] [blame] | 2049 | } |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2050 | |
Peter Ujfalusi | ae0add7 | 2015-12-09 10:18:11 +0200 | [diff] [blame] | 2051 | for (i = 0; i < nelm; i++) { |
| 2052 | rsv_slots[i][0] = tmp[i][0]; |
| 2053 | rsv_slots[i][1] = tmp[i][1]; |
| 2054 | } |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2055 | rsv_slots[nelm][0] = -1; |
| 2056 | rsv_slots[nelm][1] = -1; |
Peter Ujfalusi | ae0add7 | 2015-12-09 10:18:11 +0200 | [diff] [blame] | 2057 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2058 | info->rsv = rsv_info; |
| 2059 | info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots; |
Peter Ujfalusi | ae0add7 | 2015-12-09 10:18:11 +0200 | [diff] [blame] | 2060 | |
| 2061 | kfree(tmp); |
Peter Ujfalusi | 966a87b | 2015-10-16 10:18:07 +0300 | [diff] [blame] | 2062 | } |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2063 | |
| 2064 | return info; |
| 2065 | } |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2066 | |
| 2067 | static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec, |
| 2068 | struct of_dma *ofdma) |
| 2069 | { |
| 2070 | struct edma_cc *ecc = ofdma->of_dma_data; |
| 2071 | struct dma_chan *chan = NULL; |
| 2072 | struct edma_chan *echan; |
| 2073 | int i; |
| 2074 | |
| 2075 | if (!ecc || dma_spec->args_count < 1) |
| 2076 | return NULL; |
| 2077 | |
| 2078 | for (i = 0; i < ecc->num_channels; i++) { |
| 2079 | echan = &ecc->slave_chans[i]; |
| 2080 | if (echan->ch_num == dma_spec->args[0]) { |
| 2081 | chan = &echan->vchan.chan; |
| 2082 | break; |
| 2083 | } |
| 2084 | } |
| 2085 | |
| 2086 | if (!chan) |
| 2087 | return NULL; |
| 2088 | |
| 2089 | if (echan->ecc->legacy_mode && dma_spec->args_count == 1) |
| 2090 | goto out; |
| 2091 | |
| 2092 | if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 && |
| 2093 | dma_spec->args[1] < echan->ecc->num_tc) { |
| 2094 | echan->tc = &echan->ecc->tc_list[dma_spec->args[1]]; |
| 2095 | goto out; |
| 2096 | } |
| 2097 | |
| 2098 | return NULL; |
| 2099 | out: |
| 2100 | /* The channel is going to be used as HW synchronized */ |
| 2101 | echan->hw_triggered = true; |
| 2102 | return dma_get_slave_channel(chan); |
| 2103 | } |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2104 | #else |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2105 | static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, |
| 2106 | bool legacy_mode) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2107 | { |
| 2108 | return ERR_PTR(-EINVAL); |
| 2109 | } |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2110 | |
| 2111 | static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec, |
| 2112 | struct of_dma *ofdma) |
| 2113 | { |
| 2114 | return NULL; |
| 2115 | } |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2116 | #endif |
| 2117 | |
Bill Pemberton | 463a1f8 | 2012-11-19 13:22:55 -0500 | [diff] [blame] | 2118 | static int edma_probe(struct platform_device *pdev) |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2119 | { |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2120 | struct edma_soc_info *info = pdev->dev.platform_data; |
| 2121 | s8 (*queue_priority_mapping)[2]; |
| 2122 | int i, off, ln; |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2123 | const s16 (*rsv_slots)[2]; |
| 2124 | const s16 (*xbar_chans)[2]; |
| 2125 | int irq; |
| 2126 | char *irq_name; |
| 2127 | struct resource *mem; |
| 2128 | struct device_node *node = pdev->dev.of_node; |
| 2129 | struct device *dev = &pdev->dev; |
| 2130 | struct edma_cc *ecc; |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2131 | bool legacy_mode = true; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2132 | int ret; |
| 2133 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2134 | if (node) { |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2135 | const struct of_device_id *match; |
| 2136 | |
| 2137 | match = of_match_node(edma_of_ids, node); |
| 2138 | if (match && (u32)match->data == EDMA_BINDING_TPCC) |
| 2139 | legacy_mode = false; |
| 2140 | |
| 2141 | info = edma_setup_info_from_dt(dev, legacy_mode); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2142 | if (IS_ERR(info)) { |
| 2143 | dev_err(dev, "failed to get DT data\n"); |
| 2144 | return PTR_ERR(info); |
| 2145 | } |
| 2146 | } |
| 2147 | |
| 2148 | if (!info) |
| 2149 | return -ENODEV; |
| 2150 | |
| 2151 | pm_runtime_enable(dev); |
| 2152 | ret = pm_runtime_get_sync(dev); |
| 2153 | if (ret < 0) { |
| 2154 | dev_err(dev, "pm_runtime_get_sync() failed\n"); |
| 2155 | return ret; |
| 2156 | } |
| 2157 | |
Peter Ujfalusi | 907f74a | 2015-10-14 14:42:56 +0300 | [diff] [blame] | 2158 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); |
Russell King | 94cb0e7 | 2013-06-27 13:45:16 +0100 | [diff] [blame] | 2159 | if (ret) |
| 2160 | return ret; |
| 2161 | |
Peter Ujfalusi | 907f74a | 2015-10-14 14:42:56 +0300 | [diff] [blame] | 2162 | ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2163 | if (!ecc) { |
Peter Ujfalusi | 907f74a | 2015-10-14 14:42:56 +0300 | [diff] [blame] | 2164 | dev_err(dev, "Can't allocate controller\n"); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2165 | return -ENOMEM; |
| 2166 | } |
| 2167 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2168 | ecc->dev = dev; |
| 2169 | ecc->id = pdev->id; |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2170 | ecc->legacy_mode = legacy_mode; |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2171 | /* When booting with DT the pdev->id is -1 */ |
| 2172 | if (ecc->id < 0) |
| 2173 | ecc->id = 0; |
Peter Ujfalusi | ca304fa | 2015-10-14 14:42:49 +0300 | [diff] [blame] | 2174 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2175 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc"); |
| 2176 | if (!mem) { |
| 2177 | dev_dbg(dev, "mem resource not found, using index 0\n"); |
| 2178 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 2179 | if (!mem) { |
| 2180 | dev_err(dev, "no mem resource?\n"); |
| 2181 | return -ENODEV; |
| 2182 | } |
| 2183 | } |
| 2184 | ecc->base = devm_ioremap_resource(dev, mem); |
| 2185 | if (IS_ERR(ecc->base)) |
| 2186 | return PTR_ERR(ecc->base); |
Peter Ujfalusi | b2c843a | 2015-10-14 14:42:50 +0300 | [diff] [blame] | 2187 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2188 | platform_set_drvdata(pdev, ecc); |
| 2189 | |
| 2190 | /* Get eDMA3 configuration from IP */ |
| 2191 | ret = edma_setup_from_hw(dev, info, ecc); |
| 2192 | if (ret) |
| 2193 | return ret; |
| 2194 | |
Peter Ujfalusi | cb78205 | 2015-10-14 14:42:54 +0300 | [diff] [blame] | 2195 | /* Allocate memory based on the information we got from the IP */ |
| 2196 | ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels, |
| 2197 | sizeof(*ecc->slave_chans), GFP_KERNEL); |
| 2198 | if (!ecc->slave_chans) |
| 2199 | return -ENOMEM; |
| 2200 | |
Peter Ujfalusi | 7a73b13 | 2015-10-14 14:43:05 +0300 | [diff] [blame] | 2201 | ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), |
Peter Ujfalusi | cb78205 | 2015-10-14 14:42:54 +0300 | [diff] [blame] | 2202 | sizeof(unsigned long), GFP_KERNEL); |
Peter Ujfalusi | 7a73b13 | 2015-10-14 14:43:05 +0300 | [diff] [blame] | 2203 | if (!ecc->slot_inuse) |
Peter Ujfalusi | cb78205 | 2015-10-14 14:42:54 +0300 | [diff] [blame] | 2204 | return -ENOMEM; |
| 2205 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2206 | ecc->default_queue = info->default_queue; |
| 2207 | |
| 2208 | for (i = 0; i < ecc->num_slots; i++) |
| 2209 | edma_write_slot(ecc, i, &dummy_paramset); |
| 2210 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2211 | if (info->rsv) { |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2212 | /* Set the reserved slots in inuse list */ |
| 2213 | rsv_slots = info->rsv->rsv_slots; |
| 2214 | if (rsv_slots) { |
| 2215 | for (i = 0; rsv_slots[i][0] != -1; i++) { |
| 2216 | off = rsv_slots[i][0]; |
| 2217 | ln = rsv_slots[i][1]; |
Peter Ujfalusi | 7a73b13 | 2015-10-14 14:43:05 +0300 | [diff] [blame] | 2218 | set_bits(off, ln, ecc->slot_inuse); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2219 | } |
| 2220 | } |
| 2221 | } |
| 2222 | |
| 2223 | /* Clear the xbar mapped channels in unused list */ |
| 2224 | xbar_chans = info->xbar_chans; |
| 2225 | if (xbar_chans) { |
| 2226 | for (i = 0; xbar_chans[i][1] != -1; i++) { |
| 2227 | off = xbar_chans[i][1]; |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2228 | } |
| 2229 | } |
| 2230 | |
| 2231 | irq = platform_get_irq_byname(pdev, "edma3_ccint"); |
| 2232 | if (irq < 0 && node) |
| 2233 | irq = irq_of_parse_and_map(node, 0); |
| 2234 | |
| 2235 | if (irq >= 0) { |
| 2236 | irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint", |
| 2237 | dev_name(dev)); |
| 2238 | ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name, |
| 2239 | ecc); |
| 2240 | if (ret) { |
| 2241 | dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret); |
| 2242 | return ret; |
| 2243 | } |
| 2244 | } |
| 2245 | |
| 2246 | irq = platform_get_irq_byname(pdev, "edma3_ccerrint"); |
| 2247 | if (irq < 0 && node) |
| 2248 | irq = irq_of_parse_and_map(node, 2); |
| 2249 | |
| 2250 | if (irq >= 0) { |
| 2251 | irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint", |
| 2252 | dev_name(dev)); |
| 2253 | ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name, |
| 2254 | ecc); |
| 2255 | if (ret) { |
| 2256 | dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret); |
| 2257 | return ret; |
| 2258 | } |
| 2259 | } |
| 2260 | |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 2261 | ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); |
| 2262 | if (ecc->dummy_slot < 0) { |
| 2263 | dev_err(dev, "Can't allocate PaRAM dummy slot\n"); |
| 2264 | return ecc->dummy_slot; |
| 2265 | } |
| 2266 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2267 | queue_priority_mapping = info->queue_priority_mapping; |
| 2268 | |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2269 | if (!ecc->legacy_mode) { |
| 2270 | int lowest_priority = 0; |
| 2271 | struct of_phandle_args tc_args; |
| 2272 | |
| 2273 | ecc->tc_list = devm_kcalloc(dev, ecc->num_tc, |
| 2274 | sizeof(*ecc->tc_list), GFP_KERNEL); |
| 2275 | if (!ecc->tc_list) |
| 2276 | return -ENOMEM; |
| 2277 | |
| 2278 | for (i = 0;; i++) { |
| 2279 | ret = of_parse_phandle_with_fixed_args(node, "ti,tptcs", |
| 2280 | 1, i, &tc_args); |
| 2281 | if (ret || i == ecc->num_tc) |
| 2282 | break; |
| 2283 | |
| 2284 | ecc->tc_list[i].node = tc_args.np; |
| 2285 | ecc->tc_list[i].id = i; |
| 2286 | queue_priority_mapping[i][1] = tc_args.args[0]; |
| 2287 | if (queue_priority_mapping[i][1] > lowest_priority) { |
| 2288 | lowest_priority = queue_priority_mapping[i][1]; |
| 2289 | info->default_queue = i; |
| 2290 | } |
| 2291 | } |
| 2292 | } |
| 2293 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2294 | /* Event queue priority mapping */ |
| 2295 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) |
| 2296 | edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], |
| 2297 | queue_priority_mapping[i][1]); |
| 2298 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2299 | for (i = 0; i < ecc->num_region; i++) { |
| 2300 | edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0); |
| 2301 | edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0); |
| 2302 | edma_write_array(ecc, EDMA_QRAE, i, 0x0); |
| 2303 | } |
| 2304 | ecc->info = info; |
| 2305 | |
Peter Ujfalusi | 02f77ef | 2015-10-16 10:18:05 +0300 | [diff] [blame] | 2306 | /* Init the dma device and channels */ |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2307 | edma_dma_init(ecc, legacy_mode); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2308 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 2309 | for (i = 0; i < ecc->num_channels; i++) { |
| 2310 | /* Assign all channels to the default queue */ |
Peter Ujfalusi | f9425de | 2015-10-16 10:18:03 +0300 | [diff] [blame] | 2311 | edma_assign_channel_eventq(&ecc->slave_chans[i], |
| 2312 | info->default_queue); |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 2313 | /* Set entry slot to the dummy slot */ |
| 2314 | edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); |
| 2315 | } |
| 2316 | |
Peter Ujfalusi | 23e6723 | 2015-12-14 22:47:41 +0200 | [diff] [blame] | 2317 | ecc->dma_slave.filter.map = info->slave_map; |
| 2318 | ecc->dma_slave.filter.mapcnt = info->slavecnt; |
| 2319 | ecc->dma_slave.filter.fn = edma_filter_fn; |
| 2320 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2321 | ret = dma_async_device_register(&ecc->dma_slave); |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2322 | if (ret) { |
| 2323 | dev_err(dev, "slave ddev registration failed (%d)\n", ret); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2324 | goto err_reg1; |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2325 | } |
| 2326 | |
| 2327 | if (ecc->dma_memcpy) { |
| 2328 | ret = dma_async_device_register(ecc->dma_memcpy); |
| 2329 | if (ret) { |
| 2330 | dev_err(dev, "memcpy ddev registration failed (%d)\n", |
| 2331 | ret); |
| 2332 | dma_async_device_unregister(&ecc->dma_slave); |
| 2333 | goto err_reg1; |
| 2334 | } |
| 2335 | } |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2336 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2337 | if (node) |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2338 | of_dma_controller_register(node, of_edma_xlate, ecc); |
Peter Ujfalusi | dc9b6055 | 2015-10-14 14:42:47 +0300 | [diff] [blame] | 2339 | |
Peter Ujfalusi | 907f74a | 2015-10-14 14:42:56 +0300 | [diff] [blame] | 2340 | dev_info(dev, "TI EDMA DMA engine driver\n"); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2341 | |
| 2342 | return 0; |
| 2343 | |
| 2344 | err_reg1: |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2345 | edma_free_slot(ecc, ecc->dummy_slot); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2346 | return ret; |
| 2347 | } |
| 2348 | |
Greg Kroah-Hartman | 4bf27b8 | 2012-12-21 15:09:59 -0800 | [diff] [blame] | 2349 | static int edma_remove(struct platform_device *pdev) |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2350 | { |
| 2351 | struct device *dev = &pdev->dev; |
| 2352 | struct edma_cc *ecc = dev_get_drvdata(dev); |
| 2353 | |
Peter Ujfalusi | 907f74a | 2015-10-14 14:42:56 +0300 | [diff] [blame] | 2354 | if (dev->of_node) |
| 2355 | of_dma_controller_free(dev->of_node); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2356 | dma_async_device_unregister(&ecc->dma_slave); |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2357 | if (ecc->dma_memcpy) |
| 2358 | dma_async_device_unregister(ecc->dma_memcpy); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2359 | edma_free_slot(ecc, ecc->dummy_slot); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2360 | |
| 2361 | return 0; |
| 2362 | } |
| 2363 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2364 | #ifdef CONFIG_PM_SLEEP |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2365 | static int edma_pm_suspend(struct device *dev) |
| 2366 | { |
| 2367 | struct edma_cc *ecc = dev_get_drvdata(dev); |
| 2368 | struct edma_chan *echan = ecc->slave_chans; |
| 2369 | int i; |
| 2370 | |
| 2371 | for (i = 0; i < ecc->num_channels; i++) { |
| 2372 | if (echan[i].alloced) { |
| 2373 | edma_setup_interrupt(&echan[i], false); |
| 2374 | edma_tc_set_pm_state(echan[i].tc, false); |
| 2375 | } |
| 2376 | } |
| 2377 | |
| 2378 | return 0; |
| 2379 | } |
| 2380 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2381 | static int edma_pm_resume(struct device *dev) |
| 2382 | { |
| 2383 | struct edma_cc *ecc = dev_get_drvdata(dev); |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 2384 | struct edma_chan *echan = ecc->slave_chans; |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2385 | int i; |
| 2386 | s8 (*queue_priority_mapping)[2]; |
| 2387 | |
| 2388 | queue_priority_mapping = ecc->info->queue_priority_mapping; |
| 2389 | |
| 2390 | /* Event queue priority mapping */ |
| 2391 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) |
| 2392 | edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], |
| 2393 | queue_priority_mapping[i][1]); |
| 2394 | |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2395 | for (i = 0; i < ecc->num_channels; i++) { |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 2396 | if (echan[i].alloced) { |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2397 | /* ensure access through shadow region 0 */ |
| 2398 | edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5, |
| 2399 | BIT(i & 0x1f)); |
| 2400 | |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 2401 | edma_setup_interrupt(&echan[i], true); |
Peter Ujfalusi | e4e886c | 2015-10-14 14:43:06 +0300 | [diff] [blame] | 2402 | |
| 2403 | /* Set up channel -> slot mapping for the entry slot */ |
Peter Ujfalusi | 34cf301 | 2015-10-16 10:18:01 +0300 | [diff] [blame] | 2404 | edma_set_chmap(&echan[i], echan[i].slot[0]); |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2405 | |
| 2406 | edma_tc_set_pm_state(echan[i].tc, true); |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2407 | } |
| 2408 | } |
| 2409 | |
| 2410 | return 0; |
| 2411 | } |
| 2412 | #endif |
| 2413 | |
| 2414 | static const struct dev_pm_ops edma_pm_ops = { |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2415 | SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend, edma_pm_resume) |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2416 | }; |
| 2417 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2418 | static struct platform_driver edma_driver = { |
| 2419 | .probe = edma_probe, |
Bill Pemberton | a7d6e3e | 2012-11-19 13:20:04 -0500 | [diff] [blame] | 2420 | .remove = edma_remove, |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2421 | .driver = { |
Peter Ujfalusi | 2b6b3b7 | 2015-10-14 14:42:53 +0300 | [diff] [blame] | 2422 | .name = "edma", |
| 2423 | .pm = &edma_pm_ops, |
| 2424 | .of_match_table = edma_of_ids, |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2425 | }, |
| 2426 | }; |
| 2427 | |
Peter Ujfalusi | 4fa2d09 | 2015-12-16 15:19:05 +0200 | [diff] [blame] | 2428 | static int edma_tptc_probe(struct platform_device *pdev) |
| 2429 | { |
| 2430 | return 0; |
| 2431 | } |
| 2432 | |
Peter Ujfalusi | 34635b1a | 2015-11-02 15:21:40 +0200 | [diff] [blame] | 2433 | static struct platform_driver edma_tptc_driver = { |
Peter Ujfalusi | 4fa2d09 | 2015-12-16 15:19:05 +0200 | [diff] [blame] | 2434 | .probe = edma_tptc_probe, |
Peter Ujfalusi | 34635b1a | 2015-11-02 15:21:40 +0200 | [diff] [blame] | 2435 | .driver = { |
| 2436 | .name = "edma3-tptc", |
| 2437 | .of_match_table = edma_tptc_of_ids, |
| 2438 | }, |
| 2439 | }; |
| 2440 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2441 | bool edma_filter_fn(struct dma_chan *chan, void *param) |
| 2442 | { |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2443 | bool match = false; |
| 2444 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2445 | if (chan->device->dev->driver == &edma_driver.driver) { |
| 2446 | struct edma_chan *echan = to_edma_chan(chan); |
| 2447 | unsigned ch_req = *(unsigned *)param; |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2448 | if (ch_req == echan->ch_num) { |
| 2449 | /* The channel is going to be used as HW synchronized */ |
| 2450 | echan->hw_triggered = true; |
| 2451 | match = true; |
| 2452 | } |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2453 | } |
Peter Ujfalusi | 1be5336 | 2015-10-16 10:18:10 +0300 | [diff] [blame] | 2454 | return match; |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2455 | } |
| 2456 | EXPORT_SYMBOL(edma_filter_fn); |
| 2457 | |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2458 | static int edma_init(void) |
| 2459 | { |
Peter Ujfalusi | 34635b1a | 2015-11-02 15:21:40 +0200 | [diff] [blame] | 2460 | int ret; |
| 2461 | |
| 2462 | ret = platform_driver_register(&edma_tptc_driver); |
| 2463 | if (ret) |
| 2464 | return ret; |
| 2465 | |
Arnd Bergmann | 5305e4d | 2014-10-24 18:14:01 +0200 | [diff] [blame] | 2466 | return platform_driver_register(&edma_driver); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2467 | } |
| 2468 | subsys_initcall(edma_init); |
| 2469 | |
| 2470 | static void __exit edma_exit(void) |
| 2471 | { |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2472 | platform_driver_unregister(&edma_driver); |
Peter Ujfalusi | 34635b1a | 2015-11-02 15:21:40 +0200 | [diff] [blame] | 2473 | platform_driver_unregister(&edma_tptc_driver); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2474 | } |
| 2475 | module_exit(edma_exit); |
| 2476 | |
Josh Boyer | d71505b | 2013-09-04 10:32:50 -0400 | [diff] [blame] | 2477 | MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>"); |
Matt Porter | c2dde5f | 2012-08-22 21:09:34 -0400 | [diff] [blame] | 2478 | MODULE_DESCRIPTION("TI EDMA DMA engine driver"); |
| 2479 | MODULE_LICENSE("GPL v2"); |