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Jeeja KPe4e2d2f2015-10-07 11:31:52 +01001/*
2 * skl-topology.c - Implements Platform component ALSA controls/widget
3 * handlers.
4 *
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19#include <linux/slab.h>
20#include <linux/types.h>
21#include <linux/firmware.h>
22#include <sound/soc.h>
23#include <sound/soc-topology.h>
Shreyas NC6277e832016-08-12 12:29:51 +053024#include <uapi/sound/snd_sst_tokens.h>
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010025#include "skl-sst-dsp.h"
26#include "skl-sst-ipc.h"
27#include "skl-topology.h"
28#include "skl.h"
29#include "skl-tplg-interface.h"
Dharageswari R6c5768b2015-12-03 23:29:50 +053030#include "../common/sst-dsp.h"
31#include "../common/sst-dsp-priv.h"
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010032
Jeeja KPf7590d42015-10-07 11:31:53 +010033#define SKL_CH_FIXUP_MASK (1 << 0)
34#define SKL_RATE_FIXUP_MASK (1 << 1)
35#define SKL_FMT_FIXUP_MASK (1 << 2)
Shreyas NC6277e832016-08-12 12:29:51 +053036#define SKL_IN_DIR_BIT_MASK BIT(0)
37#define SKL_PIN_COUNT_MASK GENMASK(7, 4)
Jeeja KPf7590d42015-10-07 11:31:53 +010038
Vinod Koula83e3b42016-11-03 17:07:20 +053039void skl_tplg_d0i3_get(struct skl *skl, enum d0i3_capability caps)
40{
41 struct skl_d0i3_data *d0i3 = &skl->skl_sst->d0i3;
42
43 switch (caps) {
44 case SKL_D0I3_NONE:
45 d0i3->non_d0i3++;
46 break;
47
48 case SKL_D0I3_STREAMING:
49 d0i3->streaming++;
50 break;
51
52 case SKL_D0I3_NON_STREAMING:
53 d0i3->non_streaming++;
54 break;
55 }
56}
57
58void skl_tplg_d0i3_put(struct skl *skl, enum d0i3_capability caps)
59{
60 struct skl_d0i3_data *d0i3 = &skl->skl_sst->d0i3;
61
62 switch (caps) {
63 case SKL_D0I3_NONE:
64 d0i3->non_d0i3--;
65 break;
66
67 case SKL_D0I3_STREAMING:
68 d0i3->streaming--;
69 break;
70
71 case SKL_D0I3_NON_STREAMING:
72 d0i3->non_streaming--;
73 break;
74 }
75}
76
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010077/*
78 * SKL DSP driver modelling uses only few DAPM widgets so for rest we will
79 * ignore. This helpers checks if the SKL driver handles this widget type
80 */
81static int is_skl_dsp_widget_type(struct snd_soc_dapm_widget *w)
82{
83 switch (w->id) {
84 case snd_soc_dapm_dai_link:
85 case snd_soc_dapm_dai_in:
86 case snd_soc_dapm_aif_in:
87 case snd_soc_dapm_aif_out:
88 case snd_soc_dapm_dai_out:
89 case snd_soc_dapm_switch:
90 return false;
91 default:
92 return true;
93 }
94}
95
96/*
97 * Each pipelines needs memory to be allocated. Check if we have free memory
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053098 * from available pool.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010099 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530100static bool skl_is_pipe_mem_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100101 struct skl_module_cfg *mconfig)
102{
103 struct skl_sst *ctx = skl->skl_sst;
104
105 if (skl->resource.mem + mconfig->pipe->memory_pages >
106 skl->resource.max_mem) {
107 dev_err(ctx->dev,
108 "%s: module_id %d instance %d\n", __func__,
109 mconfig->id.module_id,
110 mconfig->id.instance_id);
111 dev_err(ctx->dev,
112 "exceeds ppl memory available %d mem %d\n",
113 skl->resource.max_mem, skl->resource.mem);
114 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530115 } else {
116 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100117 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530118}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100119
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530120/*
121 * Add the mem to the mem pool. This is freed when pipe is deleted.
122 * Note: DSP does actual memory management we only keep track for complete
123 * pool
124 */
125static void skl_tplg_alloc_pipe_mem(struct skl *skl,
126 struct skl_module_cfg *mconfig)
127{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100128 skl->resource.mem += mconfig->pipe->memory_pages;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100129}
130
131/*
132 * Pipeline needs needs DSP CPU resources for computation, this is
133 * quantified in MCPS (Million Clocks Per Second) required for module/pipe
134 *
135 * Each pipelines needs mcps to be allocated. Check if we have mcps for this
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530136 * pipe.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100137 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530138
139static bool skl_is_pipe_mcps_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100140 struct skl_module_cfg *mconfig)
141{
142 struct skl_sst *ctx = skl->skl_sst;
143
144 if (skl->resource.mcps + mconfig->mcps > skl->resource.max_mcps) {
145 dev_err(ctx->dev,
146 "%s: module_id %d instance %d\n", __func__,
147 mconfig->id.module_id, mconfig->id.instance_id);
148 dev_err(ctx->dev,
Guneshwor Singh7ca42f52016-02-03 17:59:46 +0530149 "exceeds ppl mcps available %d > mem %d\n",
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100150 skl->resource.max_mcps, skl->resource.mcps);
151 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530152 } else {
153 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100154 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530155}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100156
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530157static void skl_tplg_alloc_pipe_mcps(struct skl *skl,
158 struct skl_module_cfg *mconfig)
159{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100160 skl->resource.mcps += mconfig->mcps;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100161}
162
163/*
164 * Free the mcps when tearing down
165 */
166static void
167skl_tplg_free_pipe_mcps(struct skl *skl, struct skl_module_cfg *mconfig)
168{
169 skl->resource.mcps -= mconfig->mcps;
170}
171
172/*
173 * Free the memory when tearing down
174 */
175static void
176skl_tplg_free_pipe_mem(struct skl *skl, struct skl_module_cfg *mconfig)
177{
178 skl->resource.mem -= mconfig->pipe->memory_pages;
179}
180
Jeeja KPf7590d42015-10-07 11:31:53 +0100181
182static void skl_dump_mconfig(struct skl_sst *ctx,
183 struct skl_module_cfg *mcfg)
184{
185 dev_dbg(ctx->dev, "Dumping config\n");
186 dev_dbg(ctx->dev, "Input Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900187 dev_dbg(ctx->dev, "channels = %d\n", mcfg->in_fmt[0].channels);
188 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->in_fmt[0].s_freq);
189 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->in_fmt[0].ch_cfg);
190 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->in_fmt[0].valid_bit_depth);
Jeeja KPf7590d42015-10-07 11:31:53 +0100191 dev_dbg(ctx->dev, "Output Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900192 dev_dbg(ctx->dev, "channels = %d\n", mcfg->out_fmt[0].channels);
193 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->out_fmt[0].s_freq);
194 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->out_fmt[0].valid_bit_depth);
195 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->out_fmt[0].ch_cfg);
Jeeja KPf7590d42015-10-07 11:31:53 +0100196}
197
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530198static void skl_tplg_update_chmap(struct skl_module_fmt *fmt, int chs)
199{
200 int slot_map = 0xFFFFFFFF;
201 int start_slot = 0;
202 int i;
203
204 for (i = 0; i < chs; i++) {
205 /*
206 * For 2 channels with starting slot as 0, slot map will
207 * look like 0xFFFFFF10.
208 */
209 slot_map &= (~(0xF << (4 * i)) | (start_slot << (4 * i)));
210 start_slot++;
211 }
212 fmt->ch_map = slot_map;
213}
214
Jeeja KPf7590d42015-10-07 11:31:53 +0100215static void skl_tplg_update_params(struct skl_module_fmt *fmt,
216 struct skl_pipe_params *params, int fixup)
217{
218 if (fixup & SKL_RATE_FIXUP_MASK)
219 fmt->s_freq = params->s_freq;
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530220 if (fixup & SKL_CH_FIXUP_MASK) {
Jeeja KPf7590d42015-10-07 11:31:53 +0100221 fmt->channels = params->ch;
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530222 skl_tplg_update_chmap(fmt, fmt->channels);
223 }
Jeeja KP98256f82015-11-23 22:26:25 +0530224 if (fixup & SKL_FMT_FIXUP_MASK) {
225 fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
226
227 /*
228 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
229 * container so update bit depth accordingly
230 */
231 switch (fmt->valid_bit_depth) {
232 case SKL_DEPTH_16BIT:
233 fmt->bit_depth = fmt->valid_bit_depth;
234 break;
235
236 default:
237 fmt->bit_depth = SKL_DEPTH_32BIT;
238 break;
239 }
240 }
241
Jeeja KPf7590d42015-10-07 11:31:53 +0100242}
243
244/*
245 * A pipeline may have modules which impact the pcm parameters, like SRC,
246 * channel converter, format converter.
247 * We need to calculate the output params by applying the 'fixup'
248 * Topology will tell driver which type of fixup is to be applied by
249 * supplying the fixup mask, so based on that we calculate the output
250 *
251 * Now In FE the pcm hw_params is source/target format. Same is applicable
252 * for BE with its hw_params invoked.
253 * here based on FE, BE pipeline and direction we calculate the input and
254 * outfix and then apply that for a module
255 */
256static void skl_tplg_update_params_fixup(struct skl_module_cfg *m_cfg,
257 struct skl_pipe_params *params, bool is_fe)
258{
259 int in_fixup, out_fixup;
260 struct skl_module_fmt *in_fmt, *out_fmt;
261
Hardik T Shah4cd98992015-10-27 09:22:55 +0900262 /* Fixups will be applied to pin 0 only */
263 in_fmt = &m_cfg->in_fmt[0];
264 out_fmt = &m_cfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100265
266 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
267 if (is_fe) {
268 in_fixup = m_cfg->params_fixup;
269 out_fixup = (~m_cfg->converter) &
270 m_cfg->params_fixup;
271 } else {
272 out_fixup = m_cfg->params_fixup;
273 in_fixup = (~m_cfg->converter) &
274 m_cfg->params_fixup;
275 }
276 } else {
277 if (is_fe) {
278 out_fixup = m_cfg->params_fixup;
279 in_fixup = (~m_cfg->converter) &
280 m_cfg->params_fixup;
281 } else {
282 in_fixup = m_cfg->params_fixup;
283 out_fixup = (~m_cfg->converter) &
284 m_cfg->params_fixup;
285 }
286 }
287
288 skl_tplg_update_params(in_fmt, params, in_fixup);
289 skl_tplg_update_params(out_fmt, params, out_fixup);
290}
291
292/*
293 * A module needs input and output buffers, which are dependent upon pcm
294 * params, so once we have calculate params, we need buffer calculation as
295 * well.
296 */
297static void skl_tplg_update_buffer_size(struct skl_sst *ctx,
298 struct skl_module_cfg *mcfg)
299{
300 int multiplier = 1;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900301 struct skl_module_fmt *in_fmt, *out_fmt;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900302
303 /* Since fixups is applied to pin 0 only, ibs, obs needs
304 * change for pin 0 only
305 */
306 in_fmt = &mcfg->in_fmt[0];
307 out_fmt = &mcfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100308
309 if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT)
310 multiplier = 5;
Jeeja KPf7590d42015-10-07 11:31:53 +0100311
Takashi Sakamoto8e15e762017-03-06 16:12:22 +0900312 mcfg->ibs = DIV_ROUND_UP(in_fmt->s_freq, 1000) *
Takashi Sakamoto998d6fb2017-03-08 17:47:02 +0900313 in_fmt->channels * (in_fmt->bit_depth >> 3) *
Subhransu S. Prustyf0c8e1d2016-04-12 10:31:23 +0530314 multiplier;
315
Takashi Sakamoto998d6fb2017-03-08 17:47:02 +0900316 mcfg->obs = DIV_ROUND_UP(out_fmt->s_freq, 1000) *
317 out_fmt->channels * (out_fmt->bit_depth >> 3) *
Subhransu S. Prustyf0c8e1d2016-04-12 10:31:23 +0530318 multiplier;
Jeeja KPf7590d42015-10-07 11:31:53 +0100319}
320
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +0530321static u8 skl_tplg_be_dev_type(int dev_type)
322{
323 int ret;
324
325 switch (dev_type) {
326 case SKL_DEVICE_BT:
327 ret = NHLT_DEVICE_BT;
328 break;
329
330 case SKL_DEVICE_DMIC:
331 ret = NHLT_DEVICE_DMIC;
332 break;
333
334 case SKL_DEVICE_I2S:
335 ret = NHLT_DEVICE_I2S;
336 break;
337
338 default:
339 ret = NHLT_DEVICE_INVALID;
340 break;
341 }
342
343 return ret;
344}
345
Jeeja KP2d1419a2016-02-05 12:19:10 +0530346static int skl_tplg_update_be_blob(struct snd_soc_dapm_widget *w,
347 struct skl_sst *ctx)
348{
349 struct skl_module_cfg *m_cfg = w->priv;
350 int link_type, dir;
351 u32 ch, s_freq, s_fmt;
352 struct nhlt_specific_cfg *cfg;
353 struct skl *skl = get_skl_ctx(ctx->dev);
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +0530354 u8 dev_type = skl_tplg_be_dev_type(m_cfg->dev_type);
Jeeja KP2d1419a2016-02-05 12:19:10 +0530355
356 /* check if we already have blob */
357 if (m_cfg->formats_config.caps_size > 0)
358 return 0;
359
Jeeja KPc7c6c732016-03-01 07:59:10 +0530360 dev_dbg(ctx->dev, "Applying default cfg blob\n");
Jeeja KP2d1419a2016-02-05 12:19:10 +0530361 switch (m_cfg->dev_type) {
362 case SKL_DEVICE_DMIC:
363 link_type = NHLT_LINK_DMIC;
Jeeja KPc7c6c732016-03-01 07:59:10 +0530364 dir = SNDRV_PCM_STREAM_CAPTURE;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530365 s_freq = m_cfg->in_fmt[0].s_freq;
366 s_fmt = m_cfg->in_fmt[0].bit_depth;
367 ch = m_cfg->in_fmt[0].channels;
368 break;
369
370 case SKL_DEVICE_I2S:
371 link_type = NHLT_LINK_SSP;
372 if (m_cfg->hw_conn_type == SKL_CONN_SOURCE) {
Jeeja KPc7c6c732016-03-01 07:59:10 +0530373 dir = SNDRV_PCM_STREAM_PLAYBACK;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530374 s_freq = m_cfg->out_fmt[0].s_freq;
375 s_fmt = m_cfg->out_fmt[0].bit_depth;
376 ch = m_cfg->out_fmt[0].channels;
Jeeja KPc7c6c732016-03-01 07:59:10 +0530377 } else {
378 dir = SNDRV_PCM_STREAM_CAPTURE;
379 s_freq = m_cfg->in_fmt[0].s_freq;
380 s_fmt = m_cfg->in_fmt[0].bit_depth;
381 ch = m_cfg->in_fmt[0].channels;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530382 }
383 break;
384
385 default:
386 return -EINVAL;
387 }
388
389 /* update the blob based on virtual bus_id and default params */
390 cfg = skl_get_ep_blob(skl, m_cfg->vbus_id, link_type,
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +0530391 s_fmt, ch, s_freq, dir, dev_type);
Jeeja KP2d1419a2016-02-05 12:19:10 +0530392 if (cfg) {
393 m_cfg->formats_config.caps_size = cfg->size;
394 m_cfg->formats_config.caps = (u32 *) &cfg->caps;
395 } else {
396 dev_err(ctx->dev, "Blob NULL for id %x type %d dirn %d\n",
397 m_cfg->vbus_id, link_type, dir);
398 dev_err(ctx->dev, "PCM: ch %d, freq %d, fmt %d\n",
399 ch, s_freq, s_fmt);
400 return -EIO;
401 }
402
403 return 0;
404}
405
Jeeja KPf7590d42015-10-07 11:31:53 +0100406static void skl_tplg_update_module_params(struct snd_soc_dapm_widget *w,
407 struct skl_sst *ctx)
408{
409 struct skl_module_cfg *m_cfg = w->priv;
410 struct skl_pipe_params *params = m_cfg->pipe->p_params;
411 int p_conn_type = m_cfg->pipe->conn_type;
412 bool is_fe;
413
414 if (!m_cfg->params_fixup)
415 return;
416
417 dev_dbg(ctx->dev, "Mconfig for widget=%s BEFORE updation\n",
418 w->name);
419
420 skl_dump_mconfig(ctx, m_cfg);
421
422 if (p_conn_type == SKL_PIPE_CONN_TYPE_FE)
423 is_fe = true;
424 else
425 is_fe = false;
426
427 skl_tplg_update_params_fixup(m_cfg, params, is_fe);
428 skl_tplg_update_buffer_size(ctx, m_cfg);
429
430 dev_dbg(ctx->dev, "Mconfig for widget=%s AFTER updation\n",
431 w->name);
432
433 skl_dump_mconfig(ctx, m_cfg);
434}
435
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100436/*
Jeeja KPabb74002015-11-28 15:01:49 +0530437 * some modules can have multiple params set from user control and
438 * need to be set after module is initialized. If set_param flag is
439 * set module params will be done after module is initialised.
440 */
441static int skl_tplg_set_module_params(struct snd_soc_dapm_widget *w,
442 struct skl_sst *ctx)
443{
444 int i, ret;
445 struct skl_module_cfg *mconfig = w->priv;
446 const struct snd_kcontrol_new *k;
447 struct soc_bytes_ext *sb;
448 struct skl_algo_data *bc;
449 struct skl_specific_cfg *sp_cfg;
450
451 if (mconfig->formats_config.caps_size > 0 &&
Jeeja KP4ced1822015-12-03 23:29:53 +0530452 mconfig->formats_config.set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530453 sp_cfg = &mconfig->formats_config;
454 ret = skl_set_module_params(ctx, sp_cfg->caps,
455 sp_cfg->caps_size,
456 sp_cfg->param_id, mconfig);
457 if (ret < 0)
458 return ret;
459 }
460
461 for (i = 0; i < w->num_kcontrols; i++) {
462 k = &w->kcontrol_news[i];
463 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
464 sb = (void *) k->private_value;
465 bc = (struct skl_algo_data *)sb->dobj.private;
466
Jeeja KP4ced1822015-12-03 23:29:53 +0530467 if (bc->set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530468 ret = skl_set_module_params(ctx,
Dharageswari R0d682102016-07-08 18:15:03 +0530469 (u32 *)bc->params, bc->size,
Jeeja KPabb74002015-11-28 15:01:49 +0530470 bc->param_id, mconfig);
471 if (ret < 0)
472 return ret;
473 }
474 }
475 }
476
477 return 0;
478}
479
480/*
481 * some module param can set from user control and this is required as
482 * when module is initailzed. if module param is required in init it is
483 * identifed by set_param flag. if set_param flag is not set, then this
484 * parameter needs to set as part of module init.
485 */
486static int skl_tplg_set_module_init_data(struct snd_soc_dapm_widget *w)
487{
488 const struct snd_kcontrol_new *k;
489 struct soc_bytes_ext *sb;
490 struct skl_algo_data *bc;
491 struct skl_module_cfg *mconfig = w->priv;
492 int i;
493
494 for (i = 0; i < w->num_kcontrols; i++) {
495 k = &w->kcontrol_news[i];
496 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
497 sb = (struct soc_bytes_ext *)k->private_value;
498 bc = (struct skl_algo_data *)sb->dobj.private;
499
Jeeja KP4ced1822015-12-03 23:29:53 +0530500 if (bc->set_params != SKL_PARAM_INIT)
Jeeja KPabb74002015-11-28 15:01:49 +0530501 continue;
502
503 mconfig->formats_config.caps = (u32 *)&bc->params;
Dharageswari R0d682102016-07-08 18:15:03 +0530504 mconfig->formats_config.caps_size = bc->size;
Jeeja KPabb74002015-11-28 15:01:49 +0530505
506 break;
507 }
508 }
509
510 return 0;
511}
512
Jeeja KPbb704a732016-12-08 13:41:14 +0530513static int skl_tplg_module_prepare(struct skl_sst *ctx, struct skl_pipe *pipe,
514 struct snd_soc_dapm_widget *w, struct skl_module_cfg *mcfg)
515{
516 switch (mcfg->dev_type) {
517 case SKL_DEVICE_HDAHOST:
518 return skl_pcm_host_dma_prepare(ctx->dev, pipe->p_params);
519
520 case SKL_DEVICE_HDALINK:
521 return skl_pcm_link_dma_prepare(ctx->dev, pipe->p_params);
522 }
523
524 return 0;
525}
526
Jeeja KPabb74002015-11-28 15:01:49 +0530527/*
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100528 * Inside a pipe instance, we can have various modules. These modules need
529 * to instantiated in DSP by invoking INIT_MODULE IPC, which is achieved by
530 * skl_init_module() routine, so invoke that for all modules in a pipeline
531 */
532static int
533skl_tplg_init_pipe_modules(struct skl *skl, struct skl_pipe *pipe)
534{
535 struct skl_pipe_module *w_module;
536 struct snd_soc_dapm_widget *w;
537 struct skl_module_cfg *mconfig;
538 struct skl_sst *ctx = skl->skl_sst;
539 int ret = 0;
540
541 list_for_each_entry(w_module, &pipe->w_list, node) {
Jeeja KPb26199e2017-03-24 23:10:31 +0530542 uuid_le *uuid_mod;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100543 w = w_module->w;
544 mconfig = w->priv;
545
Vinod Koulb7c50552016-07-26 18:06:40 +0530546 /* check if module ids are populated */
547 if (mconfig->id.module_id < 0) {
Vinod Koula657ae72016-08-10 09:40:50 +0530548 dev_err(skl->skl_sst->dev,
549 "module %pUL id not populated\n",
550 (uuid_le *)mconfig->guid);
551 return -EIO;
Vinod Koulb7c50552016-07-26 18:06:40 +0530552 }
553
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100554 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530555 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100556 return -ENOMEM;
557
Dharageswari R6c5768b2015-12-03 23:29:50 +0530558 if (mconfig->is_loadable && ctx->dsp->fw_ops.load_mod) {
559 ret = ctx->dsp->fw_ops.load_mod(ctx->dsp,
560 mconfig->id.module_id, mconfig->guid);
561 if (ret < 0)
562 return ret;
Jeeja KPd6436782016-03-28 22:11:30 +0530563
564 mconfig->m_state = SKL_MODULE_LOADED;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530565 }
566
Jeeja KPbb704a732016-12-08 13:41:14 +0530567 /* prepare the DMA if the module is gateway cpr */
568 ret = skl_tplg_module_prepare(ctx, pipe, w, mconfig);
569 if (ret < 0)
570 return ret;
571
Jeeja KP2d1419a2016-02-05 12:19:10 +0530572 /* update blob if blob is null for be with default value */
573 skl_tplg_update_be_blob(w, ctx);
574
Jeeja KPf7590d42015-10-07 11:31:53 +0100575 /*
576 * apply fix/conversion to module params based on
577 * FE/BE params
578 */
579 skl_tplg_update_module_params(w, ctx);
Jeeja KPb26199e2017-03-24 23:10:31 +0530580 uuid_mod = (uuid_le *)mconfig->guid;
581 mconfig->id.pvt_id = skl_get_pvt_id(ctx, uuid_mod,
582 mconfig->id.instance_id);
Dharageswari Ref2a3522016-09-22 14:00:38 +0530583 if (mconfig->id.pvt_id < 0)
584 return ret;
Jeeja KPabb74002015-11-28 15:01:49 +0530585 skl_tplg_set_module_init_data(w);
Jeeja KP9939a9c2015-11-28 15:01:47 +0530586 ret = skl_init_module(ctx, mconfig);
Dharageswari Ref2a3522016-09-22 14:00:38 +0530587 if (ret < 0) {
Jeeja KPb26199e2017-03-24 23:10:31 +0530588 skl_put_pvt_id(ctx, uuid_mod, &mconfig->id.pvt_id);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100589 return ret;
Dharageswari Ref2a3522016-09-22 14:00:38 +0530590 }
Dharageswari R260eb732016-06-03 18:29:38 +0530591 skl_tplg_alloc_pipe_mcps(skl, mconfig);
Jeeja KPabb74002015-11-28 15:01:49 +0530592 ret = skl_tplg_set_module_params(w, ctx);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100593 if (ret < 0)
594 return ret;
595 }
596
597 return 0;
598}
Vinod Kould93f8e52015-10-07 11:31:54 +0100599
Dharageswari R6c5768b2015-12-03 23:29:50 +0530600static int skl_tplg_unload_pipe_modules(struct skl_sst *ctx,
601 struct skl_pipe *pipe)
602{
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530603 int ret;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530604 struct skl_pipe_module *w_module = NULL;
605 struct skl_module_cfg *mconfig = NULL;
606
607 list_for_each_entry(w_module, &pipe->w_list, node) {
Jeeja KPb26199e2017-03-24 23:10:31 +0530608 uuid_le *uuid_mod;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530609 mconfig = w_module->w->priv;
Jeeja KPb26199e2017-03-24 23:10:31 +0530610 uuid_mod = (uuid_le *)mconfig->guid;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530611
Jeeja KPd6436782016-03-28 22:11:30 +0530612 if (mconfig->is_loadable && ctx->dsp->fw_ops.unload_mod &&
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530613 mconfig->m_state > SKL_MODULE_UNINIT) {
614 ret = ctx->dsp->fw_ops.unload_mod(ctx->dsp,
Dharageswari R6c5768b2015-12-03 23:29:50 +0530615 mconfig->id.module_id);
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530616 if (ret < 0)
617 return -EIO;
618 }
Jeeja KPb26199e2017-03-24 23:10:31 +0530619 skl_put_pvt_id(ctx, uuid_mod, &mconfig->id.pvt_id);
Dharageswari R6c5768b2015-12-03 23:29:50 +0530620 }
621
622 /* no modules to unload in this path, so return */
623 return 0;
624}
625
Vinod Kould93f8e52015-10-07 11:31:54 +0100626/*
627 * Mixer module represents a pipeline. So in the Pre-PMU event of mixer we
628 * need create the pipeline. So we do following:
629 * - check the resources
630 * - Create the pipeline
631 * - Initialize the modules in pipeline
632 * - finally bind all modules together
633 */
634static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
635 struct skl *skl)
636{
637 int ret;
638 struct skl_module_cfg *mconfig = w->priv;
639 struct skl_pipe_module *w_module;
640 struct skl_pipe *s_pipe = mconfig->pipe;
641 struct skl_module_cfg *src_module = NULL, *dst_module;
642 struct skl_sst *ctx = skl->skl_sst;
643
644 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530645 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100646 return -EBUSY;
647
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530648 if (!skl_is_pipe_mem_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100649 return -ENOMEM;
650
651 /*
652 * Create a list of modules for pipe.
653 * This list contains modules from source to sink
654 */
655 ret = skl_create_pipeline(ctx, mconfig->pipe);
656 if (ret < 0)
657 return ret;
658
Dharageswari R260eb732016-06-03 18:29:38 +0530659 skl_tplg_alloc_pipe_mem(skl, mconfig);
660 skl_tplg_alloc_pipe_mcps(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100661
662 /* Init all pipe modules from source to sink */
663 ret = skl_tplg_init_pipe_modules(skl, s_pipe);
664 if (ret < 0)
665 return ret;
666
667 /* Bind modules from source to sink */
668 list_for_each_entry(w_module, &s_pipe->w_list, node) {
669 dst_module = w_module->w->priv;
670
671 if (src_module == NULL) {
672 src_module = dst_module;
673 continue;
674 }
675
676 ret = skl_bind_modules(ctx, src_module, dst_module);
677 if (ret < 0)
678 return ret;
679
680 src_module = dst_module;
681 }
682
683 return 0;
684}
685
Dharageswari Rbf3e5ef2017-03-13 22:11:32 +0530686static int skl_fill_sink_instance_id(struct skl_sst *ctx, u32 *params,
687 int size, struct skl_module_cfg *mcfg)
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530688{
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530689 int i, pvt_id;
690
Dharageswari Rbf3e5ef2017-03-13 22:11:32 +0530691 if (mcfg->m_type == SKL_MODULE_TYPE_KPB) {
692 struct skl_kpb_params *kpb_params =
693 (struct skl_kpb_params *)params;
694 struct skl_mod_inst_map *inst = kpb_params->map;
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530695
Dharageswari Rbf3e5ef2017-03-13 22:11:32 +0530696 for (i = 0; i < kpb_params->num_modules; i++) {
697 pvt_id = skl_get_pvt_instance_id_map(ctx, inst->mod_id,
698 inst->inst_id);
699 if (pvt_id < 0)
700 return -EINVAL;
701
702 inst->inst_id = pvt_id;
703 inst++;
704 }
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530705 }
Dharageswari Rbf3e5ef2017-03-13 22:11:32 +0530706
Dharageswari R5e8f0ee2016-09-22 14:00:40 +0530707 return 0;
708}
Jeeja KPcc6a4042016-02-05 12:19:08 +0530709/*
710 * Some modules require params to be set after the module is bound to
711 * all pins connected.
712 *
713 * The module provider initializes set_param flag for such modules and we
714 * send params after binding
715 */
716static int skl_tplg_set_module_bind_params(struct snd_soc_dapm_widget *w,
717 struct skl_module_cfg *mcfg, struct skl_sst *ctx)
718{
719 int i, ret;
720 struct skl_module_cfg *mconfig = w->priv;
721 const struct snd_kcontrol_new *k;
722 struct soc_bytes_ext *sb;
723 struct skl_algo_data *bc;
724 struct skl_specific_cfg *sp_cfg;
Dharageswari Rbf3e5ef2017-03-13 22:11:32 +0530725 u32 *params;
Jeeja KPcc6a4042016-02-05 12:19:08 +0530726
727 /*
728 * check all out/in pins are in bind state.
729 * if so set the module param
730 */
731 for (i = 0; i < mcfg->max_out_queue; i++) {
732 if (mcfg->m_out_pin[i].pin_state != SKL_PIN_BIND_DONE)
733 return 0;
734 }
735
736 for (i = 0; i < mcfg->max_in_queue; i++) {
737 if (mcfg->m_in_pin[i].pin_state != SKL_PIN_BIND_DONE)
738 return 0;
739 }
740
741 if (mconfig->formats_config.caps_size > 0 &&
742 mconfig->formats_config.set_params == SKL_PARAM_BIND) {
743 sp_cfg = &mconfig->formats_config;
744 ret = skl_set_module_params(ctx, sp_cfg->caps,
745 sp_cfg->caps_size,
746 sp_cfg->param_id, mconfig);
747 if (ret < 0)
748 return ret;
749 }
750
751 for (i = 0; i < w->num_kcontrols; i++) {
752 k = &w->kcontrol_news[i];
753 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
754 sb = (void *) k->private_value;
755 bc = (struct skl_algo_data *)sb->dobj.private;
756
757 if (bc->set_params == SKL_PARAM_BIND) {
Dharageswari Rbf3e5ef2017-03-13 22:11:32 +0530758 params = kzalloc(bc->max, GFP_KERNEL);
759 if (!params)
760 return -ENOMEM;
761
762 memcpy(params, bc->params, bc->max);
763 skl_fill_sink_instance_id(ctx, params, bc->max,
764 mconfig);
765
766 ret = skl_set_module_params(ctx, params,
767 bc->max, bc->param_id, mconfig);
768 kfree(params);
769
Jeeja KPcc6a4042016-02-05 12:19:08 +0530770 if (ret < 0)
771 return ret;
772 }
773 }
774 }
775
776 return 0;
777}
778
Jeeja KP8724ff12015-10-27 09:22:52 +0900779static int skl_tplg_bind_sinks(struct snd_soc_dapm_widget *w,
780 struct skl *skl,
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530781 struct snd_soc_dapm_widget *src_w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900782 struct skl_module_cfg *src_mconfig)
Vinod Kould93f8e52015-10-07 11:31:54 +0100783{
784 struct snd_soc_dapm_path *p;
Jeeja KP0ed95d72015-11-13 19:22:11 +0530785 struct snd_soc_dapm_widget *sink = NULL, *next_sink = NULL;
Jeeja KP8724ff12015-10-27 09:22:52 +0900786 struct skl_module_cfg *sink_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100787 struct skl_sst *ctx = skl->skl_sst;
Jeeja KP8724ff12015-10-27 09:22:52 +0900788 int ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100789
Jeeja KP8724ff12015-10-27 09:22:52 +0900790 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Kould93f8e52015-10-07 11:31:54 +0100791 if (!p->connect)
792 continue;
793
794 dev_dbg(ctx->dev, "%s: src widget=%s\n", __func__, w->name);
795 dev_dbg(ctx->dev, "%s: sink widget=%s\n", __func__, p->sink->name);
796
Jeeja KP0ed95d72015-11-13 19:22:11 +0530797 next_sink = p->sink;
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530798
799 if (!is_skl_dsp_widget_type(p->sink))
800 return skl_tplg_bind_sinks(p->sink, skl, src_w, src_mconfig);
801
Vinod Kould93f8e52015-10-07 11:31:54 +0100802 /*
803 * here we will check widgets in sink pipelines, so that
804 * can be any widgets type and we are only interested if
805 * they are ones used for SKL so check that first
806 */
807 if ((p->sink->priv != NULL) &&
808 is_skl_dsp_widget_type(p->sink)) {
809
810 sink = p->sink;
Vinod Kould93f8e52015-10-07 11:31:54 +0100811 sink_mconfig = sink->priv;
812
Jeeja KPcc6a4042016-02-05 12:19:08 +0530813 if (src_mconfig->m_state == SKL_MODULE_UNINIT ||
814 sink_mconfig->m_state == SKL_MODULE_UNINIT)
815 continue;
816
Vinod Kould93f8e52015-10-07 11:31:54 +0100817 /* Bind source to sink, mixin is always source */
818 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
819 if (ret)
820 return ret;
821
Jeeja KPcc6a4042016-02-05 12:19:08 +0530822 /* set module params after bind */
823 skl_tplg_set_module_bind_params(src_w, src_mconfig, ctx);
824 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx);
825
Vinod Kould93f8e52015-10-07 11:31:54 +0100826 /* Start sinks pipe first */
827 if (sink_mconfig->pipe->state != SKL_PIPE_STARTED) {
Jeeja KPd1730c32015-10-27 09:22:53 +0900828 if (sink_mconfig->pipe->conn_type !=
829 SKL_PIPE_CONN_TYPE_FE)
830 ret = skl_run_pipe(ctx,
831 sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100832 if (ret)
833 return ret;
834 }
Vinod Kould93f8e52015-10-07 11:31:54 +0100835 }
836 }
837
Jeeja KP8724ff12015-10-27 09:22:52 +0900838 if (!sink)
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530839 return skl_tplg_bind_sinks(next_sink, skl, src_w, src_mconfig);
Jeeja KP8724ff12015-10-27 09:22:52 +0900840
841 return 0;
842}
843
Vinod Kould93f8e52015-10-07 11:31:54 +0100844/*
845 * A PGA represents a module in a pipeline. So in the Pre-PMU event of PGA
846 * we need to do following:
847 * - Bind to sink pipeline
848 * Since the sink pipes can be running and we don't get mixer event on
849 * connect for already running mixer, we need to find the sink pipes
850 * here and bind to them. This way dynamic connect works.
851 * - Start sink pipeline, if not running
852 * - Then run current pipe
853 */
854static int skl_tplg_pga_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900855 struct skl *skl)
Vinod Kould93f8e52015-10-07 11:31:54 +0100856{
Jeeja KP8724ff12015-10-27 09:22:52 +0900857 struct skl_module_cfg *src_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100858 struct skl_sst *ctx = skl->skl_sst;
859 int ret = 0;
860
Jeeja KP8724ff12015-10-27 09:22:52 +0900861 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100862
863 /*
864 * find which sink it is connected to, bind with the sink,
865 * if sink is not started, start sink pipe first, then start
866 * this pipe
867 */
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530868 ret = skl_tplg_bind_sinks(w, skl, w, src_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100869 if (ret)
870 return ret;
871
Vinod Kould93f8e52015-10-07 11:31:54 +0100872 /* Start source pipe last after starting all sinks */
Jeeja KPd1730c32015-10-27 09:22:53 +0900873 if (src_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
874 return skl_run_pipe(ctx, src_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100875
876 return 0;
877}
878
Jeeja KP8724ff12015-10-27 09:22:52 +0900879static struct snd_soc_dapm_widget *skl_get_src_dsp_widget(
880 struct snd_soc_dapm_widget *w, struct skl *skl)
881{
882 struct snd_soc_dapm_path *p;
883 struct snd_soc_dapm_widget *src_w = NULL;
884 struct skl_sst *ctx = skl->skl_sst;
885
886 snd_soc_dapm_widget_for_each_source_path(w, p) {
887 src_w = p->source;
888 if (!p->connect)
889 continue;
890
891 dev_dbg(ctx->dev, "sink widget=%s\n", w->name);
892 dev_dbg(ctx->dev, "src widget=%s\n", p->source->name);
893
894 /*
895 * here we will check widgets in sink pipelines, so that can
896 * be any widgets type and we are only interested if they are
897 * ones used for SKL so check that first
898 */
899 if ((p->source->priv != NULL) &&
900 is_skl_dsp_widget_type(p->source)) {
901 return p->source;
902 }
903 }
904
905 if (src_w != NULL)
906 return skl_get_src_dsp_widget(src_w, skl);
907
908 return NULL;
909}
910
Vinod Kould93f8e52015-10-07 11:31:54 +0100911/*
912 * in the Post-PMU event of mixer we need to do following:
913 * - Check if this pipe is running
914 * - if not, then
915 * - bind this pipeline to its source pipeline
916 * if source pipe is already running, this means it is a dynamic
917 * connection and we need to bind only to that pipe
918 * - start this pipeline
919 */
920static int skl_tplg_mixer_dapm_post_pmu_event(struct snd_soc_dapm_widget *w,
921 struct skl *skl)
922{
923 int ret = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100924 struct snd_soc_dapm_widget *source, *sink;
925 struct skl_module_cfg *src_mconfig, *sink_mconfig;
926 struct skl_sst *ctx = skl->skl_sst;
927 int src_pipe_started = 0;
928
929 sink = w;
930 sink_mconfig = sink->priv;
931
932 /*
933 * If source pipe is already started, that means source is driving
934 * one more sink before this sink got connected, Since source is
935 * started, bind this sink to source and start this pipe.
936 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900937 source = skl_get_src_dsp_widget(w, skl);
938 if (source != NULL) {
939 src_mconfig = source->priv;
940 sink_mconfig = sink->priv;
941 src_pipe_started = 1;
Vinod Kould93f8e52015-10-07 11:31:54 +0100942
943 /*
Jeeja KP8724ff12015-10-27 09:22:52 +0900944 * check pipe state, then no need to bind or start the
945 * pipe
Vinod Kould93f8e52015-10-07 11:31:54 +0100946 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900947 if (src_mconfig->pipe->state != SKL_PIPE_STARTED)
948 src_pipe_started = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100949 }
950
951 if (src_pipe_started) {
952 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
953 if (ret)
954 return ret;
955
Jeeja KPcc6a4042016-02-05 12:19:08 +0530956 /* set module params after bind */
957 skl_tplg_set_module_bind_params(source, src_mconfig, ctx);
958 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx);
959
Jeeja KPd1730c32015-10-27 09:22:53 +0900960 if (sink_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
961 ret = skl_run_pipe(ctx, sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100962 }
963
964 return ret;
965}
966
967/*
968 * in the Pre-PMD event of mixer we need to do following:
969 * - Stop the pipe
970 * - find the source connections and remove that from dapm_path_list
971 * - unbind with source pipelines if still connected
972 */
973static int skl_tplg_mixer_dapm_pre_pmd_event(struct snd_soc_dapm_widget *w,
974 struct skl *skl)
975{
Vinod Kould93f8e52015-10-07 11:31:54 +0100976 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +0900977 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +0100978 struct skl_sst *ctx = skl->skl_sst;
979
Jeeja KPce1b5552015-10-27 09:22:51 +0900980 sink_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100981
982 /* Stop the pipe */
983 ret = skl_stop_pipe(ctx, sink_mconfig->pipe);
984 if (ret)
985 return ret;
986
Jeeja KPce1b5552015-10-27 09:22:51 +0900987 for (i = 0; i < sink_mconfig->max_in_queue; i++) {
988 if (sink_mconfig->m_in_pin[i].pin_state == SKL_PIN_BIND_DONE) {
989 src_mconfig = sink_mconfig->m_in_pin[i].tgt_mcfg;
990 if (!src_mconfig)
991 continue;
Vinod Kould93f8e52015-10-07 11:31:54 +0100992
Jeeja KPce1b5552015-10-27 09:22:51 +0900993 ret = skl_unbind_modules(ctx,
994 src_mconfig, sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100995 }
996 }
997
Vinod Kould93f8e52015-10-07 11:31:54 +0100998 return ret;
999}
1000
1001/*
1002 * in the Post-PMD event of mixer we need to do following:
1003 * - Free the mcps used
1004 * - Free the mem used
1005 * - Unbind the modules within the pipeline
1006 * - Delete the pipeline (modules are not required to be explicitly
1007 * deleted, pipeline delete is enough here
1008 */
1009static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
1010 struct skl *skl)
1011{
1012 struct skl_module_cfg *mconfig = w->priv;
1013 struct skl_pipe_module *w_module;
1014 struct skl_module_cfg *src_module = NULL, *dst_module;
1015 struct skl_sst *ctx = skl->skl_sst;
1016 struct skl_pipe *s_pipe = mconfig->pipe;
Vinod Kould93f8e52015-10-07 11:31:54 +01001017
Dharageswari R260eb732016-06-03 18:29:38 +05301018 if (s_pipe->state == SKL_PIPE_INVALID)
1019 return -EINVAL;
1020
Vinod Kould93f8e52015-10-07 11:31:54 +01001021 skl_tplg_free_pipe_mcps(skl, mconfig);
Vinod Koul65976872015-11-23 22:26:29 +05301022 skl_tplg_free_pipe_mem(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +01001023
1024 list_for_each_entry(w_module, &s_pipe->w_list, node) {
1025 dst_module = w_module->w->priv;
1026
Dharageswari R260eb732016-06-03 18:29:38 +05301027 if (mconfig->m_state >= SKL_MODULE_INIT_DONE)
1028 skl_tplg_free_pipe_mcps(skl, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +01001029 if (src_module == NULL) {
1030 src_module = dst_module;
1031 continue;
1032 }
1033
Guneshwor Singh7ca42f52016-02-03 17:59:46 +05301034 skl_unbind_modules(ctx, src_module, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +01001035 src_module = dst_module;
1036 }
1037
Vinod Koul547cafa2016-12-08 23:01:24 +05301038 skl_delete_pipe(ctx, mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +01001039
Jeeja KP473a4d52017-03-24 23:10:33 +05301040 list_for_each_entry(w_module, &s_pipe->w_list, node) {
1041 src_module = w_module->w->priv;
1042 src_module->m_state = SKL_MODULE_UNINIT;
1043 }
1044
Dharageswari R6c5768b2015-12-03 23:29:50 +05301045 return skl_tplg_unload_pipe_modules(ctx, s_pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +01001046}
1047
1048/*
1049 * in the Post-PMD event of PGA we need to do following:
1050 * - Free the mcps used
1051 * - Stop the pipeline
1052 * - In source pipe is connected, unbind with source pipelines
1053 */
1054static int skl_tplg_pga_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
1055 struct skl *skl)
1056{
Vinod Kould93f8e52015-10-07 11:31:54 +01001057 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +09001058 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +01001059 struct skl_sst *ctx = skl->skl_sst;
1060
Jeeja KPce1b5552015-10-27 09:22:51 +09001061 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +01001062
Vinod Kould93f8e52015-10-07 11:31:54 +01001063 /* Stop the pipe since this is a mixin module */
1064 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
1065 if (ret)
1066 return ret;
1067
Jeeja KPce1b5552015-10-27 09:22:51 +09001068 for (i = 0; i < src_mconfig->max_out_queue; i++) {
1069 if (src_mconfig->m_out_pin[i].pin_state == SKL_PIN_BIND_DONE) {
1070 sink_mconfig = src_mconfig->m_out_pin[i].tgt_mcfg;
1071 if (!sink_mconfig)
1072 continue;
1073 /*
1074 * This is a connecter and if path is found that means
1075 * unbind between source and sink has not happened yet
1076 */
Jeeja KPce1b5552015-10-27 09:22:51 +09001077 ret = skl_unbind_modules(ctx, src_mconfig,
1078 sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +01001079 }
1080 }
1081
Vinod Kould93f8e52015-10-07 11:31:54 +01001082 return ret;
1083}
1084
1085/*
Vinod Kould93f8e52015-10-07 11:31:54 +01001086 * In modelling, we assume there will be ONLY one mixer in a pipeline. If a
1087 * second one is required that is created as another pipe entity.
1088 * The mixer is responsible for pipe management and represent a pipeline
1089 * instance
1090 */
1091static int skl_tplg_mixer_event(struct snd_soc_dapm_widget *w,
1092 struct snd_kcontrol *k, int event)
1093{
1094 struct snd_soc_dapm_context *dapm = w->dapm;
1095 struct skl *skl = get_skl_ctx(dapm->dev);
1096
1097 switch (event) {
1098 case SND_SOC_DAPM_PRE_PMU:
1099 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
1100
1101 case SND_SOC_DAPM_POST_PMU:
1102 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
1103
1104 case SND_SOC_DAPM_PRE_PMD:
1105 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
1106
1107 case SND_SOC_DAPM_POST_PMD:
1108 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
1109 }
1110
1111 return 0;
1112}
1113
1114/*
1115 * In modelling, we assumed rest of the modules in pipeline are PGA. But we
1116 * are interested in last PGA (leaf PGA) in a pipeline to disconnect with
1117 * the sink when it is running (two FE to one BE or one FE to two BE)
1118 * scenarios
1119 */
1120static int skl_tplg_pga_event(struct snd_soc_dapm_widget *w,
1121 struct snd_kcontrol *k, int event)
1122
1123{
1124 struct snd_soc_dapm_context *dapm = w->dapm;
1125 struct skl *skl = get_skl_ctx(dapm->dev);
1126
1127 switch (event) {
1128 case SND_SOC_DAPM_PRE_PMU:
1129 return skl_tplg_pga_dapm_pre_pmu_event(w, skl);
1130
1131 case SND_SOC_DAPM_POST_PMD:
1132 return skl_tplg_pga_dapm_post_pmd_event(w, skl);
1133 }
1134
1135 return 0;
1136}
Vinod Koulcfb0a872015-10-07 11:31:55 +01001137
Jeeja KP140adfb2015-11-28 15:01:50 +05301138static int skl_tplg_tlv_control_get(struct snd_kcontrol *kcontrol,
1139 unsigned int __user *data, unsigned int size)
1140{
1141 struct soc_bytes_ext *sb =
1142 (struct soc_bytes_ext *)kcontrol->private_value;
1143 struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private;
Omair M Abdullah7d9f2912015-12-03 23:29:56 +05301144 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
1145 struct skl_module_cfg *mconfig = w->priv;
1146 struct skl *skl = get_skl_ctx(w->dapm->dev);
1147
1148 if (w->power)
1149 skl_get_module_params(skl->skl_sst, (u32 *)bc->params,
Dharageswari R0d682102016-07-08 18:15:03 +05301150 bc->size, bc->param_id, mconfig);
Jeeja KP140adfb2015-11-28 15:01:50 +05301151
Vinod Koul41556f62016-02-03 17:59:44 +05301152 /* decrement size for TLV header */
1153 size -= 2 * sizeof(u32);
1154
1155 /* check size as we don't want to send kernel data */
1156 if (size > bc->max)
1157 size = bc->max;
1158
Jeeja KP140adfb2015-11-28 15:01:50 +05301159 if (bc->params) {
1160 if (copy_to_user(data, &bc->param_id, sizeof(u32)))
1161 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +03001162 if (copy_to_user(data + 1, &size, sizeof(u32)))
Jeeja KP140adfb2015-11-28 15:01:50 +05301163 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +03001164 if (copy_to_user(data + 2, bc->params, size))
Jeeja KP140adfb2015-11-28 15:01:50 +05301165 return -EFAULT;
1166 }
1167
1168 return 0;
1169}
1170
1171#define SKL_PARAM_VENDOR_ID 0xff
1172
1173static int skl_tplg_tlv_control_set(struct snd_kcontrol *kcontrol,
1174 const unsigned int __user *data, unsigned int size)
1175{
1176 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
1177 struct skl_module_cfg *mconfig = w->priv;
1178 struct soc_bytes_ext *sb =
1179 (struct soc_bytes_ext *)kcontrol->private_value;
1180 struct skl_algo_data *ac = (struct skl_algo_data *)sb->dobj.private;
1181 struct skl *skl = get_skl_ctx(w->dapm->dev);
1182
1183 if (ac->params) {
Dharageswari R0d682102016-07-08 18:15:03 +05301184 if (size > ac->max)
1185 return -EINVAL;
1186
1187 ac->size = size;
Jeeja KP140adfb2015-11-28 15:01:50 +05301188 /*
1189 * if the param_is is of type Vendor, firmware expects actual
1190 * parameter id and size from the control.
1191 */
1192 if (ac->param_id == SKL_PARAM_VENDOR_ID) {
1193 if (copy_from_user(ac->params, data, size))
1194 return -EFAULT;
1195 } else {
1196 if (copy_from_user(ac->params,
Alan65b4bcb2016-02-19 11:42:32 +05301197 data + 2, size))
Jeeja KP140adfb2015-11-28 15:01:50 +05301198 return -EFAULT;
1199 }
1200
1201 if (w->power)
1202 return skl_set_module_params(skl->skl_sst,
Dharageswari R0d682102016-07-08 18:15:03 +05301203 (u32 *)ac->params, ac->size,
Jeeja KP140adfb2015-11-28 15:01:50 +05301204 ac->param_id, mconfig);
1205 }
1206
1207 return 0;
1208}
1209
Vinod Koulcfb0a872015-10-07 11:31:55 +01001210/*
Jeeja KP8871dcb2016-06-03 18:29:42 +05301211 * Fill the dma id for host and link. In case of passthrough
1212 * pipeline, this will both host and link in the same
1213 * pipeline, so need to copy the link and host based on dev_type
1214 */
1215static void skl_tplg_fill_dma_id(struct skl_module_cfg *mcfg,
1216 struct skl_pipe_params *params)
1217{
1218 struct skl_pipe *pipe = mcfg->pipe;
1219
1220 if (pipe->passthru) {
1221 switch (mcfg->dev_type) {
1222 case SKL_DEVICE_HDALINK:
1223 pipe->p_params->link_dma_id = params->link_dma_id;
Jeeja KP12c3be02016-12-08 13:41:12 +05301224 pipe->p_params->link_index = params->link_index;
Jeeja KP7f975a32017-03-24 23:10:25 +05301225 pipe->p_params->link_bps = params->link_bps;
Jeeja KP8871dcb2016-06-03 18:29:42 +05301226 break;
1227
1228 case SKL_DEVICE_HDAHOST:
1229 pipe->p_params->host_dma_id = params->host_dma_id;
Jeeja KP7f975a32017-03-24 23:10:25 +05301230 pipe->p_params->host_bps = params->host_bps;
Jeeja KP8871dcb2016-06-03 18:29:42 +05301231 break;
1232
1233 default:
1234 break;
1235 }
1236 pipe->p_params->s_fmt = params->s_fmt;
1237 pipe->p_params->ch = params->ch;
1238 pipe->p_params->s_freq = params->s_freq;
1239 pipe->p_params->stream = params->stream;
Jeeja KP12c3be02016-12-08 13:41:12 +05301240 pipe->p_params->format = params->format;
Jeeja KP8871dcb2016-06-03 18:29:42 +05301241
1242 } else {
1243 memcpy(pipe->p_params, params, sizeof(*params));
1244 }
1245}
1246
1247/*
Vinod Koulcfb0a872015-10-07 11:31:55 +01001248 * The FE params are passed by hw_params of the DAI.
1249 * On hw_params, the params are stored in Gateway module of the FE and we
1250 * need to calculate the format in DSP module configuration, that
1251 * conversion is done here
1252 */
1253int skl_tplg_update_pipe_params(struct device *dev,
1254 struct skl_module_cfg *mconfig,
1255 struct skl_pipe_params *params)
1256{
Vinod Koulcfb0a872015-10-07 11:31:55 +01001257 struct skl_module_fmt *format = NULL;
1258
Jeeja KP8871dcb2016-06-03 18:29:42 +05301259 skl_tplg_fill_dma_id(mconfig, params);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001260
1261 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK)
Hardik T Shah4cd98992015-10-27 09:22:55 +09001262 format = &mconfig->in_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001263 else
Hardik T Shah4cd98992015-10-27 09:22:55 +09001264 format = &mconfig->out_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001265
1266 /* set the hw_params */
1267 format->s_freq = params->s_freq;
1268 format->channels = params->ch;
1269 format->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
1270
1271 /*
1272 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
1273 * container so update bit depth accordingly
1274 */
1275 switch (format->valid_bit_depth) {
1276 case SKL_DEPTH_16BIT:
1277 format->bit_depth = format->valid_bit_depth;
1278 break;
1279
1280 case SKL_DEPTH_24BIT:
Jeeja KP6654f392015-10-27 09:22:46 +09001281 case SKL_DEPTH_32BIT:
Vinod Koulcfb0a872015-10-07 11:31:55 +01001282 format->bit_depth = SKL_DEPTH_32BIT;
1283 break;
1284
1285 default:
1286 dev_err(dev, "Invalid bit depth %x for pipe\n",
1287 format->valid_bit_depth);
1288 return -EINVAL;
1289 }
1290
1291 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1292 mconfig->ibs = (format->s_freq / 1000) *
1293 (format->channels) *
1294 (format->bit_depth >> 3);
1295 } else {
1296 mconfig->obs = (format->s_freq / 1000) *
1297 (format->channels) *
1298 (format->bit_depth >> 3);
1299 }
1300
1301 return 0;
1302}
1303
1304/*
1305 * Query the module config for the FE DAI
1306 * This is used to find the hw_params set for that DAI and apply to FE
1307 * pipeline
1308 */
1309struct skl_module_cfg *
1310skl_tplg_fe_get_cpr_module(struct snd_soc_dai *dai, int stream)
1311{
1312 struct snd_soc_dapm_widget *w;
1313 struct snd_soc_dapm_path *p = NULL;
1314
1315 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1316 w = dai->playback_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301317 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001318 if (p->connect && p->sink->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001319 !is_skl_dsp_widget_type(p->sink))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001320 continue;
1321
1322 if (p->sink->priv) {
1323 dev_dbg(dai->dev, "set params for %s\n",
1324 p->sink->name);
1325 return p->sink->priv;
1326 }
1327 }
1328 } else {
1329 w = dai->capture_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301330 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001331 if (p->connect && p->source->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001332 !is_skl_dsp_widget_type(p->source))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001333 continue;
1334
1335 if (p->source->priv) {
1336 dev_dbg(dai->dev, "set params for %s\n",
1337 p->source->name);
1338 return p->source->priv;
1339 }
1340 }
1341 }
1342
1343 return NULL;
1344}
1345
Dharageswari.R718a42b2016-02-05 12:19:06 +05301346static struct skl_module_cfg *skl_get_mconfig_pb_cpr(
1347 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
1348{
1349 struct snd_soc_dapm_path *p;
1350 struct skl_module_cfg *mconfig = NULL;
1351
1352 snd_soc_dapm_widget_for_each_source_path(w, p) {
1353 if (w->endpoints[SND_SOC_DAPM_DIR_OUT] > 0) {
1354 if (p->connect &&
1355 (p->sink->id == snd_soc_dapm_aif_out) &&
1356 p->source->priv) {
1357 mconfig = p->source->priv;
1358 return mconfig;
1359 }
1360 mconfig = skl_get_mconfig_pb_cpr(dai, p->source);
1361 if (mconfig)
1362 return mconfig;
1363 }
1364 }
1365 return mconfig;
1366}
1367
1368static struct skl_module_cfg *skl_get_mconfig_cap_cpr(
1369 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
1370{
1371 struct snd_soc_dapm_path *p;
1372 struct skl_module_cfg *mconfig = NULL;
1373
1374 snd_soc_dapm_widget_for_each_sink_path(w, p) {
1375 if (w->endpoints[SND_SOC_DAPM_DIR_IN] > 0) {
1376 if (p->connect &&
1377 (p->source->id == snd_soc_dapm_aif_in) &&
1378 p->sink->priv) {
1379 mconfig = p->sink->priv;
1380 return mconfig;
1381 }
1382 mconfig = skl_get_mconfig_cap_cpr(dai, p->sink);
1383 if (mconfig)
1384 return mconfig;
1385 }
1386 }
1387 return mconfig;
1388}
1389
1390struct skl_module_cfg *
1391skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, int stream)
1392{
1393 struct snd_soc_dapm_widget *w;
1394 struct skl_module_cfg *mconfig;
1395
1396 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1397 w = dai->playback_widget;
1398 mconfig = skl_get_mconfig_pb_cpr(dai, w);
1399 } else {
1400 w = dai->capture_widget;
1401 mconfig = skl_get_mconfig_cap_cpr(dai, w);
1402 }
1403 return mconfig;
1404}
1405
Vinod Koulcfb0a872015-10-07 11:31:55 +01001406static u8 skl_tplg_be_link_type(int dev_type)
1407{
1408 int ret;
1409
1410 switch (dev_type) {
1411 case SKL_DEVICE_BT:
1412 ret = NHLT_LINK_SSP;
1413 break;
1414
1415 case SKL_DEVICE_DMIC:
1416 ret = NHLT_LINK_DMIC;
1417 break;
1418
1419 case SKL_DEVICE_I2S:
1420 ret = NHLT_LINK_SSP;
1421 break;
1422
1423 case SKL_DEVICE_HDALINK:
1424 ret = NHLT_LINK_HDA;
1425 break;
1426
1427 default:
1428 ret = NHLT_LINK_INVALID;
1429 break;
1430 }
1431
1432 return ret;
1433}
1434
1435/*
1436 * Fill the BE gateway parameters
1437 * The BE gateway expects a blob of parameters which are kept in the ACPI
1438 * NHLT blob, so query the blob for interface type (i2s/pdm) and instance.
1439 * The port can have multiple settings so pick based on the PCM
1440 * parameters
1441 */
1442static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
1443 struct skl_module_cfg *mconfig,
1444 struct skl_pipe_params *params)
1445{
Vinod Koulcfb0a872015-10-07 11:31:55 +01001446 struct nhlt_specific_cfg *cfg;
1447 struct skl *skl = get_skl_ctx(dai->dev);
1448 int link_type = skl_tplg_be_link_type(mconfig->dev_type);
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +05301449 u8 dev_type = skl_tplg_be_dev_type(mconfig->dev_type);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001450
Jeeja KP8871dcb2016-06-03 18:29:42 +05301451 skl_tplg_fill_dma_id(mconfig, params);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001452
Jeeja KPb30c2752015-10-27 09:22:48 +09001453 if (link_type == NHLT_LINK_HDA)
1454 return 0;
1455
Vinod Koulcfb0a872015-10-07 11:31:55 +01001456 /* update the blob based on virtual bus_id*/
1457 cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type,
1458 params->s_fmt, params->ch,
Senthilnathan Veppurdb2f5862017-02-09 16:44:01 +05301459 params->s_freq, params->stream,
1460 dev_type);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001461 if (cfg) {
1462 mconfig->formats_config.caps_size = cfg->size;
Jeeja KPbc032812015-10-22 23:22:35 +05301463 mconfig->formats_config.caps = (u32 *) &cfg->caps;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001464 } else {
1465 dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n",
1466 mconfig->vbus_id, link_type,
1467 params->stream);
1468 dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n",
1469 params->ch, params->s_freq, params->s_fmt);
1470 return -EINVAL;
1471 }
1472
1473 return 0;
1474}
1475
1476static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai,
1477 struct snd_soc_dapm_widget *w,
1478 struct skl_pipe_params *params)
1479{
1480 struct snd_soc_dapm_path *p;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301481 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001482
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301483 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001484 if (p->connect && is_skl_dsp_widget_type(p->source) &&
1485 p->source->priv) {
1486
Jeeja KP9a03cb42015-10-27 09:22:54 +09001487 ret = skl_tplg_be_fill_pipe_params(dai,
1488 p->source->priv, params);
1489 if (ret < 0)
1490 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001491 } else {
Jeeja KP9a03cb42015-10-27 09:22:54 +09001492 ret = skl_tplg_be_set_src_pipe_params(dai,
1493 p->source, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301494 if (ret < 0)
1495 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001496 }
1497 }
1498
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301499 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001500}
1501
1502static int skl_tplg_be_set_sink_pipe_params(struct snd_soc_dai *dai,
1503 struct snd_soc_dapm_widget *w, struct skl_pipe_params *params)
1504{
1505 struct snd_soc_dapm_path *p = NULL;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301506 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001507
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301508 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001509 if (p->connect && is_skl_dsp_widget_type(p->sink) &&
1510 p->sink->priv) {
1511
Jeeja KP9a03cb42015-10-27 09:22:54 +09001512 ret = skl_tplg_be_fill_pipe_params(dai,
1513 p->sink->priv, params);
1514 if (ret < 0)
1515 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001516 } else {
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301517 ret = skl_tplg_be_set_sink_pipe_params(
Vinod Koulcfb0a872015-10-07 11:31:55 +01001518 dai, p->sink, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301519 if (ret < 0)
1520 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001521 }
1522 }
1523
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301524 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001525}
1526
1527/*
1528 * BE hw_params can be a source parameters (capture) or sink parameters
1529 * (playback). Based on sink and source we need to either find the source
1530 * list or the sink list and set the pipeline parameters
1531 */
1532int skl_tplg_be_update_params(struct snd_soc_dai *dai,
1533 struct skl_pipe_params *params)
1534{
1535 struct snd_soc_dapm_widget *w;
1536
1537 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1538 w = dai->playback_widget;
1539
1540 return skl_tplg_be_set_src_pipe_params(dai, w, params);
1541
1542 } else {
1543 w = dai->capture_widget;
1544
1545 return skl_tplg_be_set_sink_pipe_params(dai, w, params);
1546 }
1547
1548 return 0;
1549}
Vinod Koul3af36702015-10-07 11:31:56 +01001550
1551static const struct snd_soc_tplg_widget_events skl_tplg_widget_ops[] = {
1552 {SKL_MIXER_EVENT, skl_tplg_mixer_event},
Vinod Koul9a1e3502017-03-24 23:10:29 +05301553 {SKL_VMIXER_EVENT, skl_tplg_mixer_event},
Vinod Koul3af36702015-10-07 11:31:56 +01001554 {SKL_PGA_EVENT, skl_tplg_pga_event},
1555};
1556
Jeeja KP140adfb2015-11-28 15:01:50 +05301557static const struct snd_soc_tplg_bytes_ext_ops skl_tlv_ops[] = {
1558 {SKL_CONTROL_TYPE_BYTE_TLV, skl_tplg_tlv_control_get,
1559 skl_tplg_tlv_control_set},
1560};
1561
Shreyas NC6277e832016-08-12 12:29:51 +05301562static int skl_tplg_fill_pipe_tkn(struct device *dev,
1563 struct skl_pipe *pipe, u32 tkn,
1564 u32 tkn_val)
Vinod Koul3af36702015-10-07 11:31:56 +01001565{
Vinod Koul3af36702015-10-07 11:31:56 +01001566
Shreyas NC6277e832016-08-12 12:29:51 +05301567 switch (tkn) {
1568 case SKL_TKN_U32_PIPE_CONN_TYPE:
1569 pipe->conn_type = tkn_val;
1570 break;
1571
1572 case SKL_TKN_U32_PIPE_PRIORITY:
1573 pipe->pipe_priority = tkn_val;
1574 break;
1575
1576 case SKL_TKN_U32_PIPE_MEM_PGS:
1577 pipe->memory_pages = tkn_val;
1578 break;
1579
Vinod Koul8a0cb232016-11-03 17:07:18 +05301580 case SKL_TKN_U32_PMODE:
1581 pipe->lp_mode = tkn_val;
1582 break;
1583
Shreyas NC6277e832016-08-12 12:29:51 +05301584 default:
1585 dev_err(dev, "Token not handled %d\n", tkn);
1586 return -EINVAL;
Vinod Koul3af36702015-10-07 11:31:56 +01001587 }
Shreyas NC6277e832016-08-12 12:29:51 +05301588
1589 return 0;
Vinod Koul3af36702015-10-07 11:31:56 +01001590}
1591
1592/*
Shreyas NC6277e832016-08-12 12:29:51 +05301593 * Add pipeline by parsing the relevant tokens
1594 * Return an existing pipe if the pipe already exists.
Vinod Koul3af36702015-10-07 11:31:56 +01001595 */
Shreyas NC6277e832016-08-12 12:29:51 +05301596static int skl_tplg_add_pipe(struct device *dev,
1597 struct skl_module_cfg *mconfig, struct skl *skl,
1598 struct snd_soc_tplg_vendor_value_elem *tkn_elem)
Vinod Koul3af36702015-10-07 11:31:56 +01001599{
1600 struct skl_pipeline *ppl;
1601 struct skl_pipe *pipe;
1602 struct skl_pipe_params *params;
1603
1604 list_for_each_entry(ppl, &skl->ppl_list, node) {
Shreyas NC6277e832016-08-12 12:29:51 +05301605 if (ppl->pipe->ppl_id == tkn_elem->value) {
1606 mconfig->pipe = ppl->pipe;
1607 return EEXIST;
1608 }
Vinod Koul3af36702015-10-07 11:31:56 +01001609 }
1610
1611 ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL);
1612 if (!ppl)
Shreyas NC6277e832016-08-12 12:29:51 +05301613 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001614
1615 pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL);
1616 if (!pipe)
Shreyas NC6277e832016-08-12 12:29:51 +05301617 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001618
1619 params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL);
1620 if (!params)
Shreyas NC6277e832016-08-12 12:29:51 +05301621 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001622
Vinod Koul3af36702015-10-07 11:31:56 +01001623 pipe->p_params = params;
Shreyas NC6277e832016-08-12 12:29:51 +05301624 pipe->ppl_id = tkn_elem->value;
Vinod Koul3af36702015-10-07 11:31:56 +01001625 INIT_LIST_HEAD(&pipe->w_list);
1626
1627 ppl->pipe = pipe;
1628 list_add(&ppl->node, &skl->ppl_list);
1629
Shreyas NC6277e832016-08-12 12:29:51 +05301630 mconfig->pipe = pipe;
1631 mconfig->pipe->state = SKL_PIPE_INVALID;
1632
1633 return 0;
Vinod Koul3af36702015-10-07 11:31:56 +01001634}
1635
Shreyas NC6277e832016-08-12 12:29:51 +05301636static int skl_tplg_fill_pin(struct device *dev, u32 tkn,
1637 struct skl_module_pin *m_pin,
1638 int pin_index, u32 value)
1639{
1640 switch (tkn) {
1641 case SKL_TKN_U32_PIN_MOD_ID:
1642 m_pin[pin_index].id.module_id = value;
1643 break;
1644
1645 case SKL_TKN_U32_PIN_INST_ID:
1646 m_pin[pin_index].id.instance_id = value;
1647 break;
1648
1649 default:
1650 dev_err(dev, "%d Not a pin token\n", value);
1651 return -EINVAL;
1652 }
1653
1654 return 0;
1655}
1656
1657/*
1658 * Parse for pin config specific tokens to fill up the
1659 * module private data
1660 */
1661static int skl_tplg_fill_pins_info(struct device *dev,
1662 struct skl_module_cfg *mconfig,
1663 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
1664 int dir, int pin_count)
1665{
1666 int ret;
1667 struct skl_module_pin *m_pin;
1668
1669 switch (dir) {
1670 case SKL_DIR_IN:
1671 m_pin = mconfig->m_in_pin;
1672 break;
1673
1674 case SKL_DIR_OUT:
1675 m_pin = mconfig->m_out_pin;
1676 break;
1677
1678 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001679 dev_err(dev, "Invalid direction value\n");
Shreyas NC6277e832016-08-12 12:29:51 +05301680 return -EINVAL;
1681 }
1682
1683 ret = skl_tplg_fill_pin(dev, tkn_elem->token,
1684 m_pin, pin_count, tkn_elem->value);
1685
1686 if (ret < 0)
1687 return ret;
1688
1689 m_pin[pin_count].in_use = false;
1690 m_pin[pin_count].pin_state = SKL_PIN_UNBIND;
1691
1692 return 0;
1693}
1694
1695/*
1696 * Fill up input/output module config format based
1697 * on the direction
1698 */
1699static int skl_tplg_fill_fmt(struct device *dev,
1700 struct skl_module_cfg *mconfig, u32 tkn,
1701 u32 value, u32 dir, u32 pin_count)
1702{
1703 struct skl_module_fmt *dst_fmt;
1704
1705 switch (dir) {
1706 case SKL_DIR_IN:
1707 dst_fmt = mconfig->in_fmt;
1708 dst_fmt += pin_count;
1709 break;
1710
1711 case SKL_DIR_OUT:
1712 dst_fmt = mconfig->out_fmt;
1713 dst_fmt += pin_count;
1714 break;
1715
1716 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001717 dev_err(dev, "Invalid direction value\n");
Shreyas NC6277e832016-08-12 12:29:51 +05301718 return -EINVAL;
1719 }
1720
1721 switch (tkn) {
1722 case SKL_TKN_U32_FMT_CH:
1723 dst_fmt->channels = value;
1724 break;
1725
1726 case SKL_TKN_U32_FMT_FREQ:
1727 dst_fmt->s_freq = value;
1728 break;
1729
1730 case SKL_TKN_U32_FMT_BIT_DEPTH:
1731 dst_fmt->bit_depth = value;
1732 break;
1733
1734 case SKL_TKN_U32_FMT_SAMPLE_SIZE:
1735 dst_fmt->valid_bit_depth = value;
1736 break;
1737
1738 case SKL_TKN_U32_FMT_CH_CONFIG:
1739 dst_fmt->ch_cfg = value;
1740 break;
1741
1742 case SKL_TKN_U32_FMT_INTERLEAVE:
1743 dst_fmt->interleaving_style = value;
1744 break;
1745
1746 case SKL_TKN_U32_FMT_SAMPLE_TYPE:
1747 dst_fmt->sample_type = value;
1748 break;
1749
1750 case SKL_TKN_U32_FMT_CH_MAP:
1751 dst_fmt->ch_map = value;
1752 break;
1753
1754 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001755 dev_err(dev, "Invalid token %d\n", tkn);
Shreyas NC6277e832016-08-12 12:29:51 +05301756 return -EINVAL;
1757 }
1758
1759 return 0;
1760}
1761
1762static int skl_tplg_get_uuid(struct device *dev, struct skl_module_cfg *mconfig,
1763 struct snd_soc_tplg_vendor_uuid_elem *uuid_tkn)
1764{
1765 if (uuid_tkn->token == SKL_TKN_UUID)
1766 memcpy(&mconfig->guid, &uuid_tkn->uuid, 16);
1767 else {
Colin Ian Kingecd286a2016-09-16 18:51:21 +01001768 dev_err(dev, "Not an UUID token tkn %d\n", uuid_tkn->token);
Shreyas NC6277e832016-08-12 12:29:51 +05301769 return -EINVAL;
1770 }
1771
1772 return 0;
1773}
1774
1775static void skl_tplg_fill_pin_dynamic_val(
1776 struct skl_module_pin *mpin, u32 pin_count, u32 value)
Hardik T Shah4cd98992015-10-27 09:22:55 +09001777{
1778 int i;
1779
Shreyas NC6277e832016-08-12 12:29:51 +05301780 for (i = 0; i < pin_count; i++)
1781 mpin[i].is_dynamic = value;
1782}
1783
1784/*
1785 * Parse tokens to fill up the module private data
1786 */
1787static int skl_tplg_get_token(struct device *dev,
1788 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
1789 struct skl *skl, struct skl_module_cfg *mconfig)
1790{
1791 int tkn_count = 0;
1792 int ret;
1793 static int is_pipe_exists;
1794 static int pin_index, dir;
1795
1796 if (tkn_elem->token > SKL_TKN_MAX)
1797 return -EINVAL;
1798
1799 switch (tkn_elem->token) {
1800 case SKL_TKN_U8_IN_QUEUE_COUNT:
1801 mconfig->max_in_queue = tkn_elem->value;
1802 mconfig->m_in_pin = devm_kzalloc(dev, mconfig->max_in_queue *
1803 sizeof(*mconfig->m_in_pin),
1804 GFP_KERNEL);
1805 if (!mconfig->m_in_pin)
1806 return -ENOMEM;
1807
1808 break;
1809
1810 case SKL_TKN_U8_OUT_QUEUE_COUNT:
1811 mconfig->max_out_queue = tkn_elem->value;
1812 mconfig->m_out_pin = devm_kzalloc(dev, mconfig->max_out_queue *
1813 sizeof(*mconfig->m_out_pin),
1814 GFP_KERNEL);
1815
1816 if (!mconfig->m_out_pin)
1817 return -ENOMEM;
1818
1819 break;
1820
1821 case SKL_TKN_U8_DYN_IN_PIN:
1822 if (!mconfig->m_in_pin)
1823 return -ENOMEM;
1824
1825 skl_tplg_fill_pin_dynamic_val(mconfig->m_in_pin,
1826 mconfig->max_in_queue, tkn_elem->value);
1827
1828 break;
1829
1830 case SKL_TKN_U8_DYN_OUT_PIN:
1831 if (!mconfig->m_out_pin)
1832 return -ENOMEM;
1833
1834 skl_tplg_fill_pin_dynamic_val(mconfig->m_out_pin,
1835 mconfig->max_out_queue, tkn_elem->value);
1836
1837 break;
1838
1839 case SKL_TKN_U8_TIME_SLOT:
1840 mconfig->time_slot = tkn_elem->value;
1841 break;
1842
1843 case SKL_TKN_U8_CORE_ID:
1844 mconfig->core_id = tkn_elem->value;
1845
1846 case SKL_TKN_U8_MOD_TYPE:
1847 mconfig->m_type = tkn_elem->value;
1848 break;
1849
1850 case SKL_TKN_U8_DEV_TYPE:
1851 mconfig->dev_type = tkn_elem->value;
1852 break;
1853
1854 case SKL_TKN_U8_HW_CONN_TYPE:
1855 mconfig->hw_conn_type = tkn_elem->value;
1856 break;
1857
1858 case SKL_TKN_U16_MOD_INST_ID:
1859 mconfig->id.instance_id =
1860 tkn_elem->value;
1861 break;
1862
1863 case SKL_TKN_U32_MEM_PAGES:
1864 mconfig->mem_pages = tkn_elem->value;
1865 break;
1866
1867 case SKL_TKN_U32_MAX_MCPS:
1868 mconfig->mcps = tkn_elem->value;
1869 break;
1870
1871 case SKL_TKN_U32_OBS:
1872 mconfig->obs = tkn_elem->value;
1873 break;
1874
1875 case SKL_TKN_U32_IBS:
1876 mconfig->ibs = tkn_elem->value;
1877 break;
1878
1879 case SKL_TKN_U32_VBUS_ID:
1880 mconfig->vbus_id = tkn_elem->value;
1881 break;
1882
1883 case SKL_TKN_U32_PARAMS_FIXUP:
1884 mconfig->params_fixup = tkn_elem->value;
1885 break;
1886
1887 case SKL_TKN_U32_CONVERTER:
1888 mconfig->converter = tkn_elem->value;
1889 break;
1890
Vinod Koul6bd9dcf2016-11-03 17:07:19 +05301891 case SKL_TKL_U32_D0I3_CAPS:
1892 mconfig->d0i3_caps = tkn_elem->value;
1893 break;
1894
Shreyas NC6277e832016-08-12 12:29:51 +05301895 case SKL_TKN_U32_PIPE_ID:
1896 ret = skl_tplg_add_pipe(dev,
1897 mconfig, skl, tkn_elem);
1898
1899 if (ret < 0)
1900 return is_pipe_exists;
1901
1902 if (ret == EEXIST)
1903 is_pipe_exists = 1;
1904
1905 break;
1906
1907 case SKL_TKN_U32_PIPE_CONN_TYPE:
1908 case SKL_TKN_U32_PIPE_PRIORITY:
1909 case SKL_TKN_U32_PIPE_MEM_PGS:
Vinod Koul8a0cb232016-11-03 17:07:18 +05301910 case SKL_TKN_U32_PMODE:
Shreyas NC6277e832016-08-12 12:29:51 +05301911 if (is_pipe_exists) {
1912 ret = skl_tplg_fill_pipe_tkn(dev, mconfig->pipe,
1913 tkn_elem->token, tkn_elem->value);
1914 if (ret < 0)
1915 return ret;
1916 }
1917
1918 break;
1919
1920 /*
1921 * SKL_TKN_U32_DIR_PIN_COUNT token has the value for both
1922 * direction and the pin count. The first four bits represent
1923 * direction and next four the pin count.
1924 */
1925 case SKL_TKN_U32_DIR_PIN_COUNT:
1926 dir = tkn_elem->value & SKL_IN_DIR_BIT_MASK;
1927 pin_index = (tkn_elem->value &
1928 SKL_PIN_COUNT_MASK) >> 4;
1929
1930 break;
1931
1932 case SKL_TKN_U32_FMT_CH:
1933 case SKL_TKN_U32_FMT_FREQ:
1934 case SKL_TKN_U32_FMT_BIT_DEPTH:
1935 case SKL_TKN_U32_FMT_SAMPLE_SIZE:
1936 case SKL_TKN_U32_FMT_CH_CONFIG:
1937 case SKL_TKN_U32_FMT_INTERLEAVE:
1938 case SKL_TKN_U32_FMT_SAMPLE_TYPE:
1939 case SKL_TKN_U32_FMT_CH_MAP:
1940 ret = skl_tplg_fill_fmt(dev, mconfig, tkn_elem->token,
1941 tkn_elem->value, dir, pin_index);
1942
1943 if (ret < 0)
1944 return ret;
1945
1946 break;
1947
1948 case SKL_TKN_U32_PIN_MOD_ID:
1949 case SKL_TKN_U32_PIN_INST_ID:
1950 ret = skl_tplg_fill_pins_info(dev,
1951 mconfig, tkn_elem, dir,
1952 pin_index);
1953 if (ret < 0)
1954 return ret;
1955
1956 break;
1957
1958 case SKL_TKN_U32_CAPS_SIZE:
1959 mconfig->formats_config.caps_size =
1960 tkn_elem->value;
1961
1962 break;
1963
1964 case SKL_TKN_U32_PROC_DOMAIN:
1965 mconfig->domain =
1966 tkn_elem->value;
1967
1968 break;
1969
1970 case SKL_TKN_U8_IN_PIN_TYPE:
1971 case SKL_TKN_U8_OUT_PIN_TYPE:
1972 case SKL_TKN_U8_CONN_TYPE:
1973 break;
1974
1975 default:
1976 dev_err(dev, "Token %d not handled\n",
1977 tkn_elem->token);
1978 return -EINVAL;
Hardik T Shah4cd98992015-10-27 09:22:55 +09001979 }
Shreyas NC6277e832016-08-12 12:29:51 +05301980
1981 tkn_count++;
1982
1983 return tkn_count;
1984}
1985
1986/*
1987 * Parse the vendor array for specific tokens to construct
1988 * module private data
1989 */
1990static int skl_tplg_get_tokens(struct device *dev,
1991 char *pvt_data, struct skl *skl,
1992 struct skl_module_cfg *mconfig, int block_size)
1993{
1994 struct snd_soc_tplg_vendor_array *array;
1995 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
1996 int tkn_count = 0, ret;
1997 int off = 0, tuple_size = 0;
1998
1999 if (block_size <= 0)
2000 return -EINVAL;
2001
2002 while (tuple_size < block_size) {
2003 array = (struct snd_soc_tplg_vendor_array *)(pvt_data + off);
2004
2005 off += array->size;
2006
2007 switch (array->type) {
2008 case SND_SOC_TPLG_TUPLE_TYPE_STRING:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002009 dev_warn(dev, "no string tokens expected for skl tplg\n");
Shreyas NC6277e832016-08-12 12:29:51 +05302010 continue;
2011
2012 case SND_SOC_TPLG_TUPLE_TYPE_UUID:
2013 ret = skl_tplg_get_uuid(dev, mconfig, array->uuid);
2014 if (ret < 0)
2015 return ret;
2016
2017 tuple_size += sizeof(*array->uuid);
2018
2019 continue;
2020
2021 default:
2022 tkn_elem = array->value;
2023 tkn_count = 0;
2024 break;
2025 }
2026
2027 while (tkn_count <= (array->num_elems - 1)) {
2028 ret = skl_tplg_get_token(dev, tkn_elem,
2029 skl, mconfig);
2030
2031 if (ret < 0)
2032 return ret;
2033
2034 tkn_count = tkn_count + ret;
2035 tkn_elem++;
2036 }
2037
2038 tuple_size += tkn_count * sizeof(*tkn_elem);
2039 }
2040
2041 return 0;
2042}
2043
2044/*
2045 * Every data block is preceded by a descriptor to read the number
2046 * of data blocks, they type of the block and it's size
2047 */
2048static int skl_tplg_get_desc_blocks(struct device *dev,
2049 struct snd_soc_tplg_vendor_array *array)
2050{
2051 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
2052
2053 tkn_elem = array->value;
2054
2055 switch (tkn_elem->token) {
2056 case SKL_TKN_U8_NUM_BLOCKS:
2057 case SKL_TKN_U8_BLOCK_TYPE:
2058 case SKL_TKN_U16_BLOCK_SIZE:
2059 return tkn_elem->value;
2060
2061 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002062 dev_err(dev, "Invalid descriptor token %d\n", tkn_elem->token);
Shreyas NC6277e832016-08-12 12:29:51 +05302063 break;
2064 }
2065
2066 return -EINVAL;
2067}
2068
2069/*
2070 * Parse the private data for the token and corresponding value.
2071 * The private data can have multiple data blocks. So, a data block
2072 * is preceded by a descriptor for number of blocks and a descriptor
2073 * for the type and size of the suceeding data block.
2074 */
2075static int skl_tplg_get_pvt_data(struct snd_soc_tplg_dapm_widget *tplg_w,
2076 struct skl *skl, struct device *dev,
2077 struct skl_module_cfg *mconfig)
2078{
2079 struct snd_soc_tplg_vendor_array *array;
2080 int num_blocks, block_size = 0, block_type, off = 0;
2081 char *data;
2082 int ret;
2083
2084 /* Read the NUM_DATA_BLOCKS descriptor */
2085 array = (struct snd_soc_tplg_vendor_array *)tplg_w->priv.data;
2086 ret = skl_tplg_get_desc_blocks(dev, array);
2087 if (ret < 0)
2088 return ret;
2089 num_blocks = ret;
2090
2091 off += array->size;
2092 array = (struct snd_soc_tplg_vendor_array *)(tplg_w->priv.data + off);
2093
2094 /* Read the BLOCK_TYPE and BLOCK_SIZE descriptor */
2095 while (num_blocks > 0) {
2096 ret = skl_tplg_get_desc_blocks(dev, array);
2097
2098 if (ret < 0)
2099 return ret;
2100 block_type = ret;
2101 off += array->size;
2102
2103 array = (struct snd_soc_tplg_vendor_array *)
2104 (tplg_w->priv.data + off);
2105
2106 ret = skl_tplg_get_desc_blocks(dev, array);
2107
2108 if (ret < 0)
2109 return ret;
2110 block_size = ret;
2111 off += array->size;
2112
2113 array = (struct snd_soc_tplg_vendor_array *)
2114 (tplg_w->priv.data + off);
2115
2116 data = (tplg_w->priv.data + off);
2117
2118 if (block_type == SKL_TYPE_TUPLE) {
2119 ret = skl_tplg_get_tokens(dev, data,
2120 skl, mconfig, block_size);
2121
2122 if (ret < 0)
2123 return ret;
2124
2125 --num_blocks;
2126 } else {
2127 if (mconfig->formats_config.caps_size > 0)
2128 memcpy(mconfig->formats_config.caps, data,
2129 mconfig->formats_config.caps_size);
2130 --num_blocks;
2131 }
2132 }
2133
2134 return 0;
Hardik T Shah4cd98992015-10-27 09:22:55 +09002135}
2136
Dharageswari Rfe3f4442016-06-03 18:29:39 +05302137static void skl_clear_pin_config(struct snd_soc_platform *platform,
2138 struct snd_soc_dapm_widget *w)
2139{
2140 int i;
2141 struct skl_module_cfg *mconfig;
2142 struct skl_pipe *pipe;
2143
2144 if (!strncmp(w->dapm->component->name, platform->component.name,
2145 strlen(platform->component.name))) {
2146 mconfig = w->priv;
2147 pipe = mconfig->pipe;
2148 for (i = 0; i < mconfig->max_in_queue; i++) {
2149 mconfig->m_in_pin[i].in_use = false;
2150 mconfig->m_in_pin[i].pin_state = SKL_PIN_UNBIND;
2151 }
2152 for (i = 0; i < mconfig->max_out_queue; i++) {
2153 mconfig->m_out_pin[i].in_use = false;
2154 mconfig->m_out_pin[i].pin_state = SKL_PIN_UNBIND;
2155 }
2156 pipe->state = SKL_PIPE_INVALID;
2157 mconfig->m_state = SKL_MODULE_UNINIT;
2158 }
2159}
2160
2161void skl_cleanup_resources(struct skl *skl)
2162{
2163 struct skl_sst *ctx = skl->skl_sst;
2164 struct snd_soc_platform *soc_platform = skl->platform;
2165 struct snd_soc_dapm_widget *w;
2166 struct snd_soc_card *card;
2167
2168 if (soc_platform == NULL)
2169 return;
2170
2171 card = soc_platform->component.card;
2172 if (!card || !card->instantiated)
2173 return;
2174
2175 skl->resource.mem = 0;
2176 skl->resource.mcps = 0;
2177
2178 list_for_each_entry(w, &card->widgets, list) {
2179 if (is_skl_dsp_widget_type(w) && (w->priv != NULL))
2180 skl_clear_pin_config(soc_platform, w);
2181 }
2182
2183 skl_clear_module_cnt(ctx->dsp);
2184}
2185
Vinod Koul3af36702015-10-07 11:31:56 +01002186/*
2187 * Topology core widget load callback
2188 *
2189 * This is used to save the private data for each widget which gives
2190 * information to the driver about module and pipeline parameters which DSP
2191 * FW expects like ids, resource values, formats etc
2192 */
2193static int skl_tplg_widget_load(struct snd_soc_component *cmpnt,
Jeeja KPb663a8c2015-10-07 11:31:57 +01002194 struct snd_soc_dapm_widget *w,
2195 struct snd_soc_tplg_dapm_widget *tplg_w)
Vinod Koul3af36702015-10-07 11:31:56 +01002196{
2197 int ret;
2198 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2199 struct skl *skl = ebus_to_skl(ebus);
2200 struct hdac_bus *bus = ebus_to_hbus(ebus);
2201 struct skl_module_cfg *mconfig;
Vinod Koul3af36702015-10-07 11:31:56 +01002202
2203 if (!tplg_w->priv.size)
2204 goto bind_event;
2205
2206 mconfig = devm_kzalloc(bus->dev, sizeof(*mconfig), GFP_KERNEL);
2207
2208 if (!mconfig)
2209 return -ENOMEM;
2210
2211 w->priv = mconfig;
Shreyas NC09305da2016-04-21 11:45:22 +05302212
Vinod Koulb7c50552016-07-26 18:06:40 +05302213 /*
2214 * module binary can be loaded later, so set it to query when
2215 * module is load for a use case
2216 */
2217 mconfig->id.module_id = -1;
Hardik T Shah4cd98992015-10-27 09:22:55 +09002218
Shreyas NC6277e832016-08-12 12:29:51 +05302219 /* Parse private data for tuples */
2220 ret = skl_tplg_get_pvt_data(tplg_w, skl, bus->dev, mconfig);
2221 if (ret < 0)
2222 return ret;
Vinod Koul3af36702015-10-07 11:31:56 +01002223bind_event:
2224 if (tplg_w->event_type == 0) {
Vinod Koul3373f712015-10-07 16:39:38 +01002225 dev_dbg(bus->dev, "ASoC: No event handler required\n");
Vinod Koul3af36702015-10-07 11:31:56 +01002226 return 0;
2227 }
2228
2229 ret = snd_soc_tplg_widget_bind_event(w, skl_tplg_widget_ops,
Jeeja KPb663a8c2015-10-07 11:31:57 +01002230 ARRAY_SIZE(skl_tplg_widget_ops),
2231 tplg_w->event_type);
Vinod Koul3af36702015-10-07 11:31:56 +01002232
2233 if (ret) {
2234 dev_err(bus->dev, "%s: No matching event handlers found for %d\n",
2235 __func__, tplg_w->event_type);
2236 return -EINVAL;
2237 }
2238
2239 return 0;
2240}
2241
Jeeja KP140adfb2015-11-28 15:01:50 +05302242static int skl_init_algo_data(struct device *dev, struct soc_bytes_ext *be,
2243 struct snd_soc_tplg_bytes_control *bc)
2244{
2245 struct skl_algo_data *ac;
2246 struct skl_dfw_algo_data *dfw_ac =
2247 (struct skl_dfw_algo_data *)bc->priv.data;
2248
2249 ac = devm_kzalloc(dev, sizeof(*ac), GFP_KERNEL);
2250 if (!ac)
2251 return -ENOMEM;
2252
2253 /* Fill private data */
2254 ac->max = dfw_ac->max;
2255 ac->param_id = dfw_ac->param_id;
2256 ac->set_params = dfw_ac->set_params;
Dharageswari R0d682102016-07-08 18:15:03 +05302257 ac->size = dfw_ac->max;
Jeeja KP140adfb2015-11-28 15:01:50 +05302258
2259 if (ac->max) {
2260 ac->params = (char *) devm_kzalloc(dev, ac->max, GFP_KERNEL);
2261 if (!ac->params)
2262 return -ENOMEM;
2263
Alan Coxedd7ea22016-02-22 09:37:27 +05302264 memcpy(ac->params, dfw_ac->params, ac->max);
Jeeja KP140adfb2015-11-28 15:01:50 +05302265 }
2266
2267 be->dobj.private = ac;
2268 return 0;
2269}
2270
2271static int skl_tplg_control_load(struct snd_soc_component *cmpnt,
2272 struct snd_kcontrol_new *kctl,
2273 struct snd_soc_tplg_ctl_hdr *hdr)
2274{
2275 struct soc_bytes_ext *sb;
2276 struct snd_soc_tplg_bytes_control *tplg_bc;
2277 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2278 struct hdac_bus *bus = ebus_to_hbus(ebus);
2279
2280 switch (hdr->ops.info) {
2281 case SND_SOC_TPLG_CTL_BYTES:
2282 tplg_bc = container_of(hdr,
2283 struct snd_soc_tplg_bytes_control, hdr);
2284 if (kctl->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
2285 sb = (struct soc_bytes_ext *)kctl->private_value;
2286 if (tplg_bc->priv.size)
2287 return skl_init_algo_data(
2288 bus->dev, sb, tplg_bc);
2289 }
2290 break;
2291
2292 default:
2293 dev_warn(bus->dev, "Control load not supported %d:%d:%d\n",
2294 hdr->ops.get, hdr->ops.put, hdr->ops.info);
2295 break;
2296 }
2297
2298 return 0;
2299}
2300
Shreyas NC541070c2016-08-23 09:31:03 +05302301static int skl_tplg_fill_str_mfest_tkn(struct device *dev,
2302 struct snd_soc_tplg_vendor_string_elem *str_elem,
Jeeja KPeee0e162017-01-02 09:50:04 +05302303 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302304{
2305 int tkn_count = 0;
2306 static int ref_count;
2307
2308 switch (str_elem->token) {
2309 case SKL_TKN_STR_LIB_NAME:
Jeeja KPeee0e162017-01-02 09:50:04 +05302310 if (ref_count > skl->skl_sst->lib_count - 1) {
Shreyas NC541070c2016-08-23 09:31:03 +05302311 ref_count = 0;
2312 return -EINVAL;
2313 }
2314
Jeeja KPeee0e162017-01-02 09:50:04 +05302315 strncpy(skl->skl_sst->lib_info[ref_count].name,
2316 str_elem->string,
2317 ARRAY_SIZE(skl->skl_sst->lib_info[ref_count].name));
Shreyas NC541070c2016-08-23 09:31:03 +05302318 ref_count++;
2319 tkn_count++;
2320 break;
2321
2322 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002323 dev_err(dev, "Not a string token %d\n", str_elem->token);
Shreyas NC541070c2016-08-23 09:31:03 +05302324 break;
2325 }
2326
2327 return tkn_count;
2328}
2329
2330static int skl_tplg_get_str_tkn(struct device *dev,
2331 struct snd_soc_tplg_vendor_array *array,
Jeeja KPeee0e162017-01-02 09:50:04 +05302332 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302333{
2334 int tkn_count = 0, ret;
2335 struct snd_soc_tplg_vendor_string_elem *str_elem;
2336
2337 str_elem = (struct snd_soc_tplg_vendor_string_elem *)array->value;
2338 while (tkn_count < array->num_elems) {
Jeeja KPeee0e162017-01-02 09:50:04 +05302339 ret = skl_tplg_fill_str_mfest_tkn(dev, str_elem, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302340 str_elem++;
2341
2342 if (ret < 0)
2343 return ret;
2344
2345 tkn_count = tkn_count + ret;
2346 }
2347
2348 return tkn_count;
2349}
2350
2351static int skl_tplg_get_int_tkn(struct device *dev,
2352 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
Jeeja KPeee0e162017-01-02 09:50:04 +05302353 struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302354{
2355 int tkn_count = 0;
2356
2357 switch (tkn_elem->token) {
2358 case SKL_TKN_U32_LIB_COUNT:
Jeeja KPeee0e162017-01-02 09:50:04 +05302359 skl->skl_sst->lib_count = tkn_elem->value;
Shreyas NC541070c2016-08-23 09:31:03 +05302360 tkn_count++;
2361 break;
2362
2363 default:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002364 dev_err(dev, "Not a manifest token %d\n", tkn_elem->token);
Shreyas NC541070c2016-08-23 09:31:03 +05302365 return -EINVAL;
2366 }
2367
2368 return tkn_count;
2369}
2370
2371/*
2372 * Fill the manifest structure by parsing the tokens based on the
2373 * type.
2374 */
2375static int skl_tplg_get_manifest_tkn(struct device *dev,
Jeeja KPeee0e162017-01-02 09:50:04 +05302376 char *pvt_data, struct skl *skl,
Shreyas NC541070c2016-08-23 09:31:03 +05302377 int block_size)
2378{
2379 int tkn_count = 0, ret;
2380 int off = 0, tuple_size = 0;
2381 struct snd_soc_tplg_vendor_array *array;
2382 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
2383
2384 if (block_size <= 0)
2385 return -EINVAL;
2386
2387 while (tuple_size < block_size) {
2388 array = (struct snd_soc_tplg_vendor_array *)(pvt_data + off);
2389 off += array->size;
2390 switch (array->type) {
2391 case SND_SOC_TPLG_TUPLE_TYPE_STRING:
Jeeja KPeee0e162017-01-02 09:50:04 +05302392 ret = skl_tplg_get_str_tkn(dev, array, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302393
2394 if (ret < 0)
2395 return ret;
2396 tkn_count += ret;
2397
2398 tuple_size += tkn_count *
2399 sizeof(struct snd_soc_tplg_vendor_string_elem);
2400 continue;
2401
2402 case SND_SOC_TPLG_TUPLE_TYPE_UUID:
Colin Ian Kingecd286a2016-09-16 18:51:21 +01002403 dev_warn(dev, "no uuid tokens for skl tplf manifest\n");
Shreyas NC541070c2016-08-23 09:31:03 +05302404 continue;
2405
2406 default:
2407 tkn_elem = array->value;
2408 tkn_count = 0;
2409 break;
2410 }
2411
2412 while (tkn_count <= array->num_elems - 1) {
2413 ret = skl_tplg_get_int_tkn(dev,
Jeeja KPeee0e162017-01-02 09:50:04 +05302414 tkn_elem, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302415 if (ret < 0)
2416 return ret;
2417
2418 tkn_count = tkn_count + ret;
2419 tkn_elem++;
2420 tuple_size += tkn_count *
2421 sizeof(struct snd_soc_tplg_vendor_value_elem);
2422 break;
2423 }
2424 tkn_count = 0;
2425 }
2426
2427 return 0;
2428}
2429
2430/*
2431 * Parse manifest private data for tokens. The private data block is
2432 * preceded by descriptors for type and size of data block.
2433 */
2434static int skl_tplg_get_manifest_data(struct snd_soc_tplg_manifest *manifest,
Jeeja KPeee0e162017-01-02 09:50:04 +05302435 struct device *dev, struct skl *skl)
Shreyas NC541070c2016-08-23 09:31:03 +05302436{
2437 struct snd_soc_tplg_vendor_array *array;
2438 int num_blocks, block_size = 0, block_type, off = 0;
2439 char *data;
2440 int ret;
2441
2442 /* Read the NUM_DATA_BLOCKS descriptor */
2443 array = (struct snd_soc_tplg_vendor_array *)manifest->priv.data;
2444 ret = skl_tplg_get_desc_blocks(dev, array);
2445 if (ret < 0)
2446 return ret;
2447 num_blocks = ret;
2448
2449 off += array->size;
2450 array = (struct snd_soc_tplg_vendor_array *)
2451 (manifest->priv.data + off);
2452
2453 /* Read the BLOCK_TYPE and BLOCK_SIZE descriptor */
2454 while (num_blocks > 0) {
2455 ret = skl_tplg_get_desc_blocks(dev, array);
2456
2457 if (ret < 0)
2458 return ret;
2459 block_type = ret;
2460 off += array->size;
2461
2462 array = (struct snd_soc_tplg_vendor_array *)
2463 (manifest->priv.data + off);
2464
2465 ret = skl_tplg_get_desc_blocks(dev, array);
2466
2467 if (ret < 0)
2468 return ret;
2469 block_size = ret;
2470 off += array->size;
2471
2472 array = (struct snd_soc_tplg_vendor_array *)
2473 (manifest->priv.data + off);
2474
2475 data = (manifest->priv.data + off);
2476
2477 if (block_type == SKL_TYPE_TUPLE) {
Jeeja KPeee0e162017-01-02 09:50:04 +05302478 ret = skl_tplg_get_manifest_tkn(dev, data, skl,
Shreyas NC541070c2016-08-23 09:31:03 +05302479 block_size);
2480
2481 if (ret < 0)
2482 return ret;
2483
2484 --num_blocks;
2485 } else {
2486 return -EINVAL;
2487 }
2488 }
2489
2490 return 0;
2491}
2492
Kranthi G15ecaba92016-07-26 18:06:43 +05302493static int skl_manifest_load(struct snd_soc_component *cmpnt,
2494 struct snd_soc_tplg_manifest *manifest)
2495{
Kranthi G15ecaba92016-07-26 18:06:43 +05302496 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2497 struct hdac_bus *bus = ebus_to_hbus(ebus);
2498 struct skl *skl = ebus_to_skl(ebus);
Kranthi G15ecaba92016-07-26 18:06:43 +05302499
Vinod Koulc15ad602016-08-24 18:03:13 +05302500 /* proceed only if we have private data defined */
2501 if (manifest->priv.size == 0)
2502 return 0;
2503
Jeeja KPeee0e162017-01-02 09:50:04 +05302504 skl_tplg_get_manifest_data(manifest, bus->dev, skl);
Shreyas NC541070c2016-08-23 09:31:03 +05302505
Jeeja KPeee0e162017-01-02 09:50:04 +05302506 if (skl->skl_sst->lib_count > SKL_MAX_LIB) {
Kranthi G15ecaba92016-07-26 18:06:43 +05302507 dev_err(bus->dev, "Exceeding max Library count. Got:%d\n",
Jeeja KPeee0e162017-01-02 09:50:04 +05302508 skl->skl_sst->lib_count);
2509 return -EINVAL;
Kranthi G15ecaba92016-07-26 18:06:43 +05302510 }
2511
Jeeja KPeee0e162017-01-02 09:50:04 +05302512 return 0;
Kranthi G15ecaba92016-07-26 18:06:43 +05302513}
2514
Vinod Koul3af36702015-10-07 11:31:56 +01002515static struct snd_soc_tplg_ops skl_tplg_ops = {
2516 .widget_load = skl_tplg_widget_load,
Jeeja KP140adfb2015-11-28 15:01:50 +05302517 .control_load = skl_tplg_control_load,
2518 .bytes_ext_ops = skl_tlv_ops,
2519 .bytes_ext_ops_count = ARRAY_SIZE(skl_tlv_ops),
Kranthi G15ecaba92016-07-26 18:06:43 +05302520 .manifest = skl_manifest_load,
Vinod Koul3af36702015-10-07 11:31:56 +01002521};
2522
Jeeja KP287af4f2016-06-03 18:29:40 +05302523/*
2524 * A pipe can have multiple modules, each of them will be a DAPM widget as
2525 * well. While managing a pipeline we need to get the list of all the
2526 * widgets in a pipelines, so this helper - skl_tplg_create_pipe_widget_list()
2527 * helps to get the SKL type widgets in that pipeline
2528 */
2529static int skl_tplg_create_pipe_widget_list(struct snd_soc_platform *platform)
2530{
2531 struct snd_soc_dapm_widget *w;
2532 struct skl_module_cfg *mcfg = NULL;
2533 struct skl_pipe_module *p_module = NULL;
2534 struct skl_pipe *pipe;
2535
2536 list_for_each_entry(w, &platform->component.card->widgets, list) {
2537 if (is_skl_dsp_widget_type(w) && w->priv != NULL) {
2538 mcfg = w->priv;
2539 pipe = mcfg->pipe;
2540
2541 p_module = devm_kzalloc(platform->dev,
2542 sizeof(*p_module), GFP_KERNEL);
2543 if (!p_module)
2544 return -ENOMEM;
2545
2546 p_module->w = w;
2547 list_add_tail(&p_module->node, &pipe->w_list);
2548 }
2549 }
2550
2551 return 0;
2552}
2553
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302554static void skl_tplg_set_pipe_type(struct skl *skl, struct skl_pipe *pipe)
2555{
2556 struct skl_pipe_module *w_module;
2557 struct snd_soc_dapm_widget *w;
2558 struct skl_module_cfg *mconfig;
2559 bool host_found = false, link_found = false;
2560
2561 list_for_each_entry(w_module, &pipe->w_list, node) {
2562 w = w_module->w;
2563 mconfig = w->priv;
2564
2565 if (mconfig->dev_type == SKL_DEVICE_HDAHOST)
2566 host_found = true;
2567 else if (mconfig->dev_type != SKL_DEVICE_NONE)
2568 link_found = true;
2569 }
2570
2571 if (host_found && link_found)
2572 pipe->passthru = true;
2573 else
2574 pipe->passthru = false;
2575}
2576
Vinod Koul3af36702015-10-07 11:31:56 +01002577/* This will be read from topology manifest, currently defined here */
2578#define SKL_MAX_MCPS 30000000
2579#define SKL_FW_MAX_MEM 1000000
2580
2581/*
2582 * SKL topology init routine
2583 */
2584int skl_tplg_init(struct snd_soc_platform *platform, struct hdac_ext_bus *ebus)
2585{
2586 int ret;
2587 const struct firmware *fw;
2588 struct hdac_bus *bus = ebus_to_hbus(ebus);
2589 struct skl *skl = ebus_to_skl(ebus);
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302590 struct skl_pipeline *ppl;
Vinod Koul3af36702015-10-07 11:31:56 +01002591
Vinod Koul4b235c42016-02-19 11:42:34 +05302592 ret = request_firmware(&fw, skl->tplg_name, bus->dev);
Vinod Koul3af36702015-10-07 11:31:56 +01002593 if (ret < 0) {
Jeeja KPb663a8c2015-10-07 11:31:57 +01002594 dev_err(bus->dev, "tplg fw %s load failed with %d\n",
Vinod Koul4b235c42016-02-19 11:42:34 +05302595 skl->tplg_name, ret);
2596 ret = request_firmware(&fw, "dfw_sst.bin", bus->dev);
2597 if (ret < 0) {
2598 dev_err(bus->dev, "Fallback tplg fw %s load failed with %d\n",
2599 "dfw_sst.bin", ret);
2600 return ret;
2601 }
Vinod Koul3af36702015-10-07 11:31:56 +01002602 }
2603
2604 /*
2605 * The complete tplg for SKL is loaded as index 0, we don't use
2606 * any other index
2607 */
Jeeja KPb663a8c2015-10-07 11:31:57 +01002608 ret = snd_soc_tplg_component_load(&platform->component,
2609 &skl_tplg_ops, fw, 0);
Vinod Koul3af36702015-10-07 11:31:56 +01002610 if (ret < 0) {
2611 dev_err(bus->dev, "tplg component load failed%d\n", ret);
Sudip Mukherjeec14a82c2016-01-21 17:27:59 +05302612 release_firmware(fw);
Vinod Koul3af36702015-10-07 11:31:56 +01002613 return -EINVAL;
2614 }
2615
2616 skl->resource.max_mcps = SKL_MAX_MCPS;
2617 skl->resource.max_mem = SKL_FW_MAX_MEM;
2618
Vinod Kould8018362016-01-05 17:16:04 +05302619 skl->tplg = fw;
Jeeja KP287af4f2016-06-03 18:29:40 +05302620 ret = skl_tplg_create_pipe_widget_list(platform);
2621 if (ret < 0)
2622 return ret;
Vinod Kould8018362016-01-05 17:16:04 +05302623
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302624 list_for_each_entry(ppl, &skl->ppl_list, node)
2625 skl_tplg_set_pipe_type(skl, ppl->pipe);
Vinod Koul3af36702015-10-07 11:31:56 +01002626
2627 return 0;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +01002628}