blob: 85a423f91960b6e95f3e89158717922e5f51ced7 [file] [log] [blame]
Ralph Metzler43dd07f2011-07-03 13:42:18 -03001#include "drxk_map.h"
2
3#define DRXK_VERSION_MAJOR 0
4#define DRXK_VERSION_MINOR 9
5#define DRXK_VERSION_PATCH 4300
6
7#define HI_I2C_DELAY 42
8#define HI_I2C_BRIDGE_DELAY 350
9#define DRXK_MAX_RETRIES 100
10
11#define DRIVER_4400 1
12
13#define DRXX_JTAGID 0x039210D9
14#define DRXX_J_JTAGID 0x239310D9
15#define DRXX_K_JTAGID 0x039210D9
16
17#define DRX_UNKNOWN 254
18#define DRX_AUTO 255
19
20#define DRX_SCU_READY 0
21#define DRXK_MAX_WAITTIME (200)
22#define SCU_RESULT_OK 0
Mauro Carvalho Chehab75589772011-07-10 13:25:48 -030023#define SCU_RESULT_SIZE -4
24#define SCU_RESULT_INVPAR -3
Ralph Metzler43dd07f2011-07-03 13:42:18 -030025#define SCU_RESULT_UNKSTD -2
26#define SCU_RESULT_UNKCMD -1
27
28#ifndef DRXK_OFDM_TR_SHUTDOWN_TIMEOUT
29#define DRXK_OFDM_TR_SHUTDOWN_TIMEOUT (200)
30#endif
31
32#define DRXK_8VSB_MPEG_BIT_RATE 19392658UL /*bps*/
33#define DRXK_DVBT_MPEG_BIT_RATE 32000000UL /*bps*/
34#define DRXK_QAM16_MPEG_BIT_RATE 27000000UL /*bps*/
35#define DRXK_QAM32_MPEG_BIT_RATE 33000000UL /*bps*/
36#define DRXK_QAM64_MPEG_BIT_RATE 40000000UL /*bps*/
37#define DRXK_QAM128_MPEG_BIT_RATE 46000000UL /*bps*/
38#define DRXK_QAM256_MPEG_BIT_RATE 52000000UL /*bps*/
39#define DRXK_MAX_MPEG_BIT_RATE 52000000UL /*bps*/
40
41#define IQM_CF_OUT_ENA_OFDM__M 0x4
42#define IQM_FS_ADJ_SEL_B_QAM 0x1
43#define IQM_FS_ADJ_SEL_B_OFF 0x0
44#define IQM_FS_ADJ_SEL_B_VSB 0x2
45#define IQM_RC_ADJ_SEL_B_OFF 0x0
46#define IQM_RC_ADJ_SEL_B_QAM 0x1
47#define IQM_RC_ADJ_SEL_B_VSB 0x2
48
49enum OperationMode {
50 OM_NONE,
51 OM_QAM_ITU_A,
52 OM_QAM_ITU_B,
53 OM_QAM_ITU_C,
54 OM_DVBT
55};
56
Oliver Endrissebc7de22011-07-03 13:49:44 -030057enum DRXPowerMode {
Ralph Metzler43dd07f2011-07-03 13:42:18 -030058 DRX_POWER_UP = 0,
59 DRX_POWER_MODE_1,
60 DRX_POWER_MODE_2,
61 DRX_POWER_MODE_3,
62 DRX_POWER_MODE_4,
63 DRX_POWER_MODE_5,
64 DRX_POWER_MODE_6,
65 DRX_POWER_MODE_7,
66 DRX_POWER_MODE_8,
67
68 DRX_POWER_MODE_9,
69 DRX_POWER_MODE_10,
70 DRX_POWER_MODE_11,
71 DRX_POWER_MODE_12,
72 DRX_POWER_MODE_13,
73 DRX_POWER_MODE_14,
74 DRX_POWER_MODE_15,
75 DRX_POWER_MODE_16,
76 DRX_POWER_DOWN = 255
Oliver Endrissebc7de22011-07-03 13:49:44 -030077};
Ralph Metzler43dd07f2011-07-03 13:42:18 -030078
79
80/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */
81#ifndef DRXK_POWER_DOWN_OFDM
82#define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1
83#endif
84
85/** /brief Intermediate power mode for DRXK, power down core (sysclk) */
86#ifndef DRXK_POWER_DOWN_CORE
87#define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9
88#endif
89
90/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */
91#ifndef DRXK_POWER_DOWN_PLL
92#define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10
93#endif
94
95
96enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF };
97enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN };
98enum EDrxkCoefArrayIndex {
99 DRXK_COEF_IDX_MN = 0,
100 DRXK_COEF_IDX_FM ,
101 DRXK_COEF_IDX_L ,
102 DRXK_COEF_IDX_LP ,
103 DRXK_COEF_IDX_BG ,
104 DRXK_COEF_IDX_DK ,
105 DRXK_COEF_IDX_I ,
106 DRXK_COEF_IDX_MAX
107};
108enum EDrxkSifAttenuation {
109 DRXK_SIF_ATTENUATION_0DB,
110 DRXK_SIF_ATTENUATION_3DB,
111 DRXK_SIF_ATTENUATION_6DB,
112 DRXK_SIF_ATTENUATION_9DB
113};
114enum EDrxkConstellation {
115 DRX_CONSTELLATION_BPSK = 0,
116 DRX_CONSTELLATION_QPSK,
117 DRX_CONSTELLATION_PSK8,
118 DRX_CONSTELLATION_QAM16,
119 DRX_CONSTELLATION_QAM32,
120 DRX_CONSTELLATION_QAM64,
121 DRX_CONSTELLATION_QAM128,
122 DRX_CONSTELLATION_QAM256,
123 DRX_CONSTELLATION_QAM512,
124 DRX_CONSTELLATION_QAM1024,
125 DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
126 DRX_CONSTELLATION_AUTO = DRX_AUTO
127};
128enum EDrxkInterleaveMode {
129 DRXK_QAM_I12_J17 = 16,
130 DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN
131};
132enum {
133 DRXK_SPIN_A1 = 0,
134 DRXK_SPIN_A2,
135 DRXK_SPIN_A3,
136 DRXK_SPIN_UNKNOWN
137};
138
139enum DRXKCfgDvbtSqiSpeed {
140 DRXK_DVBT_SQI_SPEED_FAST = 0,
141 DRXK_DVBT_SQI_SPEED_MEDIUM,
142 DRXK_DVBT_SQI_SPEED_SLOW,
143 DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
144} ;
145
146enum DRXFftmode_t {
147 DRX_FFTMODE_2K = 0,
148 DRX_FFTMODE_4K,
149 DRX_FFTMODE_8K,
150 DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
151 DRX_FFTMODE_AUTO = DRX_AUTO
152};
153
154enum DRXMPEGStrWidth_t {
155 DRX_MPEG_STR_WIDTH_1,
156 DRX_MPEG_STR_WIDTH_8
157};
158
159enum DRXQamLockRange_t {
160 DRX_QAM_LOCKRANGE_NORMAL,
161 DRX_QAM_LOCKRANGE_EXTENDED
162};
163
164struct DRXKCfgDvbtEchoThres_t {
165 u16 threshold;
166 enum DRXFftmode_t fftMode;
167} ;
168
Oliver Endrissebc7de22011-07-03 13:49:44 -0300169struct SCfgAgc {
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300170 enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */
171 u16 outputLevel; /* range dependent on AGC */
172 u16 minOutputLevel; /* range dependent on AGC */
173 u16 maxOutputLevel; /* range dependent on AGC */
174 u16 speed; /* range dependent on AGC */
175 u16 top; /* rf-agc take over point */
176 u16 cutOffCurrent; /* rf-agc is accelerated if output current
Oliver Endrissebc7de22011-07-03 13:49:44 -0300177 is below cut-off current */
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300178 u16 IngainTgtMax;
179 u16 FastClipCtrlDelay;
180};
181
Oliver Endrissebc7de22011-07-03 13:49:44 -0300182struct SCfgPreSaw {
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300183 u16 reference; /* pre SAW reference value, range 0 .. 31 */
184 bool usePreSaw; /* TRUE algorithms must use pre SAW sense */
185};
186
Oliver Endrissebc7de22011-07-03 13:49:44 -0300187struct DRXKOfdmScCmd_t {
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300188 u16 cmd; /**< Command number */
189 u16 subcmd; /**< Sub-command parameter*/
190 u16 param0; /**< General purpous param */
191 u16 param1; /**< General purpous param */
192 u16 param2; /**< General purpous param */
193 u16 param3; /**< General purpous param */
194 u16 param4; /**< General purpous param */
195};
196
197struct drxk_state {
198 struct dvb_frontend c_frontend;
199 struct dvb_frontend t_frontend;
200 struct dvb_frontend_parameters param;
201 struct device *dev;
202
203 struct i2c_adapter *i2c;
204 u8 demod_address;
205 void *priv;
206
207 struct mutex mutex;
208 struct mutex ctlock;
209
Oliver Endrissebc7de22011-07-03 13:49:44 -0300210 u32 m_Instance; /**< Channel 1,2,3 or 4 */
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300211
Oliver Endrissebc7de22011-07-03 13:49:44 -0300212 int m_ChunkSize;
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300213 u8 Chunk[256];
214
Oliver Endrissebc7de22011-07-03 13:49:44 -0300215 bool m_hasLNA;
216 bool m_hasDVBT;
217 bool m_hasDVBC;
218 bool m_hasAudio;
219 bool m_hasATV;
220 bool m_hasOOB;
221 bool m_hasSAWSW; /**< TRUE if mat_tx is available */
222 bool m_hasGPIO1; /**< TRUE if mat_rx is available */
223 bool m_hasGPIO2; /**< TRUE if GPIO is available */
224 bool m_hasIRQN; /**< TRUE if IRQN is available */
225 u16 m_oscClockFreq;
226 u16 m_HICfgTimingDiv;
227 u16 m_HICfgBridgeDelay;
228 u16 m_HICfgWakeUpKey;
229 u16 m_HICfgTimeout;
230 u16 m_HICfgCtrl;
231 s32 m_sysClockFreq; /**< system clock frequency in kHz */
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300232
Oliver Endrissebc7de22011-07-03 13:49:44 -0300233 enum EDrxkState m_DrxkState; /**< State of Drxk (init,stopped,started) */
234 enum OperationMode m_OperationMode; /**< digital standards */
235 struct SCfgAgc m_vsbRfAgcCfg; /**< settings for VSB RF-AGC */
236 struct SCfgAgc m_vsbIfAgcCfg; /**< settings for VSB IF-AGC */
237 u16 m_vsbPgaCfg; /**< settings for VSB PGA */
238 struct SCfgPreSaw m_vsbPreSawCfg; /**< settings for pre SAW sense */
239 s32 m_Quality83percent; /**< MER level (*0.1 dB) for 83% quality indication */
240 s32 m_Quality93percent; /**< MER level (*0.1 dB) for 93% quality indication */
241 bool m_smartAntInverted;
242 bool m_bDebugEnableBridge;
243 bool m_bPDownOpenBridge; /**< only open DRXK bridge before power-down once it has been accessed */
244 bool m_bPowerDown; /**< Power down when not used */
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300245
Oliver Endrissebc7de22011-07-03 13:49:44 -0300246 u32 m_IqmFsRateOfs; /**< frequency shift as written to DRXK register (28bit fixpoint) */
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300247
Oliver Endrissebc7de22011-07-03 13:49:44 -0300248 bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */
249 bool m_insertRSByte; /**< If TRUE, insert RS byte */
250 bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */
251 bool m_invertDATA; /**< If TRUE, invert DATA signals */
252 bool m_invertERR; /**< If TRUE, invert ERR signal */
253 bool m_invertSTR; /**< If TRUE, invert STR signals */
254 bool m_invertVAL; /**< If TRUE, invert VAL signals */
255 bool m_invertCLK; /**< If TRUE, invert CLK signals */
256 bool m_DVBCStaticCLK;
257 bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will
258 be used, otherwise clockrate will
259 adapt to the bitrate of the TS */
260 u32 m_DVBTBitrate;
261 u32 m_DVBCBitrate;
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300262
Oliver Endrissebc7de22011-07-03 13:49:44 -0300263 u8 m_TSDataStrength;
264 u8 m_TSClockkStrength;
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300265
Mauro Carvalho Chehab48763e22011-12-09 08:53:36 -0200266 bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */
267
Oliver Endrissebc7de22011-07-03 13:49:44 -0300268 enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width */
269 u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case
270 static clockrate is selected */
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300271
Oliver Endrissebc7de22011-07-03 13:49:44 -0300272 /* LARGE_INTEGER m_StartTime; */ /**< Contains the time of the last demod start */
273 s32 m_MpegLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */
274 s32 m_DemodLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300275
Oliver Endrissebc7de22011-07-03 13:49:44 -0300276 bool m_disableTEIhandling;
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300277
Oliver Endrissebc7de22011-07-03 13:49:44 -0300278 bool m_RfAgcPol;
279 bool m_IfAgcPol;
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300280
Oliver Endrissebc7de22011-07-03 13:49:44 -0300281 struct SCfgAgc m_atvRfAgcCfg; /**< settings for ATV RF-AGC */
282 struct SCfgAgc m_atvIfAgcCfg; /**< settings for ATV IF-AGC */
283 struct SCfgPreSaw m_atvPreSawCfg; /**< settings for ATV pre SAW sense */
284 bool m_phaseCorrectionBypass;
285 s16 m_atvTopVidPeak;
286 u16 m_atvTopNoiseTh;
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300287 enum EDrxkSifAttenuation m_sifAttenuation;
Oliver Endrissebc7de22011-07-03 13:49:44 -0300288 bool m_enableCVBSOutput;
289 bool m_enableSIFOutput;
290 bool m_bMirrorFreqSpect;
291 enum EDrxkConstellation m_Constellation; /**< Constellation type of the channel */
292 u32 m_CurrSymbolRate; /**< Current QAM symbol rate */
293 struct SCfgAgc m_qamRfAgcCfg; /**< settings for QAM RF-AGC */
294 struct SCfgAgc m_qamIfAgcCfg; /**< settings for QAM IF-AGC */
295 u16 m_qamPgaCfg; /**< settings for QAM PGA */
296 struct SCfgPreSaw m_qamPreSawCfg; /**< settings for QAM pre SAW sense */
297 enum EDrxkInterleaveMode m_qamInterleaveMode; /**< QAM Interleave mode */
298 u16 m_fecRsPlen;
299 u16 m_fecRsPrescale;
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300300
301 enum DRXKCfgDvbtSqiSpeed m_sqiSpeed;
302
Oliver Endrissebc7de22011-07-03 13:49:44 -0300303 u16 m_GPIO;
304 u16 m_GPIOCfg;
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300305
Oliver Endrissebc7de22011-07-03 13:49:44 -0300306 struct SCfgAgc m_dvbtRfAgcCfg; /**< settings for QAM RF-AGC */
307 struct SCfgAgc m_dvbtIfAgcCfg; /**< settings for QAM IF-AGC */
308 struct SCfgPreSaw m_dvbtPreSawCfg; /**< settings for QAM pre SAW sense */
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300309
Oliver Endrissebc7de22011-07-03 13:49:44 -0300310 u16 m_agcFastClipCtrlDelay;
311 bool m_adcCompPassed;
312 u16 m_adcCompCoef[64];
313 u16 m_adcState;
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300314
Oliver Endrissebc7de22011-07-03 13:49:44 -0300315 u8 *m_microcode;
316 int m_microcode_length;
317 bool m_DRXK_A1_PATCH_CODE;
318 bool m_DRXK_A1_ROM_CODE;
319 bool m_DRXK_A2_ROM_CODE;
320 bool m_DRXK_A3_ROM_CODE;
321 bool m_DRXK_A2_PATCH_CODE;
322 bool m_DRXK_A3_PATCH_CODE;
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300323
Oliver Endrissebc7de22011-07-03 13:49:44 -0300324 bool m_rfmirror;
325 u8 m_deviceSpin;
326 u32 m_iqmRcRate;
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300327
Oliver Endrissebc7de22011-07-03 13:49:44 -0300328 enum DRXPowerMode m_currentPowerMode;
Mauro Carvalho Chehabe076c922011-07-09 13:06:12 -0300329
Mauro Carvalho Chehab90796ac2011-07-10 09:36:30 -0300330 /*
331 * Configurable parameters at the driver. They stores the values found
332 * at struct drxk_config.
333 */
Mauro Carvalho Chehabe076c922011-07-09 13:06:12 -0300334
Mauro Carvalho Chehab90796ac2011-07-10 09:36:30 -0300335 u16 UIO_mask; /* Bits used by UIO */
Mauro Carvalho Chehab147e1102011-07-10 08:24:26 -0300336
Mauro Carvalho Chehab90796ac2011-07-10 09:36:30 -0300337 bool single_master;
338 bool no_i2c_bridge;
339 bool antenna_dvbt;
340 u16 antenna_gpio;
Mauro Carvalho Chehab147e1102011-07-10 08:24:26 -0300341
Mauro Carvalho Chehabe4f4f872011-07-09 17:35:26 -0300342 const char *microcode_name;
Ralph Metzler43dd07f2011-07-03 13:42:18 -0300343};
344
345#define NEVER_LOCK 0
346#define NOT_LOCKED 1
347#define DEMOD_LOCK 2
348#define FEC_LOCK 3
349#define MPEG_LOCK 4
350