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Nicolas Ferre49fe2ba2011-10-10 18:29:24 +02001/*
2 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
Jean-Christophe PLAGNIOL-VILLARD6db64d22013-05-15 01:21:50 +080010#include "at91sam9g45.dtsi"
Alexandre Belloni66844c72014-03-19 00:15:41 +010011#include <dt-bindings/pwm/pwm.h>
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020012
13/ {
14 model = "Atmel AT91SAM9M10G45-EK";
15 compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
16
17 chosen {
Alexandre Belloniaa070462015-06-03 14:24:10 +020018 bootargs = "mem=64M root=/dev/mtdblock1 rw rootfstype=jffs2";
19 stdout-path = "serial0:115200n8";
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020020 };
21
Ludovic Desrochesdcce6ce2012-04-02 20:44:20 +020022 memory {
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020023 reg = <0x70000000 0x4000000>;
24 };
25
Jean-Christophe PLAGNIOL-VILLARDeb5e76f2012-03-02 20:44:23 +080026 clocks {
Alexandre Belloni4c67a132014-06-13 20:01:51 +020027 slow_xtal {
28 clock-frequency = <32768>;
29 };
30
31 main_xtal {
32 clock-frequency = <12000000>;
33 };
Jean-Christophe PLAGNIOL-VILLARDeb5e76f2012-03-02 20:44:23 +080034 };
35
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020036 ahb {
37 apb {
38 dbgu: serial@ffffee00 {
39 status = "okay";
40 };
41
Alexandre Bellonifb0f84f2016-06-08 18:12:31 +020042 tcb0: timer@fff7c000 {
43 timer@0 {
44 compatible = "atmel,tcb-timer";
45 reg = <0>, <1>;
46 };
47
48 timer@2 {
49 compatible = "atmel,tcb-timer";
50 reg = <2>;
51 };
52 };
53
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020054 usart1: serial@fff90000 {
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +080055 pinctrl-0 =
56 <&pinctrl_usart1
57 &pinctrl_usart1_rts
58 &pinctrl_usart1_cts>;
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +020059 status = "okay";
60 };
Nicolas Ferre0d4f99d2011-12-05 18:03:05 +010061
62 macb0: ethernet@fffbc000 {
63 phy-mode = "rmii";
64 status = "okay";
65 };
Ludovic Desrochesfbc18712012-09-12 08:42:17 +020066
67 i2c0: i2c@fff84000 {
68 status = "okay";
Josh Wu917cdc52015-06-16 18:08:34 +080069 ov2640: camera@30 {
70 compatible = "ovti,ov2640";
71 reg = <0x30>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
74 resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>;
75 pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>;
76 clocks = <&pck1>;
77 clock-names = "xvclk";
78 assigned-clocks = <&pck1>;
79 assigned-clock-rates = <25000000>;
80
81 port {
82 ov2640_0: endpoint {
83 remote-endpoint = <&isi_0>;
84 bus-width = <8>;
85 };
86 };
87 };
Ludovic Desrochesfbc18712012-09-12 08:42:17 +020088 };
89
90 i2c1: i2c@fff88000 {
91 status = "okay";
92 };
Ludovic Desroches4134a452012-11-19 12:24:02 +010093
Wenyou Yangc77bcef2013-05-31 11:11:33 +080094 watchdog@fffffd40 {
95 status = "okay";
96 };
97
Ludovic Desroches4134a452012-11-19 12:24:02 +010098 mmc0: mmc@fff80000 {
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +080099 pinctrl-0 = <
100 &pinctrl_board_mmc0
101 &pinctrl_mmc0_slot0_clk_cmd_dat0
102 &pinctrl_mmc0_slot0_dat1_3>;
Ludovic Desroches4134a452012-11-19 12:24:02 +0100103 status = "okay";
104 slot@0 {
105 reg = <0>;
106 bus-width = <4>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800107 cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>;
Ludovic Desroches4134a452012-11-19 12:24:02 +0100108 };
109 };
110
111 mmc1: mmc@fffd0000 {
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800112 pinctrl-0 = <
113 &pinctrl_board_mmc1
114 &pinctrl_mmc1_slot0_clk_cmd_dat0
115 &pinctrl_mmc1_slot0_dat1_3>;
Ludovic Desroches4134a452012-11-19 12:24:02 +0100116 status = "okay";
117 slot@0 {
118 reg = <0>;
119 bus-width = <4>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800120 cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>;
121 wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>;
Ludovic Desroches4134a452012-11-19 12:24:02 +0100122 };
123 };
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800124
125 pinctrl@fffff200 {
Josh Wu917cdc52015-06-16 18:08:34 +0800126 camera_sensor {
127 pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 {
128 atmel,pins =
129 <AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;
130 };
131
132 pinctrl_sensor_reset: sensor_reset-0 {
133 atmel,pins =
134 <AT91_PIOD 12 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
135 };
136
137 pinctrl_sensor_power: sensor_power-0 {
138 atmel,pins =
139 <AT91_PIOD 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
140 };
141 };
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800142 mmc0 {
143 pinctrl_board_mmc0: mmc0-board {
144 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800145 <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD10 gpio CD pin pull up and deglitch */
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800146 };
147 };
148
149 mmc1 {
150 pinctrl_board_mmc1: mmc1-board {
151 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800152 <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PD11 gpio CD pin pull up and deglitch */
153 AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800154 };
155 };
Bo Sheneed97292013-12-19 11:59:18 +0800156
157 pwm0 {
158 pinctrl_pwm_leds: pwm-led {
159 atmel,pins =
160 <AT91_PIOD 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PD0 periph B */
161 AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PD31 periph B */
162 };
163 };
Jean-Christophe PLAGNIOL-VILLARD199e2ed2012-11-20 00:38:18 +0800164 };
Richard Genoudb6811e92013-04-03 14:03:05 +0800165
166 spi0: spi@fffa4000{
167 status = "okay";
168 cs-gpios = <&pioB 3 0>, <0>, <0>, <0>;
169 mtd_dataflash@0 {
170 compatible = "atmel,at45", "atmel,dataflash";
171 spi-max-frequency = <13000000>;
172 reg = <0>;
173 };
174 };
Jean-Christophe PLAGNIOL-VILLARD24ce10e2013-05-03 20:56:01 +0800175
176 usb2: gadget@fff78000 {
177 atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
178 status = "okay";
179 };
Bo Sheneed97292013-12-19 11:59:18 +0800180
Dmitry Rezvanov2b179392017-06-18 21:40:49 +0900181 ac97: sound@fffac000 {
182 status = "okay";
183 };
184
Alexandre Bellonie10a57e2014-03-19 00:15:40 +0100185 adc0: adc@fffb0000 {
186 pinctrl-names = "default";
187 pinctrl-0 = <
188 &pinctrl_adc0_ad0
189 &pinctrl_adc0_ad1
190 &pinctrl_adc0_ad2
191 &pinctrl_adc0_ad3
192 &pinctrl_adc0_ad4
193 &pinctrl_adc0_ad5
194 &pinctrl_adc0_ad6
195 &pinctrl_adc0_ad7>;
196 atmel,adc-ts-wires = <4>;
197 status = "okay";
198 };
199
Josh Wu917cdc52015-06-16 18:08:34 +0800200 isi@fffb4000 {
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_isi_data_0_7>;
203 status = "okay";
204 port {
205 isi_0: endpoint {
206 remote-endpoint = <&ov2640_0>;
207 bus-width = <8>;
Josh Wubc81beb2015-09-18 19:28:22 +0800208 vsync-active = <1>;
209 hsync-active = <1>;
Josh Wu917cdc52015-06-16 18:08:34 +0800210 };
211 };
212 };
213
Bo Sheneed97292013-12-19 11:59:18 +0800214 pwm0: pwm@fffb8000 {
215 status = "okay";
216
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_pwm_leds>;
219 };
Erik van Luijk4dd79332014-09-02 12:52:12 +0200220
Boris Brezillon199ec7a2014-11-14 11:08:52 +0100221 rtc@fffffd20 {
222 atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
223 status = "okay";
224 };
225
226 gpbr: syscon@fffffd60 {
227 status = "okay";
228 };
229
Erik van Luijk4dd79332014-09-02 12:52:12 +0200230 rtc@fffffdb0 {
231 status = "okay";
232 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200233 };
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800234
Mathieu Malaterreed4ced02017-12-15 13:46:26 +0100235 fb0: fb@500000 {
Jean-Christophe PLAGNIOL-VILLARDf4390a72013-03-29 02:11:22 +0800236 display = <&display0>;
237 status = "okay";
238
239 display0: display {
240 bits-per-pixel = <32>;
241 atmel,lcdcon-backlight;
242 atmel,dmacon = <0x1>;
243 atmel,lcdcon2 = <0x80008002>;
244 atmel,guard-time = <9>;
245 atmel,lcd-wiring-mode = "RGB";
246
247 display-timings {
248 native-mode = <&timing0>;
249 timing0: timing0 {
250 clock-frequency = <9000000>;
251 hactive = <480>;
252 vactive = <272>;
253 hback-porch = <1>;
254 hfront-porch = <1>;
255 vback-porch = <40>;
256 vfront-porch = <1>;
257 hsync-len = <45>;
258 vsync-len = <1>;
259 };
260 };
261 };
262 };
263
Boris Brezillon1004a292017-05-30 11:20:53 +0200264 ebi: ebi@10000000 {
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800265 status = "okay";
266
Boris Brezillon1004a292017-05-30 11:20:53 +0200267 nand_controller: nand-controller {
268 status = "okay";
269 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
270 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800271
Boris Brezillon1004a292017-05-30 11:20:53 +0200272 nand@3 {
273 reg = <0x3 0x0 0x800000>;
274 rb-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>;
275 cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
276 nand-bus-width = <8>;
277 nand-ecc-mode = "soft";
278 nand-on-flash-bbt;
279 label = "atmel_nand";
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800280
Boris Brezillon1004a292017-05-30 11:20:53 +0200281 partitions {
282 compatible = "fixed-partitions";
283 #address-cells = <1>;
284 #size-cells = <1>;
285
286 boot@0 {
287 label = "bootstrap/uboot/kernel";
288 reg = <0x0 0x400000>;
289 };
290
291 rootfs@400000 {
292 label = "rootfs";
293 reg = <0x400000 0x3C00000>;
294 };
295
296 data@4000000 {
297 label = "data";
298 reg = <0x4000000 0xC000000>;
299 };
300 };
301 };
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800302 };
Jean-Christophe PLAGNIOL-VILLARD6a062452011-11-21 06:55:18 +0800303 };
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800304
Rob Herring8dccafa2017-10-13 12:54:51 -0500305 usb0: ohci@700000 {
Jean-Christophe PLAGNIOL-VILLARD6a062452011-11-21 06:55:18 +0800306 status = "okay";
307 num-ports = <2>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800308 atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW
309 &pioD 3 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARDd6a01662012-01-26 02:11:06 +0800310 };
Jean-Christophe PLAGNIOL-VILLARD62c55532011-11-22 12:11:13 +0800311
Rob Herring8dccafa2017-10-13 12:54:51 -0500312 usb1: ehci@800000 {
Jean-Christophe PLAGNIOL-VILLARD62c55532011-11-22 12:11:13 +0800313 status = "okay";
314 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200315 };
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800316
317 leds {
318 compatible = "gpio-leds";
319
320 d8 {
321 label = "d8";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800322 gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800323 linux,default-trigger = "heartbeat";
324 };
Bo Sheneed97292013-12-19 11:59:18 +0800325 };
326
327 pwmleds {
328 compatible = "pwm-leds";
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800329
330 d6 {
331 label = "d6";
Alexandre Belloni66844c72014-03-19 00:15:41 +0100332 pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>;
Bo Sheneed97292013-12-19 11:59:18 +0800333 max-brightness = <255>;
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800334 linux,default-trigger = "nand-disk";
335 };
336
337 d7 {
338 label = "d7";
Alexandre Belloni66844c72014-03-19 00:15:41 +0100339 pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>;
Bo Sheneed97292013-12-19 11:59:18 +0800340 max-brightness = <255>;
Jean-Christophe PLAGNIOL-VILLARDf2ee7ac2012-02-04 12:26:01 +0800341 linux,default-trigger = "mmc0";
342 };
343 };
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800344
345 gpio_keys {
346 compatible = "gpio-keys";
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800347
348 left_click {
349 label = "left_click";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800350 gpios = <&pioB 6 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800351 linux,code = <272>;
Sudeep Holla67ae8b92015-10-21 11:10:07 +0100352 wakeup-source;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800353 };
354
355 right_click {
356 label = "right_click";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800357 gpios = <&pioB 7 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800358 linux,code = <273>;
Sudeep Holla67ae8b92015-10-21 11:10:07 +0100359 wakeup-source;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800360 };
361
362 left {
363 label = "Joystick Left";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800364 gpios = <&pioB 14 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800365 linux,code = <105>;
366 };
367
368 right {
369 label = "Joystick Right";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800370 gpios = <&pioB 15 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800371 linux,code = <106>;
372 };
373
374 up {
375 label = "Joystick Up";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800376 gpios = <&pioB 16 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800377 linux,code = <103>;
378 };
379
380 down {
381 label = "Joystick Down";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800382 gpios = <&pioB 17 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800383 linux,code = <108>;
384 };
385
386 enter {
387 label = "Joystick Press";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800388 gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
Jean-Christophe PLAGNIOL-VILLARD8a087b02012-02-04 12:42:35 +0800389 linux,code = <28>;
390 };
391 };
Nicolas Ferre49fe2ba2011-10-10 18:29:24 +0200392};