Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 1 | /* |
| 2 | * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board |
| 3 | * |
| 4 | * Copyright (C) 2011 Atmel, |
| 5 | * 2011 Nicolas Ferre <nicolas.ferre@atmel.com> |
| 6 | * |
| 7 | * Licensed under GPLv2 or later. |
| 8 | */ |
| 9 | /dts-v1/; |
Jean-Christophe PLAGNIOL-VILLARD | 6db64d2 | 2013-05-15 01:21:50 +0800 | [diff] [blame] | 10 | #include "at91sam9g45.dtsi" |
Alexandre Belloni | 66844c7 | 2014-03-19 00:15:41 +0100 | [diff] [blame] | 11 | #include <dt-bindings/pwm/pwm.h> |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 12 | |
| 13 | / { |
| 14 | model = "Atmel AT91SAM9M10G45-EK"; |
| 15 | compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9"; |
| 16 | |
| 17 | chosen { |
Alexandre Belloni | aa07046 | 2015-06-03 14:24:10 +0200 | [diff] [blame] | 18 | bootargs = "mem=64M root=/dev/mtdblock1 rw rootfstype=jffs2"; |
| 19 | stdout-path = "serial0:115200n8"; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 20 | }; |
| 21 | |
Ludovic Desroches | dcce6ce | 2012-04-02 20:44:20 +0200 | [diff] [blame] | 22 | memory { |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 23 | reg = <0x70000000 0x4000000>; |
| 24 | }; |
| 25 | |
Jean-Christophe PLAGNIOL-VILLARD | eb5e76f | 2012-03-02 20:44:23 +0800 | [diff] [blame] | 26 | clocks { |
Alexandre Belloni | 4c67a13 | 2014-06-13 20:01:51 +0200 | [diff] [blame] | 27 | slow_xtal { |
| 28 | clock-frequency = <32768>; |
| 29 | }; |
| 30 | |
| 31 | main_xtal { |
| 32 | clock-frequency = <12000000>; |
| 33 | }; |
Jean-Christophe PLAGNIOL-VILLARD | eb5e76f | 2012-03-02 20:44:23 +0800 | [diff] [blame] | 34 | }; |
| 35 | |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 36 | ahb { |
| 37 | apb { |
| 38 | dbgu: serial@ffffee00 { |
| 39 | status = "okay"; |
| 40 | }; |
| 41 | |
Alexandre Belloni | fb0f84f | 2016-06-08 18:12:31 +0200 | [diff] [blame] | 42 | tcb0: timer@fff7c000 { |
| 43 | timer@0 { |
| 44 | compatible = "atmel,tcb-timer"; |
| 45 | reg = <0>, <1>; |
| 46 | }; |
| 47 | |
| 48 | timer@2 { |
| 49 | compatible = "atmel,tcb-timer"; |
| 50 | reg = <2>; |
| 51 | }; |
| 52 | }; |
| 53 | |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 54 | usart1: serial@fff90000 { |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 55 | pinctrl-0 = |
| 56 | <&pinctrl_usart1 |
| 57 | &pinctrl_usart1_rts |
| 58 | &pinctrl_usart1_cts>; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 59 | status = "okay"; |
| 60 | }; |
Nicolas Ferre | 0d4f99d | 2011-12-05 18:03:05 +0100 | [diff] [blame] | 61 | |
| 62 | macb0: ethernet@fffbc000 { |
| 63 | phy-mode = "rmii"; |
| 64 | status = "okay"; |
| 65 | }; |
Ludovic Desroches | fbc1871 | 2012-09-12 08:42:17 +0200 | [diff] [blame] | 66 | |
| 67 | i2c0: i2c@fff84000 { |
| 68 | status = "okay"; |
Josh Wu | 917cdc5 | 2015-06-16 18:08:34 +0800 | [diff] [blame] | 69 | ov2640: camera@30 { |
| 70 | compatible = "ovti,ov2640"; |
| 71 | reg = <0x30>; |
| 72 | pinctrl-names = "default"; |
| 73 | pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; |
| 74 | resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>; |
| 75 | pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>; |
| 76 | clocks = <&pck1>; |
| 77 | clock-names = "xvclk"; |
| 78 | assigned-clocks = <&pck1>; |
| 79 | assigned-clock-rates = <25000000>; |
| 80 | |
| 81 | port { |
| 82 | ov2640_0: endpoint { |
| 83 | remote-endpoint = <&isi_0>; |
| 84 | bus-width = <8>; |
| 85 | }; |
| 86 | }; |
| 87 | }; |
Ludovic Desroches | fbc1871 | 2012-09-12 08:42:17 +0200 | [diff] [blame] | 88 | }; |
| 89 | |
| 90 | i2c1: i2c@fff88000 { |
| 91 | status = "okay"; |
| 92 | }; |
Ludovic Desroches | 4134a45 | 2012-11-19 12:24:02 +0100 | [diff] [blame] | 93 | |
Wenyou Yang | c77bcef | 2013-05-31 11:11:33 +0800 | [diff] [blame] | 94 | watchdog@fffffd40 { |
| 95 | status = "okay"; |
| 96 | }; |
| 97 | |
Ludovic Desroches | 4134a45 | 2012-11-19 12:24:02 +0100 | [diff] [blame] | 98 | mmc0: mmc@fff80000 { |
Jean-Christophe PLAGNIOL-VILLARD | 199e2ed | 2012-11-20 00:38:18 +0800 | [diff] [blame] | 99 | pinctrl-0 = < |
| 100 | &pinctrl_board_mmc0 |
| 101 | &pinctrl_mmc0_slot0_clk_cmd_dat0 |
| 102 | &pinctrl_mmc0_slot0_dat1_3>; |
Ludovic Desroches | 4134a45 | 2012-11-19 12:24:02 +0100 | [diff] [blame] | 103 | status = "okay"; |
| 104 | slot@0 { |
| 105 | reg = <0>; |
| 106 | bus-width = <4>; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 107 | cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>; |
Ludovic Desroches | 4134a45 | 2012-11-19 12:24:02 +0100 | [diff] [blame] | 108 | }; |
| 109 | }; |
| 110 | |
| 111 | mmc1: mmc@fffd0000 { |
Jean-Christophe PLAGNIOL-VILLARD | 199e2ed | 2012-11-20 00:38:18 +0800 | [diff] [blame] | 112 | pinctrl-0 = < |
| 113 | &pinctrl_board_mmc1 |
| 114 | &pinctrl_mmc1_slot0_clk_cmd_dat0 |
| 115 | &pinctrl_mmc1_slot0_dat1_3>; |
Ludovic Desroches | 4134a45 | 2012-11-19 12:24:02 +0100 | [diff] [blame] | 116 | status = "okay"; |
| 117 | slot@0 { |
| 118 | reg = <0>; |
| 119 | bus-width = <4>; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 120 | cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>; |
| 121 | wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; |
Ludovic Desroches | 4134a45 | 2012-11-19 12:24:02 +0100 | [diff] [blame] | 122 | }; |
| 123 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 199e2ed | 2012-11-20 00:38:18 +0800 | [diff] [blame] | 124 | |
| 125 | pinctrl@fffff200 { |
Josh Wu | 917cdc5 | 2015-06-16 18:08:34 +0800 | [diff] [blame] | 126 | camera_sensor { |
| 127 | pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 { |
| 128 | atmel,pins = |
| 129 | <AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; |
| 130 | }; |
| 131 | |
| 132 | pinctrl_sensor_reset: sensor_reset-0 { |
| 133 | atmel,pins = |
| 134 | <AT91_PIOD 12 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; |
| 135 | }; |
| 136 | |
| 137 | pinctrl_sensor_power: sensor_power-0 { |
| 138 | atmel,pins = |
| 139 | <AT91_PIOD 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; |
| 140 | }; |
| 141 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 199e2ed | 2012-11-20 00:38:18 +0800 | [diff] [blame] | 142 | mmc0 { |
| 143 | pinctrl_board_mmc0: mmc0-board { |
| 144 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 145 | <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD10 gpio CD pin pull up and deglitch */ |
Jean-Christophe PLAGNIOL-VILLARD | 199e2ed | 2012-11-20 00:38:18 +0800 | [diff] [blame] | 146 | }; |
| 147 | }; |
| 148 | |
| 149 | mmc1 { |
| 150 | pinctrl_board_mmc1: mmc1-board { |
| 151 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c9d0f31 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 152 | <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* PD11 gpio CD pin pull up and deglitch */ |
| 153 | AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */ |
Jean-Christophe PLAGNIOL-VILLARD | 199e2ed | 2012-11-20 00:38:18 +0800 | [diff] [blame] | 154 | }; |
| 155 | }; |
Bo Shen | eed9729 | 2013-12-19 11:59:18 +0800 | [diff] [blame] | 156 | |
| 157 | pwm0 { |
| 158 | pinctrl_pwm_leds: pwm-led { |
| 159 | atmel,pins = |
| 160 | <AT91_PIOD 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PD0 periph B */ |
| 161 | AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PD31 periph B */ |
| 162 | }; |
| 163 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 199e2ed | 2012-11-20 00:38:18 +0800 | [diff] [blame] | 164 | }; |
Richard Genoud | b6811e9 | 2013-04-03 14:03:05 +0800 | [diff] [blame] | 165 | |
| 166 | spi0: spi@fffa4000{ |
| 167 | status = "okay"; |
| 168 | cs-gpios = <&pioB 3 0>, <0>, <0>, <0>; |
| 169 | mtd_dataflash@0 { |
| 170 | compatible = "atmel,at45", "atmel,dataflash"; |
| 171 | spi-max-frequency = <13000000>; |
| 172 | reg = <0>; |
| 173 | }; |
| 174 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 24ce10e | 2013-05-03 20:56:01 +0800 | [diff] [blame] | 175 | |
| 176 | usb2: gadget@fff78000 { |
| 177 | atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>; |
| 178 | status = "okay"; |
| 179 | }; |
Bo Shen | eed9729 | 2013-12-19 11:59:18 +0800 | [diff] [blame] | 180 | |
Dmitry Rezvanov | 2b17939 | 2017-06-18 21:40:49 +0900 | [diff] [blame] | 181 | ac97: sound@fffac000 { |
| 182 | status = "okay"; |
| 183 | }; |
| 184 | |
Alexandre Belloni | e10a57e | 2014-03-19 00:15:40 +0100 | [diff] [blame] | 185 | adc0: adc@fffb0000 { |
| 186 | pinctrl-names = "default"; |
| 187 | pinctrl-0 = < |
| 188 | &pinctrl_adc0_ad0 |
| 189 | &pinctrl_adc0_ad1 |
| 190 | &pinctrl_adc0_ad2 |
| 191 | &pinctrl_adc0_ad3 |
| 192 | &pinctrl_adc0_ad4 |
| 193 | &pinctrl_adc0_ad5 |
| 194 | &pinctrl_adc0_ad6 |
| 195 | &pinctrl_adc0_ad7>; |
| 196 | atmel,adc-ts-wires = <4>; |
| 197 | status = "okay"; |
| 198 | }; |
| 199 | |
Josh Wu | 917cdc5 | 2015-06-16 18:08:34 +0800 | [diff] [blame] | 200 | isi@fffb4000 { |
| 201 | pinctrl-names = "default"; |
| 202 | pinctrl-0 = <&pinctrl_isi_data_0_7>; |
| 203 | status = "okay"; |
| 204 | port { |
| 205 | isi_0: endpoint { |
| 206 | remote-endpoint = <&ov2640_0>; |
| 207 | bus-width = <8>; |
Josh Wu | bc81beb | 2015-09-18 19:28:22 +0800 | [diff] [blame] | 208 | vsync-active = <1>; |
| 209 | hsync-active = <1>; |
Josh Wu | 917cdc5 | 2015-06-16 18:08:34 +0800 | [diff] [blame] | 210 | }; |
| 211 | }; |
| 212 | }; |
| 213 | |
Bo Shen | eed9729 | 2013-12-19 11:59:18 +0800 | [diff] [blame] | 214 | pwm0: pwm@fffb8000 { |
| 215 | status = "okay"; |
| 216 | |
| 217 | pinctrl-names = "default"; |
| 218 | pinctrl-0 = <&pinctrl_pwm_leds>; |
| 219 | }; |
Erik van Luijk | 4dd7933 | 2014-09-02 12:52:12 +0200 | [diff] [blame] | 220 | |
Boris Brezillon | 199ec7a | 2014-11-14 11:08:52 +0100 | [diff] [blame] | 221 | rtc@fffffd20 { |
| 222 | atmel,rtt-rtc-time-reg = <&gpbr 0x0>; |
| 223 | status = "okay"; |
| 224 | }; |
| 225 | |
| 226 | gpbr: syscon@fffffd60 { |
| 227 | status = "okay"; |
| 228 | }; |
| 229 | |
Erik van Luijk | 4dd7933 | 2014-09-02 12:52:12 +0200 | [diff] [blame] | 230 | rtc@fffffdb0 { |
| 231 | status = "okay"; |
| 232 | }; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 233 | }; |
Jean-Christophe PLAGNIOL-VILLARD | d6a0166 | 2012-01-26 02:11:06 +0800 | [diff] [blame] | 234 | |
Mathieu Malaterre | ed4ced0 | 2017-12-15 13:46:26 +0100 | [diff] [blame] | 235 | fb0: fb@500000 { |
Jean-Christophe PLAGNIOL-VILLARD | f4390a7 | 2013-03-29 02:11:22 +0800 | [diff] [blame] | 236 | display = <&display0>; |
| 237 | status = "okay"; |
| 238 | |
| 239 | display0: display { |
| 240 | bits-per-pixel = <32>; |
| 241 | atmel,lcdcon-backlight; |
| 242 | atmel,dmacon = <0x1>; |
| 243 | atmel,lcdcon2 = <0x80008002>; |
| 244 | atmel,guard-time = <9>; |
| 245 | atmel,lcd-wiring-mode = "RGB"; |
| 246 | |
| 247 | display-timings { |
| 248 | native-mode = <&timing0>; |
| 249 | timing0: timing0 { |
| 250 | clock-frequency = <9000000>; |
| 251 | hactive = <480>; |
| 252 | vactive = <272>; |
| 253 | hback-porch = <1>; |
| 254 | hfront-porch = <1>; |
| 255 | vback-porch = <40>; |
| 256 | vfront-porch = <1>; |
| 257 | hsync-len = <45>; |
| 258 | vsync-len = <1>; |
| 259 | }; |
| 260 | }; |
| 261 | }; |
| 262 | }; |
| 263 | |
Boris Brezillon | 1004a29 | 2017-05-30 11:20:53 +0200 | [diff] [blame] | 264 | ebi: ebi@10000000 { |
Jean-Christophe PLAGNIOL-VILLARD | d6a0166 | 2012-01-26 02:11:06 +0800 | [diff] [blame] | 265 | status = "okay"; |
| 266 | |
Boris Brezillon | 1004a29 | 2017-05-30 11:20:53 +0200 | [diff] [blame] | 267 | nand_controller: nand-controller { |
| 268 | status = "okay"; |
| 269 | pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>; |
| 270 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | d6a0166 | 2012-01-26 02:11:06 +0800 | [diff] [blame] | 271 | |
Boris Brezillon | 1004a29 | 2017-05-30 11:20:53 +0200 | [diff] [blame] | 272 | nand@3 { |
| 273 | reg = <0x3 0x0 0x800000>; |
| 274 | rb-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>; |
| 275 | cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; |
| 276 | nand-bus-width = <8>; |
| 277 | nand-ecc-mode = "soft"; |
| 278 | nand-on-flash-bbt; |
| 279 | label = "atmel_nand"; |
Jean-Christophe PLAGNIOL-VILLARD | d6a0166 | 2012-01-26 02:11:06 +0800 | [diff] [blame] | 280 | |
Boris Brezillon | 1004a29 | 2017-05-30 11:20:53 +0200 | [diff] [blame] | 281 | partitions { |
| 282 | compatible = "fixed-partitions"; |
| 283 | #address-cells = <1>; |
| 284 | #size-cells = <1>; |
| 285 | |
| 286 | boot@0 { |
| 287 | label = "bootstrap/uboot/kernel"; |
| 288 | reg = <0x0 0x400000>; |
| 289 | }; |
| 290 | |
| 291 | rootfs@400000 { |
| 292 | label = "rootfs"; |
| 293 | reg = <0x400000 0x3C00000>; |
| 294 | }; |
| 295 | |
| 296 | data@4000000 { |
| 297 | label = "data"; |
| 298 | reg = <0x4000000 0xC000000>; |
| 299 | }; |
| 300 | }; |
| 301 | }; |
Jean-Christophe PLAGNIOL-VILLARD | d6a0166 | 2012-01-26 02:11:06 +0800 | [diff] [blame] | 302 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 6a06245 | 2011-11-21 06:55:18 +0800 | [diff] [blame] | 303 | }; |
Jean-Christophe PLAGNIOL-VILLARD | d6a0166 | 2012-01-26 02:11:06 +0800 | [diff] [blame] | 304 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 305 | usb0: ohci@700000 { |
Jean-Christophe PLAGNIOL-VILLARD | 6a06245 | 2011-11-21 06:55:18 +0800 | [diff] [blame] | 306 | status = "okay"; |
| 307 | num-ports = <2>; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 308 | atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW |
| 309 | &pioD 3 GPIO_ACTIVE_LOW>; |
Jean-Christophe PLAGNIOL-VILLARD | d6a0166 | 2012-01-26 02:11:06 +0800 | [diff] [blame] | 310 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 62c5553 | 2011-11-22 12:11:13 +0800 | [diff] [blame] | 311 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 312 | usb1: ehci@800000 { |
Jean-Christophe PLAGNIOL-VILLARD | 62c5553 | 2011-11-22 12:11:13 +0800 | [diff] [blame] | 313 | status = "okay"; |
| 314 | }; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 315 | }; |
Jean-Christophe PLAGNIOL-VILLARD | f2ee7ac | 2012-02-04 12:26:01 +0800 | [diff] [blame] | 316 | |
| 317 | leds { |
| 318 | compatible = "gpio-leds"; |
| 319 | |
| 320 | d8 { |
| 321 | label = "d8"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 322 | gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; |
Jean-Christophe PLAGNIOL-VILLARD | f2ee7ac | 2012-02-04 12:26:01 +0800 | [diff] [blame] | 323 | linux,default-trigger = "heartbeat"; |
| 324 | }; |
Bo Shen | eed9729 | 2013-12-19 11:59:18 +0800 | [diff] [blame] | 325 | }; |
| 326 | |
| 327 | pwmleds { |
| 328 | compatible = "pwm-leds"; |
Jean-Christophe PLAGNIOL-VILLARD | f2ee7ac | 2012-02-04 12:26:01 +0800 | [diff] [blame] | 329 | |
| 330 | d6 { |
| 331 | label = "d6"; |
Alexandre Belloni | 66844c7 | 2014-03-19 00:15:41 +0100 | [diff] [blame] | 332 | pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>; |
Bo Shen | eed9729 | 2013-12-19 11:59:18 +0800 | [diff] [blame] | 333 | max-brightness = <255>; |
Jean-Christophe PLAGNIOL-VILLARD | f2ee7ac | 2012-02-04 12:26:01 +0800 | [diff] [blame] | 334 | linux,default-trigger = "nand-disk"; |
| 335 | }; |
| 336 | |
| 337 | d7 { |
| 338 | label = "d7"; |
Alexandre Belloni | 66844c7 | 2014-03-19 00:15:41 +0100 | [diff] [blame] | 339 | pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; |
Bo Shen | eed9729 | 2013-12-19 11:59:18 +0800 | [diff] [blame] | 340 | max-brightness = <255>; |
Jean-Christophe PLAGNIOL-VILLARD | f2ee7ac | 2012-02-04 12:26:01 +0800 | [diff] [blame] | 341 | linux,default-trigger = "mmc0"; |
| 342 | }; |
| 343 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 8a087b0 | 2012-02-04 12:42:35 +0800 | [diff] [blame] | 344 | |
| 345 | gpio_keys { |
| 346 | compatible = "gpio-keys"; |
Jean-Christophe PLAGNIOL-VILLARD | 8a087b0 | 2012-02-04 12:42:35 +0800 | [diff] [blame] | 347 | |
| 348 | left_click { |
| 349 | label = "left_click"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 350 | gpios = <&pioB 6 GPIO_ACTIVE_LOW>; |
Jean-Christophe PLAGNIOL-VILLARD | 8a087b0 | 2012-02-04 12:42:35 +0800 | [diff] [blame] | 351 | linux,code = <272>; |
Sudeep Holla | 67ae8b9 | 2015-10-21 11:10:07 +0100 | [diff] [blame] | 352 | wakeup-source; |
Jean-Christophe PLAGNIOL-VILLARD | 8a087b0 | 2012-02-04 12:42:35 +0800 | [diff] [blame] | 353 | }; |
| 354 | |
| 355 | right_click { |
| 356 | label = "right_click"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 357 | gpios = <&pioB 7 GPIO_ACTIVE_LOW>; |
Jean-Christophe PLAGNIOL-VILLARD | 8a087b0 | 2012-02-04 12:42:35 +0800 | [diff] [blame] | 358 | linux,code = <273>; |
Sudeep Holla | 67ae8b9 | 2015-10-21 11:10:07 +0100 | [diff] [blame] | 359 | wakeup-source; |
Jean-Christophe PLAGNIOL-VILLARD | 8a087b0 | 2012-02-04 12:42:35 +0800 | [diff] [blame] | 360 | }; |
| 361 | |
| 362 | left { |
| 363 | label = "Joystick Left"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 364 | gpios = <&pioB 14 GPIO_ACTIVE_LOW>; |
Jean-Christophe PLAGNIOL-VILLARD | 8a087b0 | 2012-02-04 12:42:35 +0800 | [diff] [blame] | 365 | linux,code = <105>; |
| 366 | }; |
| 367 | |
| 368 | right { |
| 369 | label = "Joystick Right"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 370 | gpios = <&pioB 15 GPIO_ACTIVE_LOW>; |
Jean-Christophe PLAGNIOL-VILLARD | 8a087b0 | 2012-02-04 12:42:35 +0800 | [diff] [blame] | 371 | linux,code = <106>; |
| 372 | }; |
| 373 | |
| 374 | up { |
| 375 | label = "Joystick Up"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 376 | gpios = <&pioB 16 GPIO_ACTIVE_LOW>; |
Jean-Christophe PLAGNIOL-VILLARD | 8a087b0 | 2012-02-04 12:42:35 +0800 | [diff] [blame] | 377 | linux,code = <103>; |
| 378 | }; |
| 379 | |
| 380 | down { |
| 381 | label = "Joystick Down"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 382 | gpios = <&pioB 17 GPIO_ACTIVE_LOW>; |
Jean-Christophe PLAGNIOL-VILLARD | 8a087b0 | 2012-02-04 12:42:35 +0800 | [diff] [blame] | 383 | linux,code = <108>; |
| 384 | }; |
| 385 | |
| 386 | enter { |
| 387 | label = "Joystick Press"; |
Jean-Christophe PLAGNIOL-VILLARD | 92f8629 | 2013-04-24 08:34:25 +0800 | [diff] [blame] | 388 | gpios = <&pioB 18 GPIO_ACTIVE_LOW>; |
Jean-Christophe PLAGNIOL-VILLARD | 8a087b0 | 2012-02-04 12:42:35 +0800 | [diff] [blame] | 389 | linux,code = <28>; |
| 390 | }; |
| 391 | }; |
Nicolas Ferre | 49fe2ba | 2011-10-10 18:29:24 +0200 | [diff] [blame] | 392 | }; |